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Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04001/*
2 * keystone2: commands for clocks
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <command.h>
12#include <asm/arch/hardware.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/psc_defs.h>
15
16struct pll_init_data cmd_pll_data = {
Hao Zhang0ecd31e2014-07-16 00:59:23 +030017 .pll = MAIN_PLL,
18 .pll_m = 16,
19 .pll_d = 1,
20 .pll_od = 2,
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040021};
22
23int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
24{
25 if (argc != 5)
26 goto pll_cmd_usage;
27
28 if (strncmp(argv[1], "pa", 2) == 0)
29 cmd_pll_data.pll = PASS_PLL;
Hao Zhang0ecd31e2014-07-16 00:59:23 +030030#ifndef CONFIG_SOC_K2E
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040031 else if (strncmp(argv[1], "arm", 3) == 0)
32 cmd_pll_data.pll = TETRIS_PLL;
Hao Zhang0ecd31e2014-07-16 00:59:23 +030033#endif
34#ifdef CONFIG_SOC_K2HK
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040035 else if (strncmp(argv[1], "ddr3a", 5) == 0)
36 cmd_pll_data.pll = DDR3A_PLL;
37 else if (strncmp(argv[1], "ddr3b", 5) == 0)
38 cmd_pll_data.pll = DDR3B_PLL;
Hao Zhang0ecd31e2014-07-16 00:59:23 +030039#else
40 else if (strncmp(argv[1], "ddr3", 4) == 0)
41 cmd_pll_data.pll = DDR3_PLL;
42#endif
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040043 else
44 goto pll_cmd_usage;
45
46 cmd_pll_data.pll_m = simple_strtoul(argv[2], NULL, 10);
47 cmd_pll_data.pll_d = simple_strtoul(argv[3], NULL, 10);
48 cmd_pll_data.pll_od = simple_strtoul(argv[4], NULL, 10);
49
50 printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
51 cmd_pll_data.pll, cmd_pll_data.pll_m,
52 cmd_pll_data.pll_d, cmd_pll_data.pll_od);
53 init_pll(&cmd_pll_data);
54
55 return 0;
56
57pll_cmd_usage:
58 return cmd_usage(cmdtp);
59}
60
Hao Zhang0ecd31e2014-07-16 00:59:23 +030061U_BOOT_CMD(
62 pllset, 5, 0, do_pll_cmd,
63 "set pll multiplier and pre divider",
Khoronzhuk, Ivan90084ea2014-10-22 16:01:28 +030064 PLLSET_CMD_LIST " <mult> <div> <OD>\n"
Hao Zhang0ecd31e2014-07-16 00:59:23 +030065);
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040066
67int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
68{
69 unsigned int clk;
70 unsigned int freq;
71
72 if (argc != 2)
73 goto getclk_cmd_usage;
74
75 clk = simple_strtoul(argv[1], NULL, 10);
76
77 freq = clk_get_rate(clk);
78 printf("clock index [%d] - frequency %u\n", clk, freq);
79 return 0;
80
81getclk_cmd_usage:
82 return cmd_usage(cmdtp);
83}
84
85U_BOOT_CMD(
86 getclk, 2, 0, do_getclk_cmd,
87 "get clock rate",
88 "<clk index>\n"
Khoronzhuk, Ivan90084ea2014-10-22 16:01:28 +030089 "The indexes for clocks:\n"
90 CLOCK_INDEXES_LIST
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040091);
92
93int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
94{
95 int psc_module;
96 int res;
97
98 if (argc != 3)
99 goto psc_cmd_usage;
100
101 psc_module = simple_strtoul(argv[1], NULL, 10);
102 if (strcmp(argv[2], "en") == 0) {
103 res = psc_enable_module(psc_module);
104 printf("psc_enable_module(%d) - %s\n", psc_module,
105 (res) ? "ERROR" : "OK");
106 return 0;
107 }
108
109 if (strcmp(argv[2], "di") == 0) {
110 res = psc_disable_module(psc_module);
111 printf("psc_disable_module(%d) - %s\n", psc_module,
112 (res) ? "ERROR" : "OK");
113 return 0;
114 }
115
116 if (strcmp(argv[2], "domain") == 0) {
117 res = psc_disable_domain(psc_module);
118 printf("psc_disable_domain(%d) - %s\n", psc_module,
119 (res) ? "ERROR" : "OK");
120 return 0;
121 }
122
123psc_cmd_usage:
124 return cmd_usage(cmdtp);
125}
126
127U_BOOT_CMD(
128 psc, 3, 0, do_psc_cmd,
129 "<enable/disable psc module os disable domain>",
130 "<mod/domain index> <en|di|domain>\n"
Khoronzhuk, Ivan90084ea2014-10-22 16:01:28 +0300131 "Intended to control Power and Sleep Controller (PSC) domains and\n"
132 "modules. The module or domain index exectly corresponds to ones\n"
133 "listed in official TRM. For instance, to enable MSMC RAM clock\n"
134 "domain use command: psc 14 en.\n"
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400135);