Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 1 | /* |
| 2 | * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core |
| 3 | * |
| 4 | * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> |
| 5 | * |
| 6 | * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> |
| 7 | * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> |
Detlev Zundel | f1b3f2b | 2009-05-13 10:54:10 +0200 | [diff] [blame] | 8 | * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 9 | * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> |
| 10 | * Copyright (c) 2003 Kshitij <kshitij@ti.com> |
| 11 | * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> |
| 12 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 13 | * SPDX-License-Identifier: GPL-2.0+ |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 14 | */ |
| 15 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 16 | #include <asm-offsets.h> |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 17 | #include <config.h> |
Aneesh V | 688ee13 | 2011-11-21 23:34:00 +0000 | [diff] [blame] | 18 | #include <asm/system.h> |
Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 19 | #include <linux/linkage.h> |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 20 | |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 21 | /************************************************************************* |
| 22 | * |
| 23 | * Startup Code (reset vector) |
| 24 | * |
Pavel Machek | eb0a0b4 | 2015-04-08 14:15:54 +0200 | [diff] [blame] | 25 | * Do important init only if we don't start from memory! |
| 26 | * Setup memory and board specific bits prior to relocation. |
| 27 | * Relocate armboot to ram. Setup stack. |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 28 | * |
| 29 | *************************************************************************/ |
| 30 | |
Albert ARIBAUD | 9852cc6 | 2014-04-15 16:13:51 +0200 | [diff] [blame] | 31 | .globl reset |
Simon Glass | 47197fe | 2015-02-07 10:47:28 -0700 | [diff] [blame] | 32 | .globl save_boot_params_ret |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 33 | |
| 34 | reset: |
Simon Glass | 47197fe | 2015-02-07 10:47:28 -0700 | [diff] [blame] | 35 | /* Allow the board to save important registers */ |
| 36 | b save_boot_params |
| 37 | save_boot_params_ret: |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 38 | /* |
Andre Przywara | 7acb96b | 2013-04-02 05:43:36 +0000 | [diff] [blame] | 39 | * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, |
| 40 | * except if in HYP mode already |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 41 | */ |
| 42 | mrs r0, cpsr |
Andre Przywara | 7acb96b | 2013-04-02 05:43:36 +0000 | [diff] [blame] | 43 | and r1, r0, #0x1f @ mask mode bits |
| 44 | teq r1, #0x1a @ test for HYP mode |
| 45 | bicne r0, r0, #0x1f @ clear all mode bits |
| 46 | orrne r0, r0, #0x13 @ set SVC mode |
| 47 | orr r0, r0, #0xc0 @ disable FIQ and IRQ |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 48 | msr cpsr,r0 |
| 49 | |
Aneesh V | 688ee13 | 2011-11-21 23:34:00 +0000 | [diff] [blame] | 50 | /* |
| 51 | * Setup vector: |
| 52 | * (OMAP4 spl TEXT_BASE is not 32 byte aligned. |
| 53 | * Continue to use ROM code vector only in OMAP4 spl) |
| 54 | */ |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 55 | #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) |
Peng Fan | 0bd6887 | 2015-01-29 18:03:39 +0800 | [diff] [blame] | 56 | /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ |
| 57 | mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register |
Aneesh V | 688ee13 | 2011-11-21 23:34:00 +0000 | [diff] [blame] | 58 | bic r0, #CR_V @ V = 0 |
Peng Fan | 0bd6887 | 2015-01-29 18:03:39 +0800 | [diff] [blame] | 59 | mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register |
Aneesh V | 688ee13 | 2011-11-21 23:34:00 +0000 | [diff] [blame] | 60 | |
| 61 | /* Set vector address in CP15 VBAR register */ |
| 62 | ldr r0, =_start |
| 63 | mcr p15, 0, r0, c12, c0, 0 @Set VBAR |
| 64 | #endif |
| 65 | |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 66 | /* the mask ROM code should have PLL and others stable */ |
| 67 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
Simon Glass | 277e308 | 2011-11-05 03:56:51 +0000 | [diff] [blame] | 68 | bl cpu_init_cp15 |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 69 | bl cpu_init_crit |
| 70 | #endif |
| 71 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 72 | bl _main |
Heiko Schocher | 56d0a4d | 2010-09-17 13:10:41 +0200 | [diff] [blame] | 73 | |
| 74 | /*------------------------------------------------------------------------------*/ |
| 75 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 76 | ENTRY(c_runtime_cpu_setup) |
Aneesh V | 3e3bc1e | 2011-06-16 23:30:49 +0000 | [diff] [blame] | 77 | /* |
| 78 | * If I-cache is enabled invalidate it |
| 79 | */ |
| 80 | #ifndef CONFIG_SYS_ICACHE_OFF |
| 81 | mcr p15, 0, r0, c7, c5, 0 @ invalidate icache |
| 82 | mcr p15, 0, r0, c7, c10, 4 @ DSB |
| 83 | mcr p15, 0, r0, c7, c5, 4 @ ISB |
| 84 | #endif |
Tetsuyuki Kobayashi | 61c70db | 2012-06-25 02:40:57 +0000 | [diff] [blame] | 85 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 86 | bx lr |
Heiko Schocher | 56d0a4d | 2010-09-17 13:10:41 +0200 | [diff] [blame] | 87 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 88 | ENDPROC(c_runtime_cpu_setup) |
Heiko Schocher | 661a29e | 2010-10-11 14:08:15 +0200 | [diff] [blame] | 89 | |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 90 | /************************************************************************* |
| 91 | * |
Tetsuyuki Kobayashi | 153ba38 | 2012-07-06 21:14:20 +0000 | [diff] [blame] | 92 | * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) |
| 93 | * __attribute__((weak)); |
| 94 | * |
| 95 | * Stack pointer is not yet initialized at this moment |
| 96 | * Don't save anything to stack even if compiled with -O0 |
| 97 | * |
| 98 | *************************************************************************/ |
| 99 | ENTRY(save_boot_params) |
Simon Glass | 47197fe | 2015-02-07 10:47:28 -0700 | [diff] [blame] | 100 | b save_boot_params_ret @ back to my caller |
Tetsuyuki Kobayashi | 153ba38 | 2012-07-06 21:14:20 +0000 | [diff] [blame] | 101 | ENDPROC(save_boot_params) |
| 102 | .weak save_boot_params |
| 103 | |
| 104 | /************************************************************************* |
| 105 | * |
Simon Glass | 277e308 | 2011-11-05 03:56:51 +0000 | [diff] [blame] | 106 | * cpu_init_cp15 |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 107 | * |
Simon Glass | 277e308 | 2011-11-05 03:56:51 +0000 | [diff] [blame] | 108 | * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless |
| 109 | * CONFIG_SYS_ICACHE_OFF is defined. |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 110 | * |
| 111 | *************************************************************************/ |
Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 112 | ENTRY(cpu_init_cp15) |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 113 | /* |
| 114 | * Invalidate L1 I/D |
| 115 | */ |
| 116 | mov r0, #0 @ set up for MCR |
| 117 | mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs |
| 118 | mcr p15, 0, r0, c7, c5, 0 @ invalidate icache |
Aneesh V | 3e3bc1e | 2011-06-16 23:30:49 +0000 | [diff] [blame] | 119 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array |
| 120 | mcr p15, 0, r0, c7, c10, 4 @ DSB |
| 121 | mcr p15, 0, r0, c7, c5, 4 @ ISB |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 122 | |
| 123 | /* |
| 124 | * disable MMU stuff and caches |
| 125 | */ |
| 126 | mrc p15, 0, r0, c1, c0, 0 |
| 127 | bic r0, r0, #0x00002000 @ clear bits 13 (--V-) |
| 128 | bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) |
| 129 | orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align |
Aneesh V | 3e3bc1e | 2011-06-16 23:30:49 +0000 | [diff] [blame] | 130 | orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB |
| 131 | #ifdef CONFIG_SYS_ICACHE_OFF |
| 132 | bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache |
| 133 | #else |
| 134 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache |
| 135 | #endif |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 136 | mcr p15, 0, r0, c1, c0, 0 |
Stephen Warren | e9d59c9 | 2013-02-26 12:28:27 +0000 | [diff] [blame] | 137 | |
Stephen Warren | c63c350 | 2013-03-04 13:29:40 +0000 | [diff] [blame] | 138 | #ifdef CONFIG_ARM_ERRATA_716044 |
| 139 | mrc p15, 0, r0, c1, c0, 0 @ read system control register |
| 140 | orr r0, r0, #1 << 11 @ set bit #11 |
| 141 | mcr p15, 0, r0, c1, c0, 0 @ write system control register |
| 142 | #endif |
| 143 | |
Nitin Garg | 7f17aed | 2014-04-02 08:55:01 -0500 | [diff] [blame] | 144 | #if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) |
Stephen Warren | e9d59c9 | 2013-02-26 12:28:27 +0000 | [diff] [blame] | 145 | mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register |
| 146 | orr r0, r0, #1 << 4 @ set bit #4 |
| 147 | mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register |
| 148 | #endif |
| 149 | |
| 150 | #ifdef CONFIG_ARM_ERRATA_743622 |
| 151 | mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register |
| 152 | orr r0, r0, #1 << 6 @ set bit #6 |
| 153 | mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register |
| 154 | #endif |
| 155 | |
| 156 | #ifdef CONFIG_ARM_ERRATA_751472 |
| 157 | mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register |
| 158 | orr r0, r0, #1 << 11 @ set bit #11 |
| 159 | mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register |
| 160 | #endif |
Nitin Garg | 245defa | 2014-04-02 08:55:02 -0500 | [diff] [blame] | 161 | #ifdef CONFIG_ARM_ERRATA_761320 |
| 162 | mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register |
| 163 | orr r0, r0, #1 << 21 @ set bit #21 |
| 164 | mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register |
| 165 | #endif |
Stephen Warren | e9d59c9 | 2013-02-26 12:28:27 +0000 | [diff] [blame] | 166 | |
Nishanth Menon | aa0294e | 2015-03-09 17:11:59 -0500 | [diff] [blame] | 167 | mov r5, lr @ Store my Caller |
| 168 | mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) |
| 169 | mov r3, r1, lsr #20 @ get variant field |
| 170 | and r3, r3, #0xf @ r3 has CPU variant |
| 171 | and r4, r1, #0xf @ r4 has CPU revision |
| 172 | mov r2, r3, lsl #4 @ shift variant field for combined value |
| 173 | orr r2, r4, r2 @ r2 has combined CPU variant + revision |
| 174 | |
| 175 | #ifdef CONFIG_ARM_ERRATA_798870 |
| 176 | cmp r2, #0x30 @ Applies to lower than R3p0 |
| 177 | bge skip_errata_798870 @ skip if not affected rev |
| 178 | cmp r2, #0x20 @ Applies to including and above R2p0 |
| 179 | blt skip_errata_798870 @ skip if not affected rev |
| 180 | |
| 181 | mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg |
| 182 | orr r0, r0, #1 << 7 @ Enable hazard-detect timeout |
| 183 | push {r1-r5} @ Save the cpu info registers |
| 184 | bl v7_arch_cp15_set_l2aux_ctrl |
| 185 | isb @ Recommended ISB after l2actlr update |
| 186 | pop {r1-r5} @ Restore the cpu info - fall through |
| 187 | skip_errata_798870: |
| 188 | #endif |
| 189 | |
Nishanth Menon | 071d6ce | 2015-03-09 17:12:00 -0500 | [diff] [blame] | 190 | #ifdef CONFIG_ARM_ERRATA_454179 |
| 191 | cmp r2, #0x21 @ Only on < r2p1 |
| 192 | bge skip_errata_454179 |
| 193 | |
| 194 | mrc p15, 0, r0, c1, c0, 1 @ Read ACR |
| 195 | orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits |
| 196 | push {r1-r5} @ Save the cpu info registers |
| 197 | bl v7_arch_cp15_set_acr |
| 198 | pop {r1-r5} @ Restore the cpu info - fall through |
| 199 | |
| 200 | skip_errata_454179: |
| 201 | #endif |
| 202 | |
Nishanth Menon | 3f44511 | 2015-03-09 17:12:01 -0500 | [diff] [blame] | 203 | #ifdef CONFIG_ARM_ERRATA_430973 |
| 204 | cmp r2, #0x21 @ Only on < r2p1 |
| 205 | bge skip_errata_430973 |
| 206 | |
| 207 | mrc p15, 0, r0, c1, c0, 1 @ Read ACR |
| 208 | orr r0, r0, #(0x1 << 6) @ Set IBE bit |
| 209 | push {r1-r5} @ Save the cpu info registers |
| 210 | bl v7_arch_cp15_set_acr |
| 211 | pop {r1-r5} @ Restore the cpu info - fall through |
| 212 | |
| 213 | skip_errata_430973: |
| 214 | #endif |
| 215 | |
Nishanth Menon | 49db62d | 2015-03-09 17:12:02 -0500 | [diff] [blame] | 216 | #ifdef CONFIG_ARM_ERRATA_621766 |
| 217 | cmp r2, #0x21 @ Only on < r2p1 |
| 218 | bge skip_errata_621766 |
| 219 | |
| 220 | mrc p15, 0, r0, c1, c0, 1 @ Read ACR |
| 221 | orr r0, r0, #(0x1 << 5) @ Set L1NEON bit |
| 222 | push {r1-r5} @ Save the cpu info registers |
| 223 | bl v7_arch_cp15_set_acr |
| 224 | pop {r1-r5} @ Restore the cpu info - fall through |
| 225 | |
| 226 | skip_errata_621766: |
| 227 | #endif |
| 228 | |
Nishanth Menon | aa0294e | 2015-03-09 17:11:59 -0500 | [diff] [blame] | 229 | mov pc, r5 @ back to my caller |
Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 230 | ENDPROC(cpu_init_cp15) |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 231 | |
Simon Glass | 277e308 | 2011-11-05 03:56:51 +0000 | [diff] [blame] | 232 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 233 | /************************************************************************* |
| 234 | * |
| 235 | * CPU_init_critical registers |
| 236 | * |
| 237 | * setup important registers |
| 238 | * setup memory timing |
| 239 | * |
| 240 | *************************************************************************/ |
Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 241 | ENTRY(cpu_init_crit) |
Dirk Behme | 7d75a10 | 2008-12-14 09:47:13 +0100 | [diff] [blame] | 242 | /* |
| 243 | * Jump to board specific initialization... |
| 244 | * The Mask ROM will have already initialized |
| 245 | * basic memory. Go here to bump up clock rate and handle |
| 246 | * wake up conditions. |
| 247 | */ |
Benoît Thébaudeau | 0a16790 | 2012-08-10 12:05:16 +0000 | [diff] [blame] | 248 | b lowlevel_init @ go setup pll,mux,memory |
Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 249 | ENDPROC(cpu_init_crit) |
Rob Herring | a693287 | 2011-06-28 05:39:38 +0000 | [diff] [blame] | 250 | #endif |