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git01.mediatek.com / filogic / uboot / 78129d93e26c2e8b02e7356f026919882d4350f2 / . / board / freescale / mx31pdk / lowlevel_init.S
blob: 5b35bb47620217eead027678a598fcbf208c94b1 [file] [log] [blame]
Magnus Lilja24f8b412009-07-04 10:31:24 +0200[diff] [blame]1/*
2 * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <config.h>
Stefano Babic78129d92011-03-14 15:43:56 +0100[diff] [blame^]24#include <asm/arch/imx-regs.h>
Magnus Lilja24f8b412009-07-04 10:31:24 +0200[diff] [blame]25#include <asm/macro.h>
26
27.globl lowlevel_init
28lowlevel_init:
29 /* Also setup the Peripheral Port Remap register inside the core */
30 ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
31 mcr p15, 0, r0, c15, c2, 4
32
33 write32 IPU_CONF, IPU_CONF_DI_EN
34 write32 CCM_CCMR, CCM_CCMR_SETUP
35
36 wait_timer 0x40000
37
38 write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
39 write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
40
41 /* Set up clock to 532MHz */
42 write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
43 write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
44
45 write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
46
47 /* Set up MX31 DDR pins */
48 write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
49 write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
50 write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
51 write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
52 write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
53 write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
54 write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
55 write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
56 write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
57 write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
58 write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
59 write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
60 write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
61 write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
62 write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
63 write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
64 write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
65 write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
66 write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
67 write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
68 write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
69 write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
70 write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
71 write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
72 write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
73 write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
74 write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
75
76 /* Set up MX31 DDR Memory Controller */
77 write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
78 write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
79
80 /* Perform DDR init sequence */
81 write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
82 write32 CSD0_BASE | 0x0f00, 0x12344321
83 write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
84 write32 CSD0_BASE, 0x12344321
85 write32 CSD0_BASE, 0x12344321
86 write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
87 write8 CSD0_BASE | 0x00000033, 0xda
88 write8 CSD0_BASE | 0x01000000, 0xff
89 write32 WEIM_ESDCTL0, ESDCTL_RW
90 write32 CSD0_BASE, 0xDEADBEEF
91 write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
92
93 mov pc, lr