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Vikas Manocha33913c52014-11-18 10:42:22 -08001/*
2 * (C) Copyright 2014
3 * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_STV0991_H
9#define __CONFIG_STV0991_H
Vikas Manocha33913c52014-11-18 10:42:22 -080010#define CONFIG_SYS_DCACHE_OFF
Vikas Manocha33913c52014-11-18 10:42:22 -080011#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
12#define CONFIG_BOARD_EARLY_INIT_F
Vikas Manocha32b9e712014-11-18 10:42:23 -080013
Vikas Manocha33913c52014-11-18 10:42:22 -080014#define CONFIG_SYS_CORTEX_R4
15
Vikas Manocha33913c52014-11-18 10:42:22 -080016#define CONFIG_SYS_NO_FLASH
17
18/* ram memory-related information */
19#define CONFIG_NR_DRAM_BANKS 1
20#define PHYS_SDRAM_1 0x00000000
21#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
22#define PHYS_SDRAM_1_SIZE 0x00198000
23
24#define CONFIG_ENV_SIZE 0x10000
Vikas Manochaf6533532015-07-02 18:29:37 -070025#define CONFIG_ENV_IS_IN_SPI_FLASH
26#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
27#define CONFIG_ENV_OFFSET 0x30000
Vikas Manocha33913c52014-11-18 10:42:22 -080028#define CONFIG_ENV_ADDR \
29 (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
30#define CONFIG_SYS_MAXARGS 16
31#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
32
33/* serial port (PL011) configuration */
Vikas Manocha33913c52014-11-18 10:42:22 -080034#define CONFIG_BAUDRATE 115200
Vikas Manocha0860b6a2014-12-01 12:27:54 -080035#define CONFIG_PL01X_SERIAL
Vikas Manocha33913c52014-11-18 10:42:22 -080036
37/* user interface */
Vikas Manocha7f34a692014-11-18 10:42:24 -080038#define CONFIG_SYS_CBSIZE 1024
Vikas Manocha33913c52014-11-18 10:42:22 -080039#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
40 +sizeof(CONFIG_SYS_PROMPT) + 16)
41
42/* MISC */
43#define CONFIG_SYS_LOAD_ADDR 0x00000000
Vikas Manochad70864c2014-12-01 12:27:53 -080044#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
Vikas Manocha33913c52014-11-18 10:42:22 -080045#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
46#define CONFIG_SYS_INIT_SP_OFFSET \
47 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
48/* U-boot Load Address */
49#define CONFIG_SYS_TEXT_BASE 0x00010000
50#define CONFIG_SYS_INIT_SP_ADDR \
51 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
52
Vikas Manocha32b9e712014-11-18 10:42:23 -080053/* GMAC related configs */
54
55#define CONFIG_MII
56#define CONFIG_PHYLIB
Vikas Manocha32b9e712014-11-18 10:42:23 -080057#define CONFIG_DW_ALTDESCRIPTOR
58#define CONFIG_PHY_MICREL
59
60/* Command support defines */
61#define CONFIG_CMD_PING
62#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
63
Vikas Manocha7f34a692014-11-18 10:42:24 -080064#define CONFIG_SYS_MEMTEST_START 0x0000
65#define CONFIG_SYS_MEMTEST_END 1024*1024
66#define CONFIG_CMD_MEMTEST
67
68/* Misc configuration */
69#define CONFIG_SYS_LONGHELP
70#define CONFIG_CMDLINE_EDITING
71
72#define CONFIG_BOOTDELAY 3
73#define CONFIG_BOOTCOMMAND "go 0x40040000"
Stefan Roese83da3f12015-05-18 14:08:23 +020074
Vikas Manocha41b47012015-05-03 14:10:34 -070075#define CONFIG_OF_LIBFDT
Vikas Manocha8cc062f2015-07-02 18:29:41 -070076
77/*
78+ * QSPI support
79+ */
80#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
Vikas Manocha8cc062f2015-07-02 18:29:41 -070081#define CONFIG_CQSPI_DECODER 0
82#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
83#define CONFIG_CMD_SPI
84
Vikas Manocha8cc062f2015-07-02 18:29:41 -070085#define CONFIG_CMD_SF
86#endif
87
Vikas Manocha33913c52014-11-18 10:42:22 -080088#endif /* __CONFIG_H */