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git01.mediatek.com / filogic / uboot / 77e0a8f912d50cf08703c08c2eb78f343f6f3ccb / . / arch / x86 / lib / fsp2 / fsp_meminit.c
blob: 022e2cb64e5a52509613bc82aee67b7b97bb85e1 [file] [log] [blame]
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]1// SPDX-License-Identifier: Intel
2/*
3 * Copyright (C) 2015-2016 Intel Corp.
4 * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
5 * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
6 * Mostly taken from coreboot fsp2_0/memory_init.c
7 */
8
9#include <common.h>
10#include <binman.h>
Simon Glass1ea97892020-05-10 11:40:00 -0600[diff] [blame]11#include <bootstage.h>
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]12#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]13#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]14#include <asm/global_data.h>
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]15#include <asm/mrccache.h>
16#include <asm/fsp/fsp_infoheader.h>
17#include <asm/fsp2/fsp_api.h>
18#include <asm/fsp2/fsp_internal.h>
19#include <asm/arch/fsp/fsp_configs.h>
20#include <asm/arch/fsp/fsp_m_upd.h>
21
22static int prepare_mrc_cache_type(enum mrc_type_t type,
23 struct mrc_data_container **cachep)
24{
25 struct mrc_data_container *cache;
26 struct mrc_region entry;
27 int ret;
28
29 ret = mrccache_get_region(type, NULL, &entry);
30 if (ret)
31 return ret;
32 cache = mrccache_find_current(&entry);
33 if (!cache)
34 return -ENOENT;
35
36 log_debug("MRC at %x, size %x\n", (uint)cache->data, cache->data_size);
37 *cachep = cache;
38
39 return 0;
40}
41
42int prepare_mrc_cache(struct fspm_upd *upd)
43{
44 struct mrc_data_container *cache;
45 int ret;
46
47 ret = prepare_mrc_cache_type(MRC_TYPE_NORMAL, &cache);
48 if (ret)
49 return log_msg_ret("Cannot get normal cache", ret);
50 upd->arch.nvs_buffer_ptr = cache->data;
51
52 ret = prepare_mrc_cache_type(MRC_TYPE_VAR, &cache);
53 if (ret)
54 return log_msg_ret("Cannot get var cache", ret);
55 upd->config.variable_nvs_buffer_ptr = cache->data;
56
57 return 0;
58}
59
60int fsp_memory_init(bool s3wake, bool use_spi_flash)
61{
62 struct fspm_upd upd, *fsp_upd;
63 fsp_memory_init_func func;
64 struct binman_entry entry;
65 struct fsp_header *hdr;
66 struct hob_header *hob;
67 struct udevice *dev;
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]68 int delay;
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]69 int ret;
70
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]71 log_debug("Locating FSP\n");
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]72 ret = fsp_locate_fsp(FSP_M, &entry, use_spi_flash, &dev, &hdr, NULL);
73 if (ret)
74 return log_msg_ret("locate FSP", ret);
75 debug("Found FSP_M at %x, size %x\n", hdr->img_base, hdr->img_size);
76
77 /* Copy over the default config */
78 fsp_upd = (struct fspm_upd *)(hdr->img_base + hdr->cfg_region_off);
79 if (fsp_upd->header.signature != FSPM_UPD_SIGNATURE)
80 return log_msg_ret("Bad UPD signature", -EPERM);
81 memcpy(&upd, fsp_upd, sizeof(upd));
82
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]83 delay = dev_read_u32_default(dev, "fspm,training-delay", 0);
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]84 ret = fspm_update_config(dev, &upd);
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]85 if (ret) {
86 if (ret != -ENOENT)
87 return log_msg_ret("Could not setup config", ret);
88 } else {
89 delay = 0;
90 }
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]91
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]92 if (delay)
93 printf("SDRAM training (%d seconds)...", delay);
94 else
95 log_debug("SDRAM init...");
Simon Glassea6a6092020-05-10 11:39:59 -0600[diff] [blame]96 bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_M, "fsp-m");
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]97 func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init);
98 ret = func(&upd, &hob);
Simon Glassea6a6092020-05-10 11:39:59 -0600[diff] [blame]99 bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_M);
Simon Glassc5c4ed62020-07-02 21:12:12 -0600[diff] [blame]100 cpu_reinit_fpu();
Simon Glass1d2a3342020-07-09 18:43:17 -0600[diff] [blame]101 if (delay)
102 printf("done\n");
103 else
104 log_debug("done\n");
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]105 if (ret)
106 return log_msg_ret("SDRAM init fail\n", ret);
107
108 gd->arch.hob_list = hob;
Simon Glass466c7852019-12-06 21:42:18 -0700[diff] [blame]109
110 ret = fspm_done(dev);
111 if (ret)
112 return log_msg_ret("fsm_done\n", ret);
113
114 return 0;
115}