Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) |
| 2 | /* |
| 3 | * Copyright 2020-2021 TQ-Systems GmbH |
| 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | |
| 8 | #include "imx8mm-tqma8mqml.dtsi" |
| 9 | #include "mba8mx.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx"; |
| 13 | compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 14 | chassis-type = "embedded"; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 15 | |
| 16 | aliases { |
| 17 | eeprom0 = &eeprom3; |
| 18 | mmc0 = &usdhc3; |
| 19 | mmc1 = &usdhc2; |
| 20 | mmc2 = &usdhc1; |
| 21 | rtc0 = &pcf85063; |
| 22 | rtc1 = &snvs_rtc; |
| 23 | }; |
| 24 | |
| 25 | reg_usdhc2_vmmc: regulator-vmmc { |
| 26 | compatible = "regulator-fixed"; |
| 27 | pinctrl-names = "default"; |
| 28 | pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; |
| 29 | regulator-name = "VSD_3V3"; |
| 30 | regulator-min-microvolt = <3300000>; |
| 31 | regulator-max-microvolt = <3300000>; |
| 32 | gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; |
| 33 | enable-active-high; |
| 34 | startup-delay-us = <100>; |
| 35 | off-on-delay-us = <12000>; |
| 36 | }; |
| 37 | |
| 38 | connector { |
| 39 | compatible = "gpio-usb-b-connector", "usb-b-connector"; |
| 40 | type = "micro"; |
| 41 | label = "X19"; |
| 42 | pinctrl-names = "default"; |
| 43 | pinctrl-0 = <&pinctrl_usb1_connector>; |
| 44 | id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; |
| 45 | |
| 46 | ports { |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <0>; |
| 49 | |
| 50 | port@0 { |
| 51 | reg = <0>; |
| 52 | usb_dr_connector: endpoint { |
| 53 | remote-endpoint = <&usb1_drd_sw>; |
| 54 | }; |
| 55 | }; |
| 56 | }; |
| 57 | }; |
| 58 | }; |
| 59 | |
| 60 | &i2c1 { |
| 61 | expander2: gpio@27 { |
| 62 | compatible = "nxp,pca9555"; |
| 63 | reg = <0x27>; |
| 64 | gpio-controller; |
| 65 | #gpio-cells = <2>; |
| 66 | vcc-supply = <®_vcc_3v3>; |
| 67 | pinctrl-names = "default"; |
| 68 | pinctrl-0 = <&pinctrl_expander>; |
| 69 | interrupt-parent = <&gpio1>; |
| 70 | interrupts = <9 IRQ_TYPE_EDGE_FALLING>; |
| 71 | interrupt-controller; |
| 72 | #interrupt-cells = <2>; |
| 73 | }; |
| 74 | }; |
| 75 | |
| 76 | &pcie_phy { |
| 77 | clocks = <&pcie0_refclk>; |
| 78 | status = "okay"; |
| 79 | }; |
| 80 | |
| 81 | &pcie0 { |
| 82 | reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; |
| 83 | clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, |
| 84 | <&clk IMX8MM_CLK_PCIE1_AUX>; |
| 85 | assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, |
| 86 | <&clk IMX8MM_CLK_PCIE1_CTRL>; |
| 87 | assigned-clock-rates = <10000000>, <250000000>; |
| 88 | assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, |
| 89 | <&clk IMX8MM_SYS_PLL2_250M>; |
| 90 | status = "okay"; |
| 91 | }; |
| 92 | |
| 93 | &sai3 { |
| 94 | assigned-clocks = <&clk IMX8MM_CLK_SAI3>; |
| 95 | assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; |
| 96 | clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; |
| 97 | clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, |
| 98 | <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, |
| 99 | <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, |
| 100 | <&clk IMX8MM_AUDIO_PLL2_OUT>; |
| 101 | }; |
| 102 | |
| 103 | &tlv320aic3x04 { |
| 104 | clock-names = "mclk"; |
| 105 | clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; |
| 106 | }; |
| 107 | |
| 108 | &uart1 { |
| 109 | assigned-clocks = <&clk IMX8MM_CLK_UART1>; |
| 110 | assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; |
| 111 | }; |
| 112 | |
| 113 | &uart2 { |
| 114 | assigned-clocks = <&clk IMX8MM_CLK_UART2>; |
| 115 | assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; |
| 116 | }; |
| 117 | |
| 118 | &usbotg1 { |
| 119 | pinctrl-names = "default"; |
| 120 | pinctrl-0 = <&pinctrl_usbotg1>; |
| 121 | dr_mode = "otg"; |
| 122 | srp-disable; |
| 123 | hnp-disable; |
| 124 | adp-disable; |
| 125 | power-active-high; |
| 126 | over-current-active-low; |
| 127 | usb-role-switch; |
| 128 | status = "okay"; |
| 129 | |
| 130 | port { |
| 131 | usb1_drd_sw: endpoint { |
| 132 | remote-endpoint = <&usb_dr_connector>; |
| 133 | }; |
| 134 | }; |
| 135 | }; |
| 136 | |
| 137 | &usbotg2 { |
| 138 | dr_mode = "host"; |
| 139 | disable-over-current; |
| 140 | vbus-supply = <®_hub_vbus>; |
| 141 | status = "okay"; |
| 142 | }; |
| 143 | |
| 144 | &iomuxc { |
| 145 | pinctrl_ecspi1: ecspi1grp { |
| 146 | fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x00000006>, |
| 147 | <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x00000006>, |
| 148 | <MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x00000006>, |
| 149 | <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00000006>; |
| 150 | }; |
| 151 | |
| 152 | pinctrl_ecspi2: ecspi2grp { |
| 153 | fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x00000006>, |
| 154 | <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x00000006>, |
| 155 | <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x00000006>, |
| 156 | <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00000006>; |
| 157 | }; |
| 158 | |
| 159 | pinctrl_expander: expandergrp { |
| 160 | fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x94>; |
| 161 | }; |
| 162 | |
| 163 | pinctrl_fec1: fec1grp { |
| 164 | fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002>, |
| 165 | <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002>, |
| 166 | <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14>, |
| 167 | <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14>, |
| 168 | <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14>, |
| 169 | <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14>, |
| 170 | <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90>, |
| 171 | <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90>, |
| 172 | <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90>, |
| 173 | <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90>, |
| 174 | <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14>, |
| 175 | <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90>, |
| 176 | <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90>, |
| 177 | <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14>; |
| 178 | }; |
| 179 | |
| 180 | pinctrl_gpiobutton: gpiobuttongrp { |
| 181 | fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x84>, |
| 182 | <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x84>, |
| 183 | <MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x84>; |
| 184 | }; |
| 185 | |
| 186 | pinctrl_gpioled: gpioledgrp { |
| 187 | fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x84>, |
| 188 | <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x84>; |
| 189 | }; |
| 190 | |
| 191 | pinctrl_i2c2: i2c2grp { |
| 192 | fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000004>, |
| 193 | <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000004>; |
| 194 | }; |
| 195 | |
| 196 | pinctrl_i2c2_gpio: i2c2gpiogrp { |
| 197 | fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x40000004>, |
| 198 | <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x40000004>; |
| 199 | }; |
| 200 | |
| 201 | pinctrl_i2c3: i2c3grp { |
| 202 | fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000004>, |
| 203 | <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000004>; |
| 204 | }; |
| 205 | |
| 206 | pinctrl_i2c3_gpio: i2c3gpiogrp { |
| 207 | fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x40000004>, |
| 208 | <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x40000004>; |
| 209 | }; |
| 210 | |
| 211 | pinctrl_pwm3: pwm3grp { |
| 212 | fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x14>; |
| 213 | }; |
| 214 | |
| 215 | pinctrl_pwm4: pwm4grp { |
| 216 | fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x14>; |
| 217 | }; |
| 218 | |
| 219 | pinctrl_sai3: sai3grp { |
| 220 | fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x94>, |
| 221 | <MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x94>, |
| 222 | <MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x94>, |
| 223 | <MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x94>, |
| 224 | <MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x94>, |
| 225 | <MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x94>, |
| 226 | <MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x94>; |
| 227 | }; |
| 228 | |
| 229 | pinctrl_uart1: uart1grp { |
| 230 | fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x16>, |
| 231 | <MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x16>; |
| 232 | }; |
| 233 | |
| 234 | pinctrl_uart2: uart2grp { |
| 235 | fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x16>, |
| 236 | <MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x16>; |
| 237 | }; |
| 238 | |
| 239 | pinctrl_uart3: uart3grp { |
| 240 | fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x16>, |
| 241 | <MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x16>; |
| 242 | }; |
| 243 | |
| 244 | pinctrl_uart4: uart4grp { |
| 245 | fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x16>, |
| 246 | <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x16>; |
| 247 | }; |
| 248 | |
| 249 | pinctrl_usbotg1: usbotg1grp { |
| 250 | fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>, |
| 251 | <MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>; |
| 252 | }; |
| 253 | |
| 254 | pinctrl_usb1_connector: usb1-connectorgrp { |
| 255 | fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c0>; |
| 256 | }; |
| 257 | |
| 258 | pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { |
| 259 | fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x84>; |
| 260 | }; |
| 261 | |
| 262 | pinctrl_usdhc2: usdhc2grp { |
| 263 | fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>, |
| 264 | <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>, |
| 265 | <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, |
| 266 | <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, |
| 267 | <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, |
| 268 | <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, |
| 269 | <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; |
| 270 | }; |
| 271 | |
| 272 | pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { |
| 273 | fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>, |
| 274 | <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>, |
| 275 | <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, |
| 276 | <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, |
| 277 | <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, |
| 278 | <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, |
| 279 | <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; |
| 280 | }; |
| 281 | |
| 282 | pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { |
| 283 | fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>, |
| 284 | <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>, |
| 285 | <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, |
| 286 | <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, |
| 287 | <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, |
| 288 | <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, |
| 289 | <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; |
| 290 | }; |
| 291 | }; |