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git01.mediatek.com / filogic / uboot / 77c3cf1939dab2dcff0be20104c5d546c5541638 / . / dts / upstream / Bindings / iommu / arm,smmu.yaml
blob: a4042ae2477024b0230d7db843c74f6b1da7d732 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM System MMU Architecture Implementation
8
9maintainers:
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
12
13description: |+
14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters external to the CPU.
17
18 The SMMU may also raise interrupts in response to various fault
19 conditions.
20
21properties:
22 $nodename:
23 pattern: "^iommu@[0-9a-f]*"
24 compatible:
25 oneOf:
26 - description: Qcom SoCs implementing "arm,smmu-v2"
27 items:
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
34
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
36 items:
37 - enum:
38 - qcom,qcm2290-smmu-500
39 - qcom,qdu1000-smmu-500
40 - qcom,sa8775p-smmu-500
41 - qcom,sc7180-smmu-500
42 - qcom,sc7280-smmu-500
43 - qcom,sc8180x-smmu-500
44 - qcom,sc8280xp-smmu-500
45 - qcom,sdm670-smmu-500
46 - qcom,sdm845-smmu-500
47 - qcom,sdx55-smmu-500
48 - qcom,sdx65-smmu-500
49 - qcom,sdx75-smmu-500
50 - qcom,sm6115-smmu-500
51 - qcom,sm6125-smmu-500
52 - qcom,sm6350-smmu-500
53 - qcom,sm6375-smmu-500
54 - qcom,sm8150-smmu-500
55 - qcom,sm8250-smmu-500
56 - qcom,sm8350-smmu-500
57 - qcom,sm8450-smmu-500
58 - qcom,sm8550-smmu-500
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]59 - qcom,sm8650-smmu-500
60 - qcom,x1e80100-smmu-500
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]61 - const: qcom,smmu-500
62 - const: arm,mmu-500
63
64 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
65 deprecated: true
66 items:
67 # Do not add additional SoC to this list. Instead use two previous lists.
68 - enum:
69 - qcom,qcm2290-smmu-500
70 - qcom,sc7180-smmu-500
71 - qcom,sc7280-smmu-500
72 - qcom,sc8180x-smmu-500
73 - qcom,sc8280xp-smmu-500
74 - qcom,sdm845-smmu-500
75 - qcom,sm6115-smmu-500
76 - qcom,sm6350-smmu-500
77 - qcom,sm6375-smmu-500
78 - qcom,sm8150-smmu-500
79 - qcom,sm8250-smmu-500
80 - qcom,sm8350-smmu-500
81 - qcom,sm8450-smmu-500
82 - const: arm,mmu-500
83 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
84 items:
85 - enum:
86 - qcom,sa8775p-smmu-500
87 - qcom,sc7280-smmu-500
88 - qcom,sc8280xp-smmu-500
89 - qcom,sm6115-smmu-500
90 - qcom,sm6125-smmu-500
91 - qcom,sm8150-smmu-500
92 - qcom,sm8250-smmu-500
93 - qcom,sm8350-smmu-500
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]94 - qcom,sm8450-smmu-500
95 - qcom,sm8550-smmu-500
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]96 - const: qcom,adreno-smmu
97 - const: qcom,smmu-500
98 - const: arm,mmu-500
99 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
100 deprecated: true
101 items:
102 # Do not add additional SoC to this list. Instead use previous list.
103 - enum:
104 - qcom,sc7280-smmu-500
105 - qcom,sm8150-smmu-500
106 - qcom,sm8250-smmu-500
107 - const: qcom,adreno-smmu
108 - const: arm,mmu-500
109 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
110 items:
111 - enum:
112 - qcom,msm8996-smmu-v2
113 - qcom,sc7180-smmu-v2
114 - qcom,sdm630-smmu-v2
115 - qcom,sdm845-smmu-v2
116 - qcom,sm6350-smmu-v2
117 - qcom,sm7150-smmu-v2
118 - const: qcom,adreno-smmu
119 - const: qcom,smmu-v2
120 - description: Qcom Adreno GPUs on Google Cheza platform
121 items:
122 - const: qcom,sdm845-smmu-v2
123 - const: qcom,smmu-v2
124 - description: Marvell SoCs implementing "arm,mmu-500"
125 items:
126 - const: marvell,ap806-smmu-500
127 - const: arm,mmu-500
128 - description: NVIDIA SoCs that require memory controller interaction
129 and may program multiple ARM MMU-500s identically with the memory
130 controller interleaving translations between multiple instances
131 for improved performance.
132 items:
133 - enum:
134 - nvidia,tegra186-smmu
135 - nvidia,tegra194-smmu
136 - nvidia,tegra234-smmu
137 - const: nvidia,smmu-500
138 - items:
139 - const: arm,mmu-500
140 - const: arm,smmu-v2
141 - items:
142 - enum:
143 - arm,mmu-400
144 - arm,mmu-401
145 - const: arm,smmu-v1
146 - enum:
147 - arm,smmu-v1
148 - arm,smmu-v2
149 - arm,mmu-400
150 - arm,mmu-401
151 - arm,mmu-500
152 - cavium,smmu-v2
153
154 reg:
155 minItems: 1
156 maxItems: 2
157
158 '#global-interrupts':
159 description: The number of global interrupts exposed by the device.
160 $ref: /schemas/types.yaml#/definitions/uint32
161 minimum: 0
162 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
163
164 '#iommu-cells':
165 enum: [ 1, 2 ]
166 description: |
167 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
168 value of 1, each IOMMU specifier represents a distinct stream ID emitted
169 by that device into the relevant SMMU.
170
171 SMMUs with stream matching support and complex masters may use a value of
172 2, where the second cell of the IOMMU specifier represents an SMR mask to
173 combine with the ID in the first cell. Care must be taken to ensure the
174 set of matched IDs does not result in conflicts.
175
176 interrupts:
177 minItems: 1
178 maxItems: 388 # 260 plus 128 contexts
179 description: |
180 Interrupt list, with the first #global-interrupts entries corresponding to
181 the global interrupts and any following entries corresponding to context
182 interrupts, specified in order of their indexing by the SMMU.
183
184 For SMMUv2 implementations, there must be exactly one interrupt per
185 context bank. In the case of a single, combined interrupt, it must be
186 listed multiple times.
187
188 dma-coherent:
189 description: |
190 Present if page table walks made by the SMMU are cache coherent with the
191 CPU.
192
193 NOTE: this only applies to the SMMU itself, not masters connected
194 upstream of the SMMU.
195
196 calxeda,smmu-secure-config-access:
197 type: boolean
198 description:
199 Enable proper handling of buggy implementations that always use secure
200 access to SMMU configuration registers. In this case non-secure aliases of
201 secure registers have to be used during SMMU configuration.
202
203 stream-match-mask:
204 $ref: /schemas/types.yaml#/definitions/uint32
205 description: |
206 For SMMUs supporting stream matching and using #iommu-cells = <1>,
207 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
208 be programmed into the SMRn.MASK field of every stream match register
209 used). For cases where it is desirable to ignore some portion of every
210 Stream ID (e.g. for certain MMU-500 configurations given globally unique
211 input IDs). This property is not valid for SMMUs using stream indexing, or
212 using stream matching with #iommu-cells = <2>, and may be ignored if
213 present in such cases.
214
215 clock-names:
216 minItems: 1
217 maxItems: 7
218
219 clocks:
220 minItems: 1
221 maxItems: 7
222
223 power-domains:
224 minItems: 1
225 maxItems: 3
226
227 nvidia,memory-controller:
228 description: |
229 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
230 The memory controller needs to be programmed with a mapping of memory
231 client IDs to ARM SMMU stream IDs.
232
233 If this property is absent, the mapping programmed by early firmware
234 will be used and it is not guaranteed that IOMMU translations will be
235 enabled for any given device.
236 $ref: /schemas/types.yaml#/definitions/phandle
237
238required:
239 - compatible
240 - reg
241 - '#global-interrupts'
242 - '#iommu-cells'
243 - interrupts
244
245additionalProperties: false
246
247allOf:
248 - if:
249 properties:
250 compatible:
251 contains:
252 enum:
253 - nvidia,tegra186-smmu
254 - nvidia,tegra194-smmu
255 - nvidia,tegra234-smmu
256 then:
257 properties:
258 reg:
259 minItems: 1
260 maxItems: 2
261
262 # The reference to the memory controller is required to ensure that the
263 # memory client to stream ID mapping can be done synchronously with the
264 # IOMMU attachment.
265 required:
266 - nvidia,memory-controller
267 else:
268 properties:
269 reg:
270 maxItems: 1
271
272 - if:
273 properties:
274 compatible:
275 contains:
276 enum:
277 - qcom,msm8998-smmu-v2
278 - qcom,sdm630-smmu-v2
279 then:
280 anyOf:
281 - properties:
282 clock-names:
283 items:
284 - const: bus
285 clocks:
286 items:
287 - description: bus clock required for downstream bus access and for
288 the smmu ptw
289 - properties:
290 clock-names:
291 items:
292 - const: iface
293 - const: mem
294 - const: mem_iface
295 clocks:
296 items:
297 - description: interface clock required to access smmu's registers
298 through the TCU's programming interface.
299 - description: bus clock required for memory access
300 - description: bus clock required for GPU memory access
301 - properties:
302 clock-names:
303 items:
304 - const: iface-mm
305 - const: iface-smmu
306 - const: bus-smmu
307 clocks:
308 items:
309 - description: interface clock required to access mnoc's registers
310 through the TCU's programming interface.
311 - description: interface clock required to access smmu's registers
312 through the TCU's programming interface.
313 - description: bus clock required for the smmu ptw
314
315 - if:
316 properties:
317 compatible:
318 contains:
319 enum:
320 - qcom,sm6375-smmu-v2
321 then:
322 anyOf:
323 - properties:
324 clock-names:
325 items:
326 - const: bus
327 clocks:
328 items:
329 - description: bus clock required for downstream bus access and for
330 the smmu ptw
331 - properties:
332 clock-names:
333 items:
334 - const: iface
335 - const: mem
336 - const: mem_iface
337 clocks:
338 items:
339 - description: interface clock required to access smmu's registers
340 through the TCU's programming interface.
341 - description: bus clock required for memory access
342 - description: bus clock required for GPU memory access
343 - properties:
344 clock-names:
345 items:
346 - const: iface-mm
347 - const: iface-smmu
348 - const: bus-mm
349 - const: bus-smmu
350 clocks:
351 items:
352 - description: interface clock required to access mnoc's registers
353 through the TCU's programming interface.
354 - description: interface clock required to access smmu's registers
355 through the TCU's programming interface.
356 - description: bus clock required for downstream bus access
357 - description: bus clock required for the smmu ptw
358
359 - if:
360 properties:
361 compatible:
362 contains:
363 enum:
364 - qcom,msm8996-smmu-v2
365 - qcom,sc7180-smmu-v2
366 - qcom,sdm845-smmu-v2
367 then:
368 properties:
369 clock-names:
370 items:
371 - const: bus
372 - const: iface
373
374 clocks:
375 items:
376 - description: bus clock required for downstream bus access and for
377 the smmu ptw
378 - description: interface clock required to access smmu's registers
379 through the TCU's programming interface.
380
381 - if:
382 properties:
383 compatible:
384 contains:
385 enum:
386 - qcom,sa8775p-smmu-500
387 - qcom,sc7280-smmu-500
388 - qcom,sc8280xp-smmu-500
389 then:
390 properties:
391 clock-names:
392 items:
393 - const: gcc_gpu_memnoc_gfx_clk
394 - const: gcc_gpu_snoc_dvm_gfx_clk
395 - const: gpu_cc_ahb_clk
396 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
397 - const: gpu_cc_cx_gmu_clk
398 - const: gpu_cc_hub_cx_int_clk
399 - const: gpu_cc_hub_aon_clk
400
401 clocks:
402 items:
403 - description: GPU memnoc_gfx clock
404 - description: GPU snoc_dvm_gfx clock
405 - description: GPU ahb clock
406 - description: GPU hlos1_vote_GPU smmu clock
407 - description: GPU cx_gmu clock
408 - description: GPU hub_cx_int clock
409 - description: GPU hub_aon clock
410
411 - if:
412 properties:
413 compatible:
414 contains:
415 enum:
416 - qcom,sm6350-smmu-v2
417 - qcom,sm7150-smmu-v2
418 - qcom,sm8150-smmu-500
419 - qcom,sm8250-smmu-500
420 then:
421 properties:
422 clock-names:
423 items:
424 - const: ahb
425 - const: bus
426 - const: iface
427
428 clocks:
429 items:
430 - description: bus clock required for AHB bus access
431 - description: bus clock required for downstream bus access and for
432 the smmu ptw
433 - description: interface clock required to access smmu's registers
434 through the TCU's programming interface.
435
436 - if:
437 properties:
438 compatible:
439 items:
440 - enum:
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]441 - qcom,sm8350-smmu-500
442 - const: qcom,adreno-smmu
443 - const: qcom,smmu-500
444 - const: arm,mmu-500
445 then:
446 properties:
447 clock-names:
448 items:
449 - const: bus
450 - const: iface
451 - const: ahb
452 - const: hlos1_vote_gpu_smmu
453 - const: cx_gmu
454 - const: hub_cx_int
455 - const: hub_aon
456 clocks:
457 minItems: 7
458 maxItems: 7
459
460 - if:
461 properties:
462 compatible:
463 items:
464 - enum:
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]465 - qcom,sm6115-smmu-500
466 - qcom,sm6125-smmu-500
467 - const: qcom,adreno-smmu
468 - const: qcom,smmu-500
469 - const: arm,mmu-500
470 then:
471 properties:
472 clock-names:
473 items:
474 - const: mem
475 - const: hlos
476 - const: iface
477
478 clocks:
479 items:
480 - description: GPU memory bus clock
481 - description: Voter clock required for HLOS SMMU access
482 - description: Interface clock required for register access
483
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]484 - if:
485 properties:
486 compatible:
487 const: qcom,sm8450-smmu-500
488 then:
489 properties:
490 clock-names:
491 items:
492 - const: gmu
493 - const: hub
494 - const: hlos
495 - const: bus
496 - const: iface
497 - const: ahb
498
499 clocks:
500 items:
501 - description: GMU clock
502 - description: GPU HUB clock
503 - description: HLOS vote clock
504 - description: GPU memory bus clock
505 - description: GPU SNoC bus clock
506 - description: GPU AHB clock
507
508 - if:
509 properties:
510 compatible:
511 const: qcom,sm8550-smmu-500
512 then:
513 properties:
514 clock-names:
515 items:
516 - const: hlos
517 - const: bus
518 - const: iface
519 - const: ahb
520
521 clocks:
522 items:
523 - description: HLOS vote clock
524 - description: GPU memory bus clock
525 - description: GPU SNoC bus clock
526 - description: GPU AHB clock
527
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]528 # Disallow clocks for all other platforms with specific compatibles
529 - if:
530 properties:
531 compatible:
532 contains:
533 enum:
534 - cavium,smmu-v2
535 - marvell,ap806-smmu-500
536 - nvidia,smmu-500
537 - qcom,qcm2290-smmu-500
538 - qcom,qdu1000-smmu-500
539 - qcom,sc7180-smmu-500
540 - qcom,sc8180x-smmu-500
541 - qcom,sdm670-smmu-500
542 - qcom,sdm845-smmu-500
543 - qcom,sdx55-smmu-500
544 - qcom,sdx65-smmu-500
545 - qcom,sm6350-smmu-500
546 - qcom,sm6375-smmu-500
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]547 - qcom,sm8650-smmu-500
548 - qcom,x1e80100-smmu-500
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]549 then:
550 properties:
551 clock-names: false
552 clocks: false
553
554 - if:
555 properties:
556 compatible:
557 contains:
558 const: qcom,sm6375-smmu-500
559 then:
560 properties:
561 power-domains:
562 items:
563 - description: SNoC MMU TBU RT GDSC
564 - description: SNoC MMU TBU NRT GDSC
565 - description: SNoC TURING MMU TBU0 GDSC
566
567 required:
568 - power-domains
569 else:
570 properties:
571 power-domains:
572 maxItems: 1
573
574examples:
575 - |+
576 /* SMMU with stream matching or stream indexing */
577 smmu1: iommu@ba5e0000 {
578 compatible = "arm,smmu-v1";
579 reg = <0xba5e0000 0x10000>;
580 #global-interrupts = <2>;
581 interrupts = <0 32 4>,
582 <0 33 4>,
583 <0 34 4>, /* This is the first context interrupt */
584 <0 35 4>,
585 <0 36 4>,
586 <0 37 4>;
587 #iommu-cells = <1>;
588 };
589
590 /* device with two stream IDs, 0 and 7 */
591 master1 {
592 iommus = <&smmu1 0>,
593 <&smmu1 7>;
594 };
595
596
597 /* SMMU with stream matching */
598 smmu2: iommu@ba5f0000 {
599 compatible = "arm,smmu-v1";
600 reg = <0xba5f0000 0x10000>;
601 #global-interrupts = <2>;
602 interrupts = <0 38 4>,
603 <0 39 4>,
604 <0 40 4>, /* This is the first context interrupt */
605 <0 41 4>,
606 <0 42 4>,
607 <0 43 4>;
608 #iommu-cells = <2>;
609 };
610
611 /* device with stream IDs 0 and 7 */
612 master2 {
613 iommus = <&smmu2 0 0>,
614 <&smmu2 7 0>;
615 };
616
617 /* device with stream IDs 1, 17, 33 and 49 */
618 master3 {
619 iommus = <&smmu2 1 0x30>;
620 };
621
622
623 /* ARM MMU-500 with 10-bit stream ID input configuration */
624 smmu3: iommu@ba600000 {
625 compatible = "arm,mmu-500", "arm,smmu-v2";
626 reg = <0xba600000 0x10000>;
627 #global-interrupts = <2>;
628 interrupts = <0 44 4>,
629 <0 45 4>,
630 <0 46 4>, /* This is the first context interrupt */
631 <0 47 4>,
632 <0 48 4>,
633 <0 49 4>;
634 #iommu-cells = <1>;
635 /* always ignore appended 5-bit TBU number */
636 stream-match-mask = <0x7c00>;
637 };
638
639 bus {
640 /* bus whose child devices emit one unique 10-bit stream
641 ID each, but may master through multiple SMMU TBUs */
642 iommu-map = <0 &smmu3 0 0x400>;
643
644
645 };
646
647 - |+
648 /* Qcom's arm,smmu-v2 implementation */
649 #include <dt-bindings/interrupt-controller/arm-gic.h>
650 #include <dt-bindings/interrupt-controller/irq.h>
651 smmu4: iommu@d00000 {
652 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
653 reg = <0xd00000 0x10000>;
654
655 #global-interrupts = <1>;
656 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
659 #iommu-cells = <1>;
660 power-domains = <&mmcc 0>;
661
662 clocks = <&mmcc 123>,
663 <&mmcc 124>;
664 clock-names = "bus", "iface";
665 };