blob: 36538e7f96adc75a51638c413b121ac79c4e0194 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Bryan Wu97adb222014-06-24 11:45:29 +09002/*
Alexandre Courbot7f936d42015-07-09 16:33:00 +09003 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
Bryan Wu97adb222014-06-24 11:45:29 +09004 */
5
6/* Tegra vpr routines */
7
8#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Bryan Wu97adb222014-06-24 11:45:29 +090010#include <asm/io.h>
11#include <asm/arch/tegra.h>
12#include <asm/arch/mc.h>
Stephen Warren8eadc5f2018-07-31 12:39:07 -060013#include <asm/arch-tegra/ap.h>
Bryan Wu97adb222014-06-24 11:45:29 +090014
Alexandre Courbot7f936d42015-07-09 16:33:00 +090015#include <fdt_support.h>
16
17static bool _configured;
18
Alexandre Courbotf36729d2015-10-19 13:57:03 +090019void tegra_gpu_config(void)
Bryan Wu97adb222014-06-24 11:45:29 +090020{
21 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
22
Stephen Warren8eadc5f2018-07-31 12:39:07 -060023#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
24 if (!tegra_cpu_is_non_secure())
25#endif
26 {
27 /* Turn VPR off */
28 writel(0, &mc->mc_video_protect_size_mb);
29 writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
30 &mc->mc_video_protect_reg_ctrl);
31 /* read back to ensure the write went through */
32 readl(&mc->mc_video_protect_reg_ctrl);
33 }
Alexandre Courbot7f936d42015-07-09 16:33:00 +090034
35 debug("configured VPR\n");
36
37 _configured = true;
38}
39
Alexandre Courbot5e270dc2015-07-09 16:33:01 +090040#if defined(CONFIG_OF_LIBFDT)
41
Stephen Warrenf4949cd2016-04-12 11:17:39 -060042int tegra_gpu_enable_node(void *blob, const char *compat)
Alexandre Courbot5e270dc2015-07-09 16:33:01 +090043{
44 int offset;
45
Stephen Warrenf4949cd2016-04-12 11:17:39 -060046 if (!_configured)
47 return 0;
48
Marek BehĂșn5d6b4482022-01-20 01:04:42 +010049 fdt_for_each_node_by_compatible(offset, blob, -1, compat)
Stephen Warrenf4949cd2016-04-12 11:17:39 -060050 fdt_status_okay(blob, offset);
Alexandre Courbot5e270dc2015-07-09 16:33:01 +090051
52 return 0;
53}
54
55#endif