blob: bd03f118822a534701324ed04139ba0e83d3714f [file] [log] [blame]
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -07001/**
2 * (C) Copyright 2014, Cavium Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5**/
6
7#ifndef __THUNDERX_88XX_H__
8#define __THUNDERX_88XX_H__
9
10#define CONFIG_REMAKE_ELF
11
12#define CONFIG_THUNDERX
13
14#define CONFIG_SYS_64BIT
15
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070016#define MEM_BASE 0x00500000
17
Sergey Temerkhanov62dce242015-10-14 09:55:51 -070018#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
19
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070020/* Link Definitions */
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070021#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
22
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070023/* SMP Spin Table Definitions */
24#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
25
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070026/* Generic Timer Definitions */
27#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
28
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070029#define CONFIG_SYS_MEMTEST_START MEM_BASE
30#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
31
32/* Size of malloc() pool */
33#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
34
35/* PL011 Serial Configuration */
36
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070037#define CONFIG_PL011_CLOCK 24000000
38#define CONFIG_CONS_INDEX 1
39
40/* Generic Interrupt Controller Definitions */
41#define GICD_BASE (0x801000000000)
42#define GICR_BASE (0x801000002000)
43#define CONFIG_SYS_SERIAL0 0x87e024000000
44#define CONFIG_SYS_SERIAL1 0x87e025000000
45
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070046/* BOOTP options */
47#define CONFIG_BOOTP_BOOTFILESIZE
48#define CONFIG_BOOTP_BOOTPATH
49#define CONFIG_BOOTP_GATEWAY
50#define CONFIG_BOOTP_HOSTNAME
51#define CONFIG_BOOTP_PXE
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070052
53/* Miscellaneous configurable options */
54#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
55
56/* Physical Memory Map */
57#define CONFIG_NR_DRAM_BANKS 1
58#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
59#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
60#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
61
62/* Initial environment variables */
63#define UBOOT_IMG_HEAD_SIZE 0x40
64/* C80000 - 0x40 */
65#define CONFIG_EXTRA_ENV_SETTINGS \
66 "kernel_addr=08007ffc0\0" \
67 "fdt_addr=0x94C00000\0" \
68 "fdt_high=0x9fffffff\0"
69
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070070/* Do not preserve environment */
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070071#define CONFIG_ENV_SIZE 0x1000
72
73/* Monitor Command Prompt */
74#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070075#define CONFIG_SYS_LONGHELP
76#define CONFIG_CMDLINE_EDITING 1
77#define CONFIG_SYS_MAXARGS 64 /* max command args */
78#define CONFIG_NO_RELOCATION 1
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070079#define PLL_REF_CLK 50000000 /* 50 MHz */
80#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
81
82#endif /* __THUNDERX_88XX_H__ */