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Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +09001/*
Nobuhiro Iwamatsu10b2b402011-01-06 12:38:01 +09002 * Configuation settings for shmin (T-SH7706LAN, T-SH7706LSR)
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +09003 *
Nobuhiro Iwamatsu10b2b402011-01-06 12:38:01 +09004 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +09005 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +09007 */
8
9#ifndef __SHMIN_H
10#define __SHMIN_H
11
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090012#define CONFIG_CPU_SH7706 1
Nobuhiro Iwamatsu10b2b402011-01-06 12:38:01 +090013/* T-SH7706LAN */
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090014#define CONFIG_SHMIN 1
Nobuhiro Iwamatsu10b2b402011-01-06 12:38:01 +090015/* T-SH7706LSR*/
16/* #define CONFIG_T_SH7706LSR 1 */
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090017
Wolfgang Denka4de8352011-02-02 22:36:10 +010018/*
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090019 * This board has original boot loader. If you write u-boot to 0x0,
20 * you should set undef.
21 */
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090022#undef CONFIG_SHOW_BOOT_PROGRESS
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020023#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090024
25/* system */
26#define SHMIN_SDRAM_BASE (0x8C000000)
27#define SHMIN_FLASH_BASE_1 (0xA0000000)
28
29#define CONFIG_SYS_LONGHELP /* undef to save memory */
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090030#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090031/* List of legal baudrate settings for this board */
Nobuhiro Iwamatsu10b2b402011-01-06 12:38:01 +090032#define CONFIG_SYS_BAUDRATE_TABLE { 9600,14400,19200,38400,57600,115200 }
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090033
34/* SCIF */
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090035#define CONFIG_CONS_SCIF0 1
36
37/* memory */
38#define CONFIG_SYS_SDRAM_BASE SHMIN_SDRAM_BASE
39#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
40#define CONFIG_SYS_MEMTEST_START SHMIN_SDRAM_BASE
41#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - (256 * 1024))
42
43#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1 * 1024 * 1024)
44#define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE)
45#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
46#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090047#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
48
49/* FLASH */
50#define CONFIG_SYS_FLASH_CFI
51#define CONFIG_FLASH_CFI_DRIVER
52#undef CONFIG_SYS_FLASH_QUIET_TEST
53#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
54#define CONFIG_SYS_FLASH_BASE SHMIN_FLASH_BASE_1
55#define CONFIG_SYS_MAX_FLASH_SECT 11
56#define CONFIG_SYS_MAX_FLASH_BANKS 1
57
58#define CONFIG_FLASH_CFI_LEGACY
59#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_FLASH_BASE
60#define CONFIG_SYS_ATMEL_TOTALSECT CONFIG_SYS_MAX_FLASH_SECT
61#define CONFIG_SYS_ATMEL_REGION 4
62#define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
63#define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
64
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090065#define CONFIG_ENV_SECT_SIZE (64 * 1024)
66#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Nobuhiro Iwamatsu10b2b402011-01-06 12:38:01 +090067
68#ifdef CONFIG_T_SH7706LSR
69#define CONFIG_ENV_ADDR (SHMIN_FLASH_BASE_1 + 70000)
70#else
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090071#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Nobuhiro Iwamatsu10b2b402011-01-06 12:38:01 +090072#endif
73
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090074#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
75#define CONFIG_SYS_FLASH_WRITE_TOUT 500
76
77/* Board Clock */
Nobuhiro Iwamatsu10b2b402011-01-06 12:38:01 +090078#ifdef CONFIG_T_SH7706LSR
79#define CONFIG_SYS_CLK_FREQ 40000000
80#else
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090081#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu10b2b402011-01-06 12:38:01 +090082#endif /* CONFIG_T_SH7706LSR */
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090083#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
84#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090085#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsu980fbb72010-10-25 03:12:24 +090086
87/* Network device */
88#define CONFIG_DRIVER_NE2000
89#define CONFIG_DRIVER_NE2000_BASE (0xb0000300)
90
91#endif /* __SHMIN_H */