Jim Liu | d1ce509 | 2022-10-11 16:09:13 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (c) 2022 Nuvoton Technology Corp. |
| 4 | */ |
| 5 | |
| 6 | #include <dm.h> |
| 7 | #include <errno.h> |
| 8 | #include <regmap.h> |
| 9 | #include <syscon.h> |
| 10 | #include <asm/io.h> |
| 11 | #include <dm/device_compat.h> |
| 12 | #include <dm/pinctrl.h> |
| 13 | #include <linux/bitfield.h> |
| 14 | #include <asm/arch/rst.h> |
| 15 | |
| 16 | /* GCR register offsets */ |
| 17 | #define WD0RCR 0x38 |
| 18 | #define WD1RCR 0x3c |
| 19 | #define WD2RCR 0x40 |
| 20 | #define SWRSTC1 0x44 |
| 21 | #define SWRSTC2 0x48 |
| 22 | #define SWRSTC3 0x4c |
| 23 | #define SWRSTC4 0x50 |
| 24 | #define CORSTC 0x5c |
| 25 | #define FLOCKR1 0x74 |
| 26 | #define INTCR4 0xc0 |
| 27 | #define I2CSEGSEL 0xe0 |
| 28 | #define MFSEL1 0x260 |
| 29 | #define MFSEL2 0x264 |
| 30 | #define MFSEL3 0x268 |
| 31 | #define MFSEL4 0x26c |
| 32 | #define MFSEL5 0x270 |
| 33 | #define MFSEL6 0x274 |
| 34 | #define MFSEL7 0x278 |
| 35 | |
| 36 | /* GPIO register offsets */ |
| 37 | #define GPIO_POL 0x08 /* Polarity */ |
| 38 | #define GPIO_DOUT 0x0c /* Data OUT */ |
| 39 | #define GPIO_OTYP 0x14 /* Output Type */ |
| 40 | #define GPIO_PU 0x1c /* Pull-up */ |
| 41 | #define GPIO_PD 0x20 /* Pull-down */ |
| 42 | #define GPIO_DBNC 0x24 /* Debounce */ |
| 43 | #define GPIO_EVEN 0x40 /* Event Enable */ |
| 44 | #define GPIO_EVST 0x4c /* Event Status */ |
| 45 | #define GPIO_IEM 0x58 /* Input Enable */ |
| 46 | #define GPIO_OSRC 0x5c /* Output Slew-Rate Control */ |
| 47 | #define GPIO_ODSC 0x60 /* Output Drive Strength Control */ |
| 48 | #define GPIO_OES 0x70 /* Output Enable Set */ |
| 49 | #define GPIO_OEC 0x74 /* Output Enable Clear */ |
| 50 | |
| 51 | #define NPCM8XX_GPIO_PER_BANK 32 |
| 52 | #define GPIOX_OFFSET 16 |
| 53 | |
| 54 | struct npcm8xx_pinctrl_priv { |
| 55 | void __iomem *gpio_base; |
| 56 | struct regmap *gcr_regmap; |
| 57 | struct regmap *rst_regmap; |
| 58 | }; |
| 59 | |
| 60 | /* |
| 61 | * Function table |
| 62 | * name, register, enable bit, pin list |
| 63 | */ |
| 64 | #define FUNC_LIST \ |
| 65 | FUNC(smb3, MFSEL1, 0, 30, 31) \ |
| 66 | FUNC(smb4, MFSEL1, 1, 28, 29) \ |
| 67 | FUNC(smb5, MFSEL1, 2, 26, 27) \ |
| 68 | FUNC(spi0cs1, MFSEL1, 3, 32) \ |
| 69 | FUNC(hsi1c, MFSEL1, 4, 45, 46, 47, 61) \ |
| 70 | FUNC(hsi2c, MFSEL1, 5, 52, 53, 54, 55) \ |
| 71 | FUNC(smb0, MFSEL1, 6, 114, 115) \ |
| 72 | FUNC(smb1, MFSEL1, 7, 116, 117) \ |
| 73 | FUNC(smb2, MFSEL1, 8, 118, 119) \ |
| 74 | FUNC(bmcuart0a, MFSEL1, 9, 41, 42) \ |
| 75 | FUNC(hsi1a, MFSEL1, 10, 43, 63) \ |
| 76 | FUNC(hsi2a, MFSEL1, 11, 48, 49) \ |
| 77 | FUNC(r1err, MFSEL1, 12, 56) \ |
| 78 | FUNC(r1md, MFSEL1, 13, 57, 58) \ |
| 79 | FUNC(r2, MFSEL1, 14, 84, 85, 86, 87, 88, 89, 200) \ |
| 80 | FUNC(r2err, MFSEL1, 15, 90) \ |
| 81 | FUNC(r2md, MFSEL1, 16, 91, 92) \ |
| 82 | FUNC(ga20kbc, MFSEL1, 17, 93, 94) \ |
| 83 | FUNC(clkout, MFSEL1, 21, 160) \ |
| 84 | FUNC(sci, MFSEL1, 22, 170) \ |
| 85 | FUNC(gspi, MFSEL1, 24, 12, 13, 14, 15) \ |
| 86 | FUNC(lpc, MFSEL1, 26, 95, 161, 163, 164, 165, 166, 167) \ |
| 87 | FUNC(hsi1b, MFSEL1, 28, 44, 62) \ |
| 88 | FUNC(hsi2b, MFSEL1, 29, 50, 51) \ |
| 89 | FUNC(iox1, MFSEL1, 30, 0, 1, 2, 3) \ |
| 90 | FUNC(serirq, MFSEL1, 31, 168) \ |
| 91 | FUNC(fanin0, MFSEL2, 0, 64) \ |
| 92 | FUNC(fanin1, MFSEL2, 1, 65) \ |
| 93 | FUNC(fanin2, MFSEL2, 2, 66) \ |
| 94 | FUNC(fanin3, MFSEL2, 3, 67) \ |
| 95 | FUNC(fanin4, MFSEL2, 4, 68) \ |
| 96 | FUNC(fanin5, MFSEL2, 5, 69) \ |
| 97 | FUNC(fanin6, MFSEL2, 6, 70) \ |
| 98 | FUNC(fanin7, MFSEL2, 7, 71) \ |
| 99 | FUNC(fanin8, MFSEL2, 8, 72) \ |
| 100 | FUNC(fanin9, MFSEL2, 9, 73) \ |
| 101 | FUNC(fanin10, MFSEL2, 10, 74) \ |
| 102 | FUNC(fanin11, MFSEL2, 11, 75) \ |
| 103 | FUNC(fanin12, MFSEL2, 12, 76) \ |
| 104 | FUNC(fanin13, MFSEL2, 13, 77) \ |
| 105 | FUNC(fanin14, MFSEL2, 14, 78) \ |
| 106 | FUNC(fanin15, MFSEL2, 15, 79) \ |
| 107 | FUNC(pwm0, MFSEL2, 16, 80) \ |
| 108 | FUNC(pwm1, MFSEL2, 17, 81) \ |
| 109 | FUNC(pwm2, MFSEL2, 18, 82) \ |
| 110 | FUNC(pwm3, MFSEL2, 19, 83) \ |
| 111 | FUNC(pwm4, MFSEL2, 20, 144) \ |
| 112 | FUNC(pwm5, MFSEL2, 21, 145) \ |
| 113 | FUNC(pwm6, MFSEL2, 22, 146) \ |
| 114 | FUNC(pwm7, MFSEL2, 23, 147) \ |
| 115 | FUNC(hgpio0, MFSEL2, 24, 20) \ |
| 116 | FUNC(hgpio1, MFSEL2, 25, 21) \ |
| 117 | FUNC(hgpio2, MFSEL2, 26, 22) \ |
| 118 | FUNC(hgpio3, MFSEL2, 27, 23) \ |
| 119 | FUNC(hgpio4, MFSEL2, 28, 24) \ |
| 120 | FUNC(hgpio5, MFSEL2, 29, 25) \ |
| 121 | FUNC(hgpio6, MFSEL2, 30, 59) \ |
| 122 | FUNC(hgpio7, MFSEL2, 31, 60) \ |
| 123 | FUNC(scipme, MFSEL3, 0, 169) \ |
| 124 | FUNC(smb6, MFSEL3, 1, 171, 172) \ |
| 125 | FUNC(smb7, MFSEL3, 2, 173, 174) \ |
| 126 | FUNC(faninx, MFSEL3, 3, 175, 176, 177, 203) \ |
| 127 | FUNC(spi1, MFSEL3, 4, 175, 176, 177, 203) \ |
| 128 | FUNC(smb12, MFSEL3, 5, 220, 221) \ |
| 129 | FUNC(smb13, MFSEL3, 6, 222, 223) \ |
| 130 | FUNC(smb14, MFSEL3, 7, 22, 23) \ |
| 131 | FUNC(smb15, MFSEL3, 8, 20, 21) \ |
| 132 | FUNC(r1, MFSEL3, 9, 178, 179, 180, 181, 182, 193, 201) \ |
| 133 | FUNC(mmc, MFSEL3, 10, 152, 154, 156, 157, 158, 159) \ |
| 134 | FUNC(mmc8, MFSEL3, 11, 148, 149, 150, 151) \ |
| 135 | FUNC(pspi, MFSEL3, 13, 17, 18, 19) \ |
| 136 | FUNC(iox2, MFSEL3, 14, 4, 5, 6, 7) \ |
| 137 | FUNC(clkrun, MFSEL3, 16, 162) \ |
| 138 | FUNC(ioxh, MFSEL3, 18, 10, 11, 24, 25) \ |
| 139 | FUNC(wdog1, MFSEL3, 19, 218) \ |
| 140 | FUNC(wdog2, MFSEL3, 20, 219) \ |
| 141 | FUNC(i3c5, MFSEL3, 22, 106, 107) \ |
| 142 | FUNC(bmcuart1, MFSEL3, 24, 43, 63) \ |
| 143 | FUNC(mmccd, MFSEL3, 25, 155) \ |
| 144 | FUNC(ddr, MFSEL3, 26, 110, 111, 112, 113, 208, 209, 210, 211, 212,\ |
| 145 | 213, 214, 215, 216, 217, 250) \ |
| 146 | FUNC(jtag2, MFSEL4, 0, 43, 44, 45, 46, 47) \ |
| 147 | FUNC(bmcuart0b, MFSEL4, 1, 48, 49) \ |
| 148 | FUNC(mmcrst, MFSEL4, 6, 155) \ |
| 149 | FUNC(espi, MFSEL4, 8, 95, 161, 163, 164, 165, 166, 167, 168) \ |
| 150 | FUNC(clkreq, MFSEL4, 9, 231) \ |
| 151 | FUNC(smb8, MFSEL4, 11, 128, 129) \ |
| 152 | FUNC(smb9, MFSEL4, 12, 130, 131) \ |
| 153 | FUNC(smb10, MFSEL4, 13, 132, 133) \ |
| 154 | FUNC(smb11, MFSEL4, 14, 134, 135) \ |
| 155 | FUNC(spi3, MFSEL4, 16, 183, 184, 185, 186) \ |
| 156 | FUNC(spi3cs1, MFSEL4, 17, 187) \ |
| 157 | FUNC(spi3cs2, MFSEL4, 18, 188) \ |
| 158 | FUNC(spi3cs3, MFSEL4, 19, 189) \ |
| 159 | FUNC(spi3quad, MFSEL4, 20, 188, 189) \ |
| 160 | FUNC(rg1mdio, MFSEL4, 21, 108, 109) \ |
| 161 | FUNC(bu2, MFSEL4, 22, 96, 97) \ |
| 162 | FUNC(rg2mdio, MFSEL4, 23, 216, 217) \ |
| 163 | FUNC(rg2, MFSEL4, 24, 110, 111, 112, 113, 208, 209, 210, 211, 212,\ |
| 164 | 213, 214, 215) \ |
| 165 | FUNC(spix, MFSEL4, 27, 224, 225, 226, 227, 229, 230) \ |
| 166 | FUNC(spixcs1, MFSEL4, 28, 228) \ |
| 167 | FUNC(spi1cs1, MFSEL5, 0, 233) \ |
| 168 | FUNC(jm2, MFSEL5, 1) \ |
| 169 | FUNC(j2j3, MFSEL5, 2, 44, 62, 45, 46) \ |
| 170 | FUNC(spi1d23, MFSEL5, 3, 191, 192) \ |
| 171 | FUNC(spi1cs2, MFSEL5, 4, 191) \ |
| 172 | FUNC(spi1cs3, MFSEL5, 5, 192) \ |
| 173 | FUNC(bu6, MFSEL5, 6, 50, 51) \ |
| 174 | FUNC(bu5, MFSEL5, 7, 52, 53) \ |
| 175 | FUNC(bu4, MFSEL5, 8, 54, 55) \ |
| 176 | FUNC(r1oen, MFSEL5, 9, 56) \ |
| 177 | FUNC(r2oen, MFSEL5, 10, 90) \ |
| 178 | FUNC(rmii3, MFSEL5, 11, 110, 111, 209, 210, 211, 214, 215) \ |
| 179 | FUNC(bu5b, MFSEL5, 12, 100, 101) \ |
| 180 | FUNC(bu4b, MFSEL5, 13, 98, 99) \ |
| 181 | FUNC(r3oen, MFSEL5, 14, 213) \ |
| 182 | FUNC(jm1, MFSEL5, 15, 136, 137, 138, 139, 140) \ |
| 183 | FUNC(gpi35, MFSEL5, 16, 35) \ |
| 184 | FUNC(i3c0, MFSEL5, 17, 240, 241) \ |
| 185 | FUNC(gpi36, MFSEL5, 18, 36) \ |
| 186 | FUNC(i3c1, MFSEL5, 19, 242, 243) \ |
| 187 | FUNC(tp_gpio4b, MFSEL5, 20, 57) \ |
| 188 | FUNC(i3c2, MFSEL5, 21, 244, 245) \ |
| 189 | FUNC(tp_gpio5b, MFSEL5, 22, 58) \ |
| 190 | FUNC(i3c3, MFSEL5, 23, 246, 247) \ |
| 191 | FUNC(smb16, MFSEL5, 24, 10, 11) \ |
| 192 | FUNC(smb17, MFSEL5, 25, 2, 3) \ |
| 193 | FUNC(smb18, MFSEL5, 26, 0, 1) \ |
| 194 | FUNC(smb19, MFSEL5, 27, 59, 60) \ |
| 195 | FUNC(smb20, MFSEL5, 28, 234, 235) \ |
| 196 | FUNC(smb21, MFSEL5, 29, 169, 170) \ |
| 197 | FUNC(smb22, MFSEL5, 30, 39, 40) \ |
| 198 | FUNC(smb23, MFSEL5, 31, 37, 38) \ |
| 199 | FUNC(smb23b, MFSEL6, 0, 134, 135) \ |
| 200 | FUNC(cp1utxd, MFSEL6, 1, 42) \ |
| 201 | FUNC(cp1gpio0, MFSEL6, 2) \ |
| 202 | FUNC(cp1gpio1, MFSEL6, 3) \ |
| 203 | FUNC(cp1gpio2, MFSEL6, 4) \ |
| 204 | FUNC(cp1gpio3, MFSEL6, 5) \ |
| 205 | FUNC(cp1gpio4, MFSEL6, 6) \ |
| 206 | FUNC(cp1gpio5, MFSEL6, 7, 17) \ |
| 207 | FUNC(cp1gpio6, MFSEL6, 8, 91) \ |
| 208 | FUNC(cp1gpio7, MFSEL6, 9, 92) \ |
| 209 | FUNC(i3c4, MFSEL6, 10, 33, 34) \ |
| 210 | FUNC(pwm8, MFSEL6, 11, 220) \ |
| 211 | FUNC(pwm9, MFSEL6, 12, 221) \ |
| 212 | FUNC(pwm10, MFSEL6, 13, 234) \ |
| 213 | FUNC(pwm11, MFSEL6, 14, 235) \ |
| 214 | FUNC(nbu1crts, MFSEL6, 15, 44, 62) \ |
| 215 | FUNC(fm0, MFSEL6, 16, 194, 195, 196, 202, 199, 198, 197) \ |
| 216 | FUNC(fm1, MFSEL6, 17, 175, 176, 177, 203, 191, 192, 233) \ |
| 217 | FUNC(fm2, MFSEL6, 18, 224, 225, 226, 227, 228, 229, 230) \ |
| 218 | FUNC(gpio1836, MFSEL6, 19, 183, 184, 185, 186) \ |
| 219 | FUNC(cp1gpio0b, MFSEL6, 20, 127) \ |
| 220 | FUNC(cp1gpio1b, MFSEL6, 21, 126) \ |
| 221 | FUNC(cp1gpio2b, MFSEL6, 22, 125) \ |
| 222 | FUNC(cp1gpio3b, MFSEL6, 23, 124) \ |
| 223 | FUNC(cp1gpio7b, MFSEL6, 24, 96) \ |
| 224 | FUNC(cp1gpio6b, MFSEL6, 25, 97) \ |
| 225 | FUNC(cp1gpio5b, MFSEL6, 26, 98) \ |
| 226 | FUNC(cp1gpio4b, MFSEL6, 27, 99) \ |
| 227 | FUNC(cp1gpio3c, MFSEL6, 28, 100) \ |
| 228 | FUNC(cp1gpio2c, MFSEL6, 29, 101) \ |
| 229 | FUNC(r3rxer, MFSEL6, 30, 212) \ |
| 230 | FUNC(cp1urxd, MFSEL6, 31, 41) \ |
| 231 | FUNC(tp_gpio0, MFSEL7, 0, 8) \ |
| 232 | FUNC(tp_gpio1, MFSEL7, 1, 9) \ |
| 233 | FUNC(tp_gpio2, MFSEL7, 2, 16) \ |
| 234 | FUNC(tp_gpio3, MFSEL7, 3, 100) \ |
| 235 | FUNC(tp_gpio4, MFSEL7, 4, 99) \ |
| 236 | FUNC(tp_gpio5, MFSEL7, 5, 98) \ |
| 237 | FUNC(tp_gpio6, MFSEL7, 6, 97) \ |
| 238 | FUNC(tp_gpio7, MFSEL7, 7, 96) \ |
| 239 | FUNC(tp_gpio0b, MFSEL7, 8, 91) \ |
| 240 | FUNC(tp_gpio1b, MFSEL7, 9, 92) \ |
| 241 | FUNC(tp_gpio2b, MFSEL7, 10, 101) \ |
| 242 | FUNC(tp_smb1, MFSEL7, 11, 142, 143) \ |
| 243 | FUNC(tp_uart, MFSEL7, 12, 50, 51) \ |
| 244 | FUNC(tp_jtag3, MFSEL7, 13, 44, 45, 46, 62) \ |
| 245 | FUNC(gpio187, MFSEL7, 24, 187) \ |
| 246 | FUNC(gpio1889, MFSEL7, 25, 188, 189) \ |
| 247 | FUNC(smb14b, MFSEL7, 26, 32, 187) \ |
| 248 | FUNC(smb15b, MFSEL7, 27, 191, 192) \ |
| 249 | FUNC(tp_smb2, MFSEL7, 28, 24, 25) \ |
| 250 | FUNC(vgadig, MFSEL7, 29, 102, 103, 104, 105) \ |
| 251 | FUNC(smb16b, MFSEL7, 30, 218, 219) \ |
| 252 | FUNC(smb0b, I2CSEGSEL, 0, 194, 195) \ |
| 253 | FUNC(smb0c, I2CSEGSEL, 1, 196, 202) \ |
| 254 | FUNC(smb0d, I2CSEGSEL, 2, 198, 199) \ |
| 255 | FUNC(smb1b, I2CSEGSEL, 5, 126, 127) \ |
| 256 | FUNC(smb1c, I2CSEGSEL, 6, 124, 125) \ |
| 257 | FUNC(smb1d, I2CSEGSEL, 7, 4, 5) \ |
| 258 | FUNC(smb2b, I2CSEGSEL, 8, 122, 123) \ |
| 259 | FUNC(smb2c, I2CSEGSEL, 9, 120, 121) \ |
| 260 | FUNC(smb2d, I2CSEGSEL, 10, 6, 7) \ |
| 261 | FUNC(smb3b, I2CSEGSEL, 11, 39, 40) \ |
| 262 | FUNC(smb3c, I2CSEGSEL, 12, 37, 38) \ |
| 263 | FUNC(smb3d, I2CSEGSEL, 13, 59, 60) \ |
| 264 | FUNC(smb4b, I2CSEGSEL, 14, 18, 19) \ |
| 265 | FUNC(smb4c, I2CSEGSEL, 15, 20, 21) \ |
| 266 | FUNC(smb4d, I2CSEGSEL, 16, 22, 23) \ |
| 267 | FUNC(smb5b, I2CSEGSEL, 19, 12, 13) \ |
| 268 | FUNC(smb5c, I2CSEGSEL, 20, 14, 15) \ |
| 269 | FUNC(smb5d, I2CSEGSEL, 21, 93, 94) \ |
| 270 | FUNC(smb0den, I2CSEGSEL, 22, 197) \ |
| 271 | FUNC(smb6b, I2CSEGSEL, 24, 2, 3) \ |
| 272 | FUNC(smb6c, I2CSEGSEL, 25, 0, 1) \ |
| 273 | FUNC(smb6d, I2CSEGSEL, 26, 10, 11) \ |
| 274 | FUNC(smb7b, I2CSEGSEL, 27, 16, 141) \ |
| 275 | FUNC(smb7c, I2CSEGSEL, 28, 24, 25) \ |
| 276 | FUNC(smb7d, I2CSEGSEL, 29, 142, 143) \ |
| 277 | FUNC(lkgpo0, FLOCKR1, 0, 16) \ |
| 278 | FUNC(lkgpo1, FLOCKR1, 4, 8) \ |
| 279 | FUNC(lkgpo2, FLOCKR1, 8, 9) \ |
| 280 | FUNC(nprd_smi, FLOCKR1, 20, 190) \ |
| 281 | FUNC(mmcwp, FLOCKR1, 24, 153) \ |
| 282 | FUNC(rg2refck, INTCR4, 6) \ |
| 283 | FUNC(r1en, INTCR4, 12) \ |
| 284 | FUNC(r2en, INTCR4, 13) \ |
| 285 | FUNC(r3en, INTCR4, 14) |
| 286 | |
| 287 | /* declare function pins */ |
| 288 | #define FUNC(_name, _reg, _bit, ...) \ |
| 289 | static const u8 _name##_pins[] = { __VA_ARGS__ }; |
| 290 | FUNC_LIST |
| 291 | |
| 292 | /* enumerate function ids */ |
| 293 | #undef FUNC |
| 294 | #define FUNC(_name, _reg, _bit, ...) \ |
| 295 | FN_##_name, |
| 296 | enum npcm8xx_func_selectors { |
| 297 | FUNC_LIST |
| 298 | FN_gpio |
| 299 | }; |
| 300 | |
| 301 | #undef FUNC |
| 302 | #define FUNC(_name, _reg, _bit, ...) { \ |
| 303 | .id = FN_##_name, \ |
| 304 | .name = #_name, \ |
| 305 | .pins = _name##_pins, \ |
| 306 | .npins = ARRAY_SIZE(_name##_pins), \ |
| 307 | .reg = _reg, \ |
| 308 | .bit = _bit, \ |
| 309 | }, |
| 310 | |
| 311 | /** |
| 312 | * struct group_info - group of pins for a function |
| 313 | * |
| 314 | * @id: identifier |
| 315 | * @name: group & function name |
| 316 | * @pins: group of pins used by this function |
| 317 | * @npins: number of pins |
| 318 | * @reg: register for enabling the function |
| 319 | * @bit: offset of enable bit in the register |
| 320 | */ |
| 321 | struct group_info { |
| 322 | u32 id; |
| 323 | char *name; |
| 324 | const u8 *pins; |
| 325 | u32 npins; |
| 326 | u32 reg; |
| 327 | u32 bit; |
| 328 | }; |
| 329 | |
| 330 | static const struct group_info npcm8xx_groups[] = { |
| 331 | FUNC_LIST |
| 332 | }; |
| 333 | |
| 334 | /* Pin flags */ |
| 335 | #define SLEW BIT(0) /* Has Slew Control */ |
| 336 | #define GPIO_ALT BIT(1) /* GPIO function is enabled by setting alternate */ |
| 337 | #define DSLO_MASK GENMASK(11, 8) /* Drive strength */ |
| 338 | #define DSHI_MASK GENMASK(15, 12) |
| 339 | #define GPIO_IDX_MASK GENMASK(18, 16) |
| 340 | #define GPIO_IDX(x) ((x) << 16) /* index of alt_func[] for gpio function */ |
| 341 | #define DS(lo, hi) (((lo) << 8) | ((hi) << 12)) |
| 342 | #define DSLO(x) FIELD_GET(DSLO_MASK, x) /* Low DS value */ |
| 343 | #define DSHI(x) FIELD_GET(DSHI_MASK, x) /* High DS value */ |
| 344 | #define GPIO_IDX_VAL(x) FIELD_GET(GPIO_IDX_MASK, x) |
| 345 | |
| 346 | #define MAX_ALT_FUNCS 5 /* Max alternate functions */ |
| 347 | /** |
| 348 | * struct pin_info |
| 349 | * |
| 350 | * @gpio_num: GPIO number as index |
| 351 | * @name: pin name |
| 352 | * @funcs: array of alternate function selectors of this pin |
| 353 | * @num_funcs: number of alternate functions |
| 354 | */ |
| 355 | struct pin_info { |
| 356 | u32 gpio_num; |
| 357 | char *name; |
| 358 | u32 funcs[MAX_ALT_FUNCS]; |
| 359 | u32 num_funcs; |
| 360 | u32 flags; |
| 361 | }; |
| 362 | |
| 363 | /* Pin table */ |
| 364 | static const struct pin_info npcm8xx_pins[] = { |
| 365 | {0, "GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA", {FN_iox1, FN_smb6c, FN_smb18}, 3, SLEW}, |
| 366 | {1, "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL", {FN_iox1, FN_smb6c, FN_smb18}, 3, SLEW}, |
| 367 | {2, "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA", {FN_iox1, FN_smb6b, FN_smb17}, 3, SLEW}, |
| 368 | {3, "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL", {FN_iox1, FN_smb6b, FN_smb17}, 3, SLEW}, |
| 369 | {4, "GPIO4/IOX2_DI/SMB1D_SDA", {FN_iox2, FN_smb1d}, 2, SLEW}, |
| 370 | {5, "GPIO5/IOX2_LD/SMB1D_SCL", {FN_iox2, FN_smb1d}, 2, SLEW}, |
| 371 | {6, "GPIO6/IOX2_CK/SMB2D_SDA", {FN_iox2, FN_smb2d}, 2, SLEW}, |
| 372 | {7, "GPIO7/IOX2_D0/SMB2D_SCL", {FN_iox2, FN_smb2d}, 2, SLEW}, |
| 373 | {8, "GPIO8/LKGPO1/TP_GPIO0", {FN_lkgpo1, FN_tp_gpio0b}, 2, DS(8, 12)}, |
| 374 | {9, "GPIO9/LKGPO2/TP_GPIO1", {FN_lkgpo2, FN_tp_gpio1b}, 2, DS(8, 12)}, |
| 375 | {10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL", {FN_ioxh, FN_smb6d, FN_smb16}, 3, SLEW}, |
| 376 | {11, "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA", {FN_ioxh, FN_smb6d, FN_smb16}, 3, SLEW}, |
| 377 | {12, "GPIO12/GSPI_CK/SMB5B_SCL", {FN_gspi, FN_smb5d}, 2, SLEW}, |
| 378 | {13, "GPIO13/GSPI_DO/SMB5B_SDA", {FN_gspi, FN_smb5d}, 2, SLEW}, |
| 379 | {14, "GPIO14/GSPI_DI/SMB5C_SCL", {FN_gspi, FN_smb5c}, 2, SLEW}, |
| 380 | {15, "GPIO15/GSPI_CS/SMB5C_SDA", {FN_gspi, FN_smb5c}, 2, SLEW}, |
| 381 | {16, "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2", {FN_lkgpo0, FN_smb7b, FN_tp_gpio2b}, 3, SLEW}, |
| 382 | {17, "GPIO17/PSPI_DI/CP1_GPIO5", {FN_pspi, FN_cp1gpio5}, 2, SLEW}, |
| 383 | {18, "GPIO18/PSPI_D0/SMB4B_SDA", {FN_pspi, FN_smb4b}, 2, SLEW}, |
| 384 | {19, "GPIO19/PSPI_CK/SMB4B_SCL", {FN_pspi, FN_smb4b}, 2, SLEW}, |
| 385 | {20, "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA", {FN_hgpio0, FN_smb15, FN_smb4c}, 3, SLEW}, |
| 386 | {21, "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL", {FN_hgpio1, FN_smb15, FN_smb4c}, 3, SLEW}, |
| 387 | {22, "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA", {FN_hgpio2, FN_smb14, FN_smb4d}, 3, SLEW}, |
| 388 | {23, "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL", {FN_hgpio3, FN_smb14, FN_smb4d}, 3, SLEW}, |
| 389 | {24, "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL", |
| 390 | {FN_hgpio4, FN_ioxh, FN_smb7c, FN_tp_smb2}, 4, SLEW}, |
| 391 | {25, "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA", {FN_hgpio5, FN_ioxh, FN_smb7c}, |
| 392 | 3, SLEW}, |
| 393 | {26, "GPIO26/SMB5_SDA", {FN_smb5}, 1, 0}, |
| 394 | {27, "GPIO27/SMB5_SCL", {FN_smb5}, 1, 0}, |
| 395 | {28, "GPIO28/SMB4_SDA", {FN_smb4}, 1, 0}, |
| 396 | {29, "GPIO29/SMB4_SCL", {FN_smb4}, 1, 0}, |
| 397 | {30, "GPIO30/SMB3_SDA", {FN_smb3}, 1, 0}, |
| 398 | {31, "GPIO31/SMB3_SCL", {FN_smb3}, 1, 0}, |
| 399 | {32, "GPIO32/SMB14_SCL/SPI0_nCS1", {FN_smb14b, FN_spi0cs1}, 2, SLEW}, |
| 400 | {33, "I3C4_SCL", {FN_i3c4}, 1, SLEW}, |
| 401 | {34, "I3C4_SDA", {FN_i3c4}, 1, SLEW}, |
| 402 | {35, "GPI35/MCBPCK", {FN_gpi35}, 1, GPIO_ALT | GPIO_IDX(0)}, |
| 403 | {36, "GPI36/SYSBPCK", {FN_gpi36}, 1, GPIO_ALT | GPIO_IDX(0)}, |
| 404 | {37, "GPIO37/SMB3C_SDA/SMB23_SDA", {FN_smb3c, FN_smb23}, 2, SLEW}, |
| 405 | {38, "GPIO38/SMB3C_SCL/SMB23_SCL", {FN_smb3c, FN_smb23}, 2, SLEW}, |
| 406 | {39, "GPIO39/SMB3B_SDA/SMB22_SDA", {FN_smb3b, FN_smb22}, 2, SLEW}, |
| 407 | {40, "GPIO40/SMB3B_SCL/SMB22_SCL", {FN_smb3b, FN_smb22}, 2, SLEW}, |
| 408 | {41, "GPIO41/BU0_RXD/CP1U_RXD", {FN_bmcuart0a, FN_cp1urxd}, 2, 0}, |
| 409 | {42, "GPIO42/BU0_TXD/CP1U_TXD", {FN_bmcuart0a, FN_cp1utxd}, 2, DS(2, 4)}, |
| 410 | {43, "GPIO43/SI1_RXD/BU1_RXD", {FN_hsi1a, FN_bmcuart1}, 2, 0}, |
| 411 | {44, "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI", |
| 412 | {FN_hsi1b, FN_nbu1crts, FN_jtag2, FN_tp_jtag3, FN_j2j3}, 5, 0}, |
| 413 | {45, "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO", |
| 414 | {FN_hsi1c, FN_jtag2, FN_j2j3, FN_tp_jtag3}, 4, DS(2, 8)}, |
| 415 | {46, "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK", |
| 416 | {FN_hsi1c, FN_jtag2, FN_j2j3, FN_tp_jtag3}, 4, 0}, |
| 417 | {47, "GPIO47/SI1n_RI1", {FN_hsi1c,}, 1, DS(2, 8)}, |
| 418 | {48, "GPIO48/SI2_TXD/BU0_TXD/STRAP5", {FN_hsi2a, FN_bmcuart0b}, 2, 0}, |
| 419 | {49, "GPIO49/SI2_RXD/BU0_RXD", {FN_hsi2a, FN_bmcuart0b}, 2, 0}, |
| 420 | {50, "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD", {FN_hsi2b, FN_bu6, FN_tp_uart}, 3, 0}, |
| 421 | {51, "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD", {FN_hsi2b, FN_bu6, FN_tp_uart}, 3, 0}, |
| 422 | {52, "GPIO52/SI2_nDCD/BU5_RXD", {FN_hsi2c, FN_bu5}, 2, 0}, |
| 423 | {53, "GPIO53/SI2_nDTR_BOUT2/BU5_TXD", {FN_hsi2c, FN_bu5}, 2, 0}, |
| 424 | {54, "GPIO54/SI2_nDSR/BU4_TXD", {FN_hsi2c, FN_bu4}, 2, 0}, |
| 425 | {55, "GPIO55/SI2_RI2/BU4_RXD", {FN_hsi2c, FN_bu4}, 2, 0}, |
| 426 | {56, "GPIO56/R1_RXERR/R1_OEN", {FN_r1err, FN_r1oen}, 2, 0}, |
| 427 | {57, "GPIO57/R1_MDC/TP_GPIO4", {FN_r1md, FN_tp_gpio4b}, 2, DS(2, 4)}, |
| 428 | {58, "GPIO58/R1_MDIO/TP_GPIO5", {FN_r1md, FN_tp_gpio5b}, 2, DS(2, 4)}, |
| 429 | {59, "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA", {FN_hgpio6, FN_smb3d, FN_smb19}, 3, 0}, |
| 430 | {60, "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL", {FN_hgpio7, FN_smb3d, FN_smb19}, 3, 0}, |
| 431 | {61, "GPIO61/SI1_nDTR_BOUT", {FN_hsi1c}, 1, 0}, |
| 432 | {62, "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO", |
| 433 | {FN_hsi1b, FN_jtag2, FN_j2j3, FN_nbu1crts, FN_tp_jtag3}, 5, 0}, |
| 434 | {63, "GPIO63/BU1_TXD1/SI1_TXD", {FN_hsi1a, FN_bmcuart1}, 2, 0}, |
| 435 | {64, "GPIO64/FANIN0", {FN_fanin0}, 1, 0}, |
| 436 | {65, "GPIO65/FANIN1", {FN_fanin1}, 1, 0}, |
| 437 | {66, "GPIO66/FANIN2", {FN_fanin2}, 1, 0}, |
| 438 | {67, "GPIO67/FANIN3", {FN_fanin3}, 1, 0}, |
| 439 | {68, "GPIO68/FANIN4", {FN_fanin4}, 1, 0}, |
| 440 | {69, "GPIO69/FANIN5", {FN_fanin5}, 1, 0}, |
| 441 | {70, "GPIO70/FANIN6", {FN_fanin6}, 1, 0}, |
| 442 | {71, "GPIO71/FANIN7", {FN_fanin7}, 1, 0}, |
| 443 | {72, "GPIO72/FANIN8", {FN_fanin8}, 1, 0}, |
| 444 | {73, "GPIO73/FANIN9", {FN_fanin9}, 1, 0}, |
| 445 | {74, "GPIO74/FANIN10", {FN_fanin10}, 1, 0}, |
| 446 | {75, "GPIO75/FANIN11", {FN_fanin11}, 1, 0}, |
| 447 | {76, "GPIO76/FANIN12", {FN_fanin12}, 1, 0}, |
| 448 | {77, "GPIO77/FANIN13", {FN_fanin13}, 1, 0}, |
| 449 | {78, "GPIO78/FANIN14", {FN_fanin14}, 1, 0}, |
| 450 | {79, "GPIO79/FANIN15", {FN_fanin15}, 1, 0}, |
| 451 | {80, "GPIO80/PWM0", {FN_pwm0}, 1, DS(4, 8)}, |
| 452 | {81, "GPIO81/PWM1", {FN_pwm1}, 1, DS(4, 8)}, |
| 453 | {82, "GPIO82/PWM2", {FN_pwm2}, 1, DS(4, 8)}, |
| 454 | {83, "GPIO83/PWM3", {FN_pwm3}, 1, DS(4, 8)}, |
| 455 | {84, "GPIO84/R2_TXD0", {FN_r2}, 1, DS(4, 8) | SLEW}, |
| 456 | {85, "GPIO85/R2_TXD1", {FN_r2}, 1, DS(4, 8) | SLEW}, |
| 457 | {86, "GPIO86/R2_TXEN", {FN_r2}, 1, DS(4, 8) | SLEW}, |
| 458 | {87, "GPIO87/R2_RXD0", {FN_r2}, 1, 0}, |
| 459 | {88, "GPIO88/R2_RXD1", {FN_r2}, 1, 0}, |
| 460 | {89, "GPIO89/R2_CRSDV", {FN_r2}, 1, 0}, |
| 461 | {90, "GPIO90/R2_RXERR/R2_OEN", {FN_r2err, FN_r2oen}, 2, 0}, |
| 462 | {91, "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0", {FN_r2md, FN_cp1gpio6, FN_tp_gpio0}, 3, DS(2, 4)}, |
| 463 | {92, "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1", {FN_r2md, FN_cp1gpio7, FN_tp_gpio1}, 3, DS(2, 4)}, |
| 464 | {93, "GPIO93/GA20/SMB5D_SCL", {FN_ga20kbc, FN_smb5d}, 2, 0}, |
| 465 | {94, "GPIO94/nKBRST/SMB5D_SDA", {FN_ga20kbc, FN_smb5d}, 2, 0}, |
| 466 | {95, "GPIO95/nESPIRST/LPC_nLRESET", {FN_lpc, FN_espi}, 2, 0}, |
| 467 | {96, "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7", {FN_cp1gpio7b, FN_bu2, FN_tp_gpio7}, 3, SLEW}, |
| 468 | {97, "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6", {FN_cp1gpio6b, FN_bu2, FN_tp_gpio6}, 3, SLEW}, |
| 469 | {98, "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5", {FN_bu4b, FN_cp1gpio5b, FN_tp_gpio5}, 3, SLEW}, |
| 470 | {99, "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4", {FN_bu4b, FN_cp1gpio4b, FN_tp_gpio4}, 3, SLEW}, |
| 471 | {100, "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3", {FN_bu5b, FN_cp1gpio3c, FN_tp_gpio3}, 3, SLEW}, |
| 472 | {101, "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2", {FN_bu5b, FN_cp1gpio2c, FN_tp_gpio2}, 3, SLEW}, |
| 473 | {102, "GPIO102/HSYNC", {FN_vgadig}, 1, DS(4, 8)}, |
| 474 | {103, "GPIO103/VSYNC", {FN_vgadig}, 1, DS(4, 8)}, |
| 475 | {104, "GPIO104/DDC_SCL", {FN_vgadig}, 1, 0}, |
| 476 | {105, "GPIO105/DDC_SDA", {FN_vgadig}, 1, 0}, |
| 477 | {106, "GPIO106/I3C5_SCL", {FN_i3c5}, 1, SLEW}, |
| 478 | {107, "GPIO107/I3C5_SDA", {FN_i3c5}, 1, SLEW}, |
| 479 | {108, "GPIO108/SG1_MDC", {FN_rg1mdio}, 1, SLEW}, |
| 480 | {109, "GPIO109/SG1_MDIO", {FN_rg1mdio}, 1, SLEW}, |
| 481 | {110, "GPIO110/RG2_TXD0/DDRV0/R3_TXD0", {FN_rg2, FN_ddr, FN_rmii3}, 3, SLEW}, |
| 482 | {111, "GPIO111/RG2_TXD1/DDRV1/R3_TXD1", {FN_rg2, FN_ddr, FN_rmii3}, 3, SLEW}, |
| 483 | {112, "GPIO112/RG2_TXD2/DDRV2", {FN_rg2, FN_ddr}, 2, SLEW}, |
| 484 | {113, "GPIO113/RG2_TXD3/DDRV3", {FN_rg2, FN_ddr}, 2, SLEW}, |
| 485 | {114, "GPIO114/SMB0_SCL", {FN_smb0}, 1, 0}, |
| 486 | {115, "GPIO115/SMB0_SDA", {FN_smb0}, 1, 0}, |
| 487 | {116, "GPIO116/SMB1_SCL", {FN_smb1}, 1, 0}, |
| 488 | {117, "GPIO117/SMB1_SDA", {FN_smb1}, 1, 0}, |
| 489 | {118, "GPIO118/SMB2_SCL", {FN_smb2}, 1, 0}, |
| 490 | {119, "GPIO119/SMB2_SDA", {FN_smb2}, 1, 0}, |
| 491 | {120, "GPIO120/SMB2C_SDA", {FN_smb2c}, 1, SLEW}, |
| 492 | {121, "GPIO121/SMB2C_SCL", {FN_smb2c}, 1, SLEW}, |
| 493 | {122, "GPIO122/SMB2B_SDA", {FN_smb2b}, 1, SLEW}, |
| 494 | {123, "GPIO123/SMB2B_SCL", {FN_smb2b}, 1, SLEW}, |
| 495 | {124, "GPIO124/SMB1C_SDA/CP1_GPIO3", {FN_smb1c, FN_cp1gpio3b}, 2, SLEW}, |
| 496 | {125, "GPIO125/SMB1C_SCL/CP1_GPIO2", {FN_smb1c, FN_cp1gpio2b}, 2, SLEW}, |
| 497 | {126, "GPIO126/SMB1B_SDA/CP1_GPIO1", {FN_smb1b, FN_cp1gpio1b}, 2, SLEW}, |
| 498 | {127, "GPIO127/SMB1B_SCL/CP1_GPIO0", {FN_smb1b, FN_cp1gpio0b}, 2, SLEW}, |
| 499 | {128, "GPIO128/SMB824_SCL", {FN_smb8}, 1, 0}, |
| 500 | {129, "GPIO129/SMB824_SDA", {FN_smb8}, 1, 0}, |
| 501 | {130, "GPIO130/SMB925_SCL", {FN_smb9}, 1, 0}, |
| 502 | {131, "GPIO131/SMB925_SDA", {FN_smb9}, 1, 0}, |
| 503 | {132, "GPIO132/SMB1026_SCL", {FN_smb10}, 1, 0}, |
| 504 | {133, "GPIO133/SMB1026_SDA", {FN_smb10}, 1, 0}, |
| 505 | {134, "GPIO134/SMB11_SCL", {FN_smb11, FN_smb23b}, 2, 0}, |
| 506 | {135, "GPIO135/SMB11_SDA", {FN_smb11, FN_smb23b}, 2, 0}, |
| 507 | {136, "GPIO136/JM1_TCK", {FN_jm1}, 1, SLEW}, |
| 508 | {137, "GPIO137/JM1_TDO", {FN_jm1}, 1, SLEW}, |
| 509 | {138, "GPIO138/JM1_TMS", {FN_jm1}, 1, SLEW}, |
| 510 | {139, "GPIO139/JM1_TDI", {FN_jm1}, 1, SLEW}, |
| 511 | {140, "GPIO140/JM1_nTRST", {FN_jm1}, 1, SLEW}, |
| 512 | {141, "GPIO141/SMB7B_SCL", {FN_smb7b}, 1, 0}, |
| 513 | {142, "GPIO142/SMB7D_SCL/TPSMB1_SCL", {FN_smb7d, FN_tp_smb1}, 2, SLEW}, |
| 514 | {143, "GPIO143/SMB7D_SDA/TPSMB1_SDA", {FN_smb7d, FN_tp_smb1}, 2, SLEW}, |
| 515 | {144, "GPIO144/PWM4", {FN_pwm4}, 1, DS(4, 8)}, |
| 516 | {145, "GPIO145/PWM5", {FN_pwm5}, 1, DS(4, 8)}, |
| 517 | {146, "GPIO146/PWM6", {FN_pwm6}, 1, DS(4, 8)}, |
| 518 | {147, "GPIO147/PWM7", {FN_pwm7}, 1, DS(4, 8)}, |
| 519 | {148, "GPIO148/MMC_DT4", {FN_mmc8}, 1, DS(8, 12) | SLEW}, |
| 520 | {149, "GPIO149/MMC_DT5", {FN_mmc8}, 1, DS(8, 12) | SLEW}, |
| 521 | {150, "GPIO150/MMC_DT6", {FN_mmc8}, 1, DS(8, 12) | SLEW}, |
| 522 | {151, "GPIO151/MMC_DT7", {FN_mmc8}, 1, DS(8, 12) | SLEW}, |
| 523 | {152, "GPIO152/MMC_CLK", {FN_mmc}, 1, DS(8, 12) | SLEW}, |
| 524 | {153, "GPIO153/MMC_WP", {FN_mmcwp}, 1, 0}, |
| 525 | {154, "GPIO154/MMC_CMD", {FN_mmc}, 1, DS(8, 12) | SLEW}, |
| 526 | {155, "GPIO155/MMC_nCD/MMC_nRSTLK", {FN_mmccd, FN_mmcrst}, 2, 0}, |
| 527 | {156, "GPIO156/MMC_DT0", {FN_mmc}, 1, DS(8, 12) | SLEW}, |
| 528 | {157, "GPIO157/MMC_DT1", {FN_mmc}, 1, DS(8, 12) | SLEW}, |
| 529 | {158, "GPIO158/MMC_DT2", {FN_mmc}, 1, DS(8, 12) | SLEW}, |
| 530 | {159, "GPIO159/MMC_DT3", {FN_mmc}, 1, DS(8, 12) | SLEW}, |
| 531 | {160, "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK", {FN_clkout}, 1, DS(8, 12) | SLEW}, |
| 532 | {161, "GPIO161/ESPI_nCS/LPC_nLFRAME", {FN_espi, FN_lpc}, 2, 0}, |
| 533 | {162, "GPIO162/LPC_nCLKRUN", {FN_clkrun}, 1, DS(8, 12)}, |
| 534 | {163, "GPIO163/ESPI_CK/LPC_LCLK", {FN_espi, FN_lpc}, 2, 0}, |
| 535 | {164, "GPIO164/ESPI_IO0/LPC_LAD0", {FN_espi, FN_lpc}, 2, 0}, |
| 536 | {165, "GPIO165/ESPI_IO1/LPC_LAD1", {FN_espi, FN_lpc}, 2, 0}, |
| 537 | {166, "GPIO166/ESPI_IO2/LPC_LAD2", {FN_espi, FN_lpc}, 2, 0}, |
| 538 | {167, "GPIO167/ESPI_IO3/LPC_LAD3", {FN_espi, FN_lpc}, 2, 0}, |
| 539 | {168, "GPIO168/ESPI_nALERT/SERIRQ", {FN_espi, FN_serirq}, 2, 0}, |
| 540 | {169, "GPIO169/nSCIPME/SMB21_SCL", {FN_scipme, FN_smb21}, 2, 0}, |
| 541 | {170, "GPIO170/nSMI/SMB21_SDA", {FN_sci, FN_smb21}, 2, 0}, |
| 542 | {171, "GPIO171/SMB6_SCL", {FN_smb6}, 1, 0}, |
| 543 | {172, "GPIO172/SMB6_SDA", {FN_smb6}, 1, 0}, |
| 544 | {173, "GPIO173/SMB7_SCL", {FN_smb7}, 1, 0}, |
| 545 | {174, "GPIO174/SMB7_SDA", {FN_smb7}, 1, 0}, |
| 546 | {175, "GPIO175/SPI1_CK/FANIN19/FM1_CK", {FN_spi1, FN_faninx, FN_fm1}, 3, DS(8, 12)}, |
| 547 | {176, "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9", {FN_spi1, FN_faninx, FN_fm1}, 3, DS(8, 12)}, |
| 548 | {177, "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10", {FN_spi1, FN_faninx, FN_fm1}, 3, DS(8, 12)}, |
| 549 | {178, "GPIO178/R1_TXD0", {FN_r1}, 1, DS(8, 12) | SLEW}, |
| 550 | {179, "GPIO179/R1_TXD1", {FN_r1}, 1, DS(8, 12) | SLEW}, |
| 551 | {180, "GPIO180/R1_TXEN", {FN_r1}, 1, DS(8, 12) | SLEW}, |
| 552 | {181, "GPIO181/R1_RXD0", {FN_r1}, 1, 0}, |
| 553 | {182, "GPIO182/R1_RXD1", {FN_r1}, 1, 0}, |
| 554 | {183, "GPIO183/SPI3_SEL", {FN_spi3, FN_gpio1836}, 2, |
| 555 | DS(8, 12) | SLEW | GPIO_ALT | GPIO_IDX(1)}, |
| 556 | {184, "GPIO184/SPI3_D0/STRAP13", {FN_spi3, FN_gpio1836}, 2, |
| 557 | DS(8, 12) | SLEW | GPIO_ALT | GPIO_IDX(1)}, |
| 558 | {185, "GPIO185/SPI3_D1", {FN_spi3, FN_gpio1836}, 2, |
| 559 | DS(8, 12) | SLEW | GPIO_ALT | GPIO_IDX(1)}, |
| 560 | {186, "GPIO186/SPI3_nCS0", {FN_spi3, FN_gpio1836}, 2, |
| 561 | DS(8, 12) | SLEW | GPIO_ALT | GPIO_IDX(1)}, |
| 562 | {187, "GPIO187/SPI3_nCS1_SMB14_SDA", {FN_spi3cs1, FN_smb14b, FN_gpio187}, 3, |
| 563 | SLEW | GPIO_ALT | GPIO_IDX(2)}, |
| 564 | {188, "GPIO188/SPI3_D2/SPI3_nCS2", {FN_spi3quad, FN_spi3cs2, FN_gpio1889}, 3, |
| 565 | DS(8, 12) | SLEW | GPIO_ALT | GPIO_IDX(2)}, |
| 566 | {189, "GPIO189/SPI3_D3/SPI3_nCS3", {FN_spi3quad, FN_spi3cs3, FN_gpio1889}, 3, |
| 567 | DS(8, 12) | SLEW | GPIO_ALT | GPIO_IDX(2)}, |
| 568 | {190, "GPIO190/nPRD_SMI", {FN_nprd_smi}, 1, DS(2, 4)}, |
| 569 | {191, "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10", |
| 570 | {FN_spi1d23, FN_spi1cs2, FN_fm1, FN_smb15}, 4, SLEW}, |
| 571 | {192, "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL", |
| 572 | {FN_spi1d23, FN_spi1cs3, FN_fm1, FN_smb15}, 4, SLEW}, |
| 573 | {193, "GPIO193/R1_CRSDV", {FN_r1}, 1, 0}, |
| 574 | {194, "GPIO194/SMB0B_SCL/FM0_CK", {FN_smb0b, FN_fm0}, 2, SLEW}, |
| 575 | {195, "GPIO195/SMB0B_SDA/FM0_D0", {FN_smb0b, FN_fm0}, 2, SLEW}, |
| 576 | {196, "GPIO196/SMB0C_SCL/FM0_D1", {FN_smb0c, FN_fm0}, 2, SLEW}, |
| 577 | {197, "GPIO197/SMB0DEN/FM0_D3", {FN_smb0den, FN_fm0}, 2, SLEW}, |
| 578 | {198, "GPIO198/SMB0D_SDA/FM0_D2", {FN_smb0d, FN_fm0}, 2, SLEW}, |
| 579 | {199, "GPIO199/SMB0D_SCL/FM0_CSO", {FN_smb0d, FN_fm0}, 2, SLEW}, |
| 580 | {200, "GPIO200/R2_CK", {FN_r2}, 1, 0}, |
| 581 | {201, "GPIO201/R1_CK", {FN_r1}, 1, 0}, |
| 582 | {202, "GPIO202/SMB0C_SDA/FM0_CSI", {FN_smb0c, FN_fm0}, 2, SLEW}, |
| 583 | {203, "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI", {FN_faninx, FN_spi1, FN_fm1}, 3, DS(8, 12)}, |
| 584 | {208, "GPIO208/RG2_TXC/DVCK", {FN_rg2, FN_ddr}, 2, SLEW}, |
| 585 | {209, "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN", {FN_rg2, FN_ddr, FN_rmii3}, 3, SLEW}, |
| 586 | {210, "GPIO210/RG2_RXD0/DDRV5/R3_RXD0", {FN_rg2, FN_ddr, FN_rmii3}, 3, DS(8, 12) | SLEW}, |
| 587 | {211, "GPIO211/RG2_RXD1/DDRV6/R3_RXD1", {FN_rg2, FN_ddr, FN_rmii3}, 3, DS(8, 12) | SLEW}, |
| 588 | {212, "GPIO212/RG2_RXD2/DDRV7/R3_RXD2", {FN_rg2, FN_ddr, FN_r3rxer}, 3, DS(8, 12) | SLEW}, |
| 589 | {213, "GPIO213/RG2_RXD3/DDRV8/R3_OEN", {FN_rg2, FN_ddr, FN_r3oen}, 3, DS(8, 12) | SLEW}, |
| 590 | {214, "GPIO214/RG2_RXC/DDRV9/R3_CK", {FN_rg2, FN_ddr, FN_rmii3}, 3, DS(8, 12) | SLEW}, |
| 591 | {215, "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV", {FN_rg2, FN_ddr, FN_rmii3}, 3, DS(8, 12) | SLEW}, |
| 592 | {216, "GPIO216/RG2_MDC/DDRV11", {FN_rg2mdio, FN_ddr}, 2, DS(8, 12) | SLEW}, |
| 593 | {217, "GPIO217/RG2_MDIO/DVHSYNC", {FN_rg2mdio, FN_ddr}, 2, DS(8, 12) | SLEW}, |
| 594 | {218, "GPIO218/nWDO1/SMB16_SCL", {FN_wdog1, FN_smb16}, 2, SLEW}, |
| 595 | {219, "GPIO219/nWDO2/SMB16_SDA", {FN_wdog2, FN_smb16}, 2, SLEW}, |
| 596 | {220, "GPIO220/SMB12_SCL/PWM8", {FN_smb12, FN_pwm8}, 2, SLEW}, |
| 597 | {221, "GPIO221/SMB12_SDA/PWM9", {FN_smb12, FN_pwm9}, 2, SLEW}, |
| 598 | {222, "GPIO222/SMB13_SCL", {FN_smb13}, 1, SLEW}, |
| 599 | {223, "GPIO223/SMB13_SDA", {FN_smb13}, 1, SLEW}, |
| 600 | {224, "GPIO224/SPIX_CK/FM2_CK", {FN_spix, FN_fm2}, 2, DS(8, 12) | SLEW}, |
| 601 | {225, "GPO225/SPIX_D0/FM2_D0/STRAP1", {FN_spix, FN_fm2}, 2, DS(8, 12) | SLEW}, |
| 602 | {226, "GPO226/SPIX_D1/FM2_D1/STRAP2", {FN_spix, FN_fm2}, 2, DS(8, 12) | SLEW}, |
| 603 | {227, "GPIO227/SPIX_nCS0/FM2_CSI", {FN_spix, FN_fm2}, 2, DS(8, 12) | SLEW}, |
| 604 | {228, "GPIO228/SPIX_nCS1/FM2_CSO", {FN_spixcs1, FN_fm2}, 2, DS(8, 12) | SLEW}, |
| 605 | {229, "GPO229/SPIX_D2/FM2_D2/STRAP3", {FN_spix, FN_fm2}, 2, DS(8, 12) | SLEW}, |
| 606 | {230, "GPO230/SPIX_D3/FM2_D3/STRAP6", {FN_spix, FN_fm2}, 2, DS(8, 12) | SLEW}, |
| 607 | {231, "GPIO231/EP_nCLKREQ", {FN_clkreq}, 1, DS(4, 12) | SLEW}, |
| 608 | {233, "GPIO233/SPI1_nCS1/FM1_CSO", {FN_spi1cs1, FN_fm1}, 2, 0}, |
| 609 | {234, "GPIO234/PWM10/SMB20_SCL", {FN_pwm10, FN_smb20}, 2, SLEW}, |
| 610 | {235, "GPIO235/PWM11/SMB20_SDA", {FN_pwm11, FN_smb20}, 2, SLEW}, |
| 611 | {240, "GPIO240/I3C0_SCL", {FN_i3c0}, 2, SLEW}, |
| 612 | {241, "GPIO241/I3C0_SDA", {FN_i3c0}, 2, SLEW}, |
| 613 | {242, "GPIO242/I3C1_SCL", {FN_i3c1}, 2, SLEW}, |
| 614 | {243, "GPIO243/I3C1_SDA", {FN_i3c1}, 2, SLEW}, |
| 615 | {244, "GPIO244/I3C2_SCL", {FN_i3c2}, 2, SLEW}, |
| 616 | {245, "GPIO245/I3C2_SDA", {FN_i3c2}, 2, SLEW}, |
| 617 | {246, "GPIO246/I3C3_SCL", {FN_i3c3}, 2, SLEW}, |
| 618 | {247, "GPIO247/I3C3_SDA", {FN_i3c3}, 2, SLEW}, |
| 619 | {250, "GPIO250/RG2_REFCK/DVVSYNC", {FN_ddr, FN_rg2refck}, 2, DS(8, 12) | SLEW}, |
| 620 | }; |
| 621 | |
| 622 | static int npcm8xx_get_pin_selector(u8 gpio) |
| 623 | { |
| 624 | int i; |
| 625 | |
| 626 | for (i = 0; i < ARRAY_SIZE(npcm8xx_pins); i++) { |
| 627 | if (npcm8xx_pins[i].gpio_num == gpio) |
| 628 | return i; |
| 629 | } |
| 630 | |
| 631 | return -ENOENT; |
| 632 | } |
| 633 | |
| 634 | static int npcm8xx_group_set_func(struct udevice *dev, |
| 635 | const struct group_info *group, |
| 636 | unsigned int func_selector) |
| 637 | { |
| 638 | struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev); |
| 639 | |
| 640 | dev_dbg(dev, "set_func [grp %s][func %s]\n", group->name, |
| 641 | npcm8xx_groups[func_selector].name); |
| 642 | if (group->id == func_selector) |
| 643 | regmap_update_bits(priv->gcr_regmap, group->reg, |
| 644 | BIT(group->bit), BIT(group->bit)); |
| 645 | else |
| 646 | regmap_update_bits(priv->gcr_regmap, group->reg, |
| 647 | BIT(group->bit), 0); |
| 648 | |
| 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | static int npcm8xx_pinmux_set(struct udevice *dev, |
| 653 | unsigned int pin_selector, |
| 654 | unsigned int func_selector) |
| 655 | { |
| 656 | const struct pin_info *pin; |
| 657 | const struct group_info *group; |
| 658 | int i; |
| 659 | |
| 660 | pin = &npcm8xx_pins[pin_selector]; |
| 661 | dev_dbg(dev, "set_mux [pin %s][func %s]\n", pin->name, |
| 662 | npcm8xx_groups[func_selector].name); |
| 663 | |
| 664 | for (i = 0; i < pin->num_funcs; i++) { |
| 665 | group = &npcm8xx_groups[pin->funcs[i]]; |
| 666 | npcm8xx_group_set_func(dev, group, func_selector); |
| 667 | } |
| 668 | |
| 669 | return 0; |
| 670 | } |
| 671 | |
| 672 | static int npcm8xx_pinmux_group_set(struct udevice *dev, |
| 673 | unsigned int group_selector, |
| 674 | unsigned int func_selector) |
| 675 | { |
| 676 | const struct group_info *group; |
| 677 | int pin_selector; |
| 678 | int i; |
| 679 | |
| 680 | dev_dbg(dev, "set_mux [grp %s][func %s]\n", |
| 681 | npcm8xx_groups[group_selector].name, |
| 682 | npcm8xx_groups[func_selector].name); |
| 683 | group = &npcm8xx_groups[group_selector]; |
| 684 | |
| 685 | if (!group->npins) { |
| 686 | /* No other alternate pins, just set group function */ |
| 687 | npcm8xx_group_set_func(dev, group, func_selector); |
| 688 | return 0; |
| 689 | } |
| 690 | |
| 691 | for (i = 0; i < group->npins; i++) { |
| 692 | pin_selector = npcm8xx_get_pin_selector(group->pins[i]); |
| 693 | if (pin_selector < 0) { |
| 694 | dev_dbg(dev, "invalid pin %d\n", group->pins[i]); |
| 695 | return -EINVAL; |
| 696 | } |
| 697 | npcm8xx_pinmux_set(dev, pin_selector, func_selector); |
| 698 | } |
| 699 | |
| 700 | return 0; |
| 701 | } |
| 702 | |
| 703 | static int npcm8xx_get_pins_count(struct udevice *dev) |
| 704 | { |
| 705 | return ARRAY_SIZE(npcm8xx_pins); |
| 706 | } |
| 707 | |
| 708 | static const char *npcm8xx_get_pin_name(struct udevice *dev, |
| 709 | unsigned int selector) |
| 710 | { |
| 711 | return npcm8xx_pins[selector].name; |
| 712 | } |
| 713 | |
| 714 | static int npcm8xx_get_groups_count(struct udevice *dev) |
| 715 | { |
| 716 | return ARRAY_SIZE(npcm8xx_groups); |
| 717 | } |
| 718 | |
| 719 | static const char *npcm8xx_get_group_name(struct udevice *dev, |
| 720 | unsigned int selector) |
| 721 | { |
| 722 | return npcm8xx_groups[selector].name; |
| 723 | } |
| 724 | |
| 725 | static int npcm8xx_get_functions_count(struct udevice *dev) |
| 726 | { |
| 727 | return ARRAY_SIZE(npcm8xx_groups); |
| 728 | } |
| 729 | |
| 730 | static const char *npcm8xx_get_function_name(struct udevice *dev, |
| 731 | unsigned int selector) |
| 732 | { |
| 733 | return npcm8xx_groups[selector].name; |
| 734 | } |
| 735 | |
| 736 | #if CONFIG_IS_ENABLED(PINCONF) |
| 737 | #define PIN_CONFIG_PERSIST_STATE (PIN_CONFIG_END + 1) |
| 738 | #define PIN_CONFIG_POLARITY_STATE (PIN_CONFIG_END + 2) |
| 739 | #define PIN_CONFIG_EVENT_CLEAR (PIN_CONFIG_END + 3) |
| 740 | |
| 741 | static const struct pinconf_param npcm8xx_conf_params[] = { |
| 742 | { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, |
| 743 | { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, |
| 744 | { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, |
| 745 | { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, |
| 746 | { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, |
| 747 | { "output-high", PIN_CONFIG_OUTPUT, 1, }, |
| 748 | { "output-low", PIN_CONFIG_OUTPUT, 0, }, |
| 749 | { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 1 }, |
| 750 | { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 1 }, |
| 751 | { "persist-enable", PIN_CONFIG_PERSIST_STATE, 1 }, |
| 752 | { "persist-disable", PIN_CONFIG_PERSIST_STATE, 0 }, |
| 753 | { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, |
| 754 | { "active-high", PIN_CONFIG_POLARITY_STATE, 0 }, |
| 755 | { "active-low", PIN_CONFIG_POLARITY_STATE, 1 }, |
| 756 | { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, |
| 757 | { "slew-rate", PIN_CONFIG_SLEW_RATE, 0}, |
| 758 | { "event-clear", PIN_CONFIG_EVENT_CLEAR, 0}, |
| 759 | }; |
| 760 | |
| 761 | /* Support for retaining the state after soft reset */ |
| 762 | static int npcm8xx_gpio_reset_persist(struct udevice *dev, uint bank, |
| 763 | uint enable) |
| 764 | { |
| 765 | struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev); |
| 766 | u8 offset = bank + GPIOX_OFFSET; |
| 767 | |
| 768 | dev_dbg(dev, "set gpio persist, bank %d, enable %d\n", bank, enable); |
| 769 | |
| 770 | if (enable) { |
| 771 | regmap_update_bits(priv->rst_regmap, WD0RCR, BIT(offset), 0); |
| 772 | regmap_update_bits(priv->rst_regmap, WD1RCR, BIT(offset), 0); |
| 773 | regmap_update_bits(priv->rst_regmap, WD2RCR, BIT(offset), 0); |
| 774 | regmap_update_bits(priv->rst_regmap, CORSTC, BIT(offset), 0); |
| 775 | } else { |
| 776 | regmap_update_bits(priv->rst_regmap, WD0RCR, BIT(offset), |
| 777 | BIT(offset)); |
| 778 | regmap_update_bits(priv->rst_regmap, WD1RCR, BIT(offset), |
| 779 | BIT(offset)); |
| 780 | regmap_update_bits(priv->rst_regmap, WD2RCR, BIT(offset), |
| 781 | BIT(offset)); |
| 782 | regmap_update_bits(priv->rst_regmap, CORSTC, BIT(offset), |
| 783 | BIT(offset)); |
| 784 | } |
| 785 | |
| 786 | return 0; |
| 787 | } |
| 788 | |
| 789 | static bool is_gpio_persist(struct udevice *dev, uint bank) |
| 790 | { |
| 791 | struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev); |
| 792 | u8 offset = bank + GPIOX_OFFSET; |
| 793 | u32 val; |
| 794 | int status; |
| 795 | |
| 796 | status = npcm_get_reset_status(); |
| 797 | dev_dbg(dev, "reset status: 0x%x\n", status); |
| 798 | |
| 799 | if (status & CORST) |
| 800 | regmap_read(priv->rst_regmap, CORSTC, &val); |
| 801 | else if (status & WD0RST) |
| 802 | regmap_read(priv->rst_regmap, WD0RCR, &val); |
| 803 | else if (status & WD1RST) |
| 804 | regmap_read(priv->rst_regmap, WD1RCR, &val); |
| 805 | else if (status & WD2RST) |
| 806 | regmap_read(priv->rst_regmap, WD2RCR, &val); |
| 807 | else |
| 808 | return false; |
| 809 | |
| 810 | return !(val & BIT(offset)); |
| 811 | } |
| 812 | |
| 813 | static void npcm8xx_set_gpio_func(struct udevice *dev, unsigned int selector) |
| 814 | { |
| 815 | const struct pin_info *pin = &npcm8xx_pins[selector]; |
| 816 | const struct group_info *group; |
| 817 | unsigned int func_selector; |
| 818 | int i; |
| 819 | |
| 820 | /* gpio function is an alternate function */ |
| 821 | if (pin->flags & GPIO_ALT) |
| 822 | func_selector = pin->funcs[GPIO_IDX_VAL(pin->flags)]; |
| 823 | else |
| 824 | func_selector = FN_gpio; |
| 825 | |
| 826 | for (i = 0; i < pin->num_funcs; i++) { |
| 827 | group = &npcm8xx_groups[pin->funcs[i]]; |
| 828 | npcm8xx_group_set_func(dev, group, func_selector); |
| 829 | } |
| 830 | } |
| 831 | |
| 832 | static int npcm8xx_pinconf_set(struct udevice *dev, unsigned int selector, |
| 833 | unsigned int param, unsigned int arg) |
| 834 | { |
| 835 | struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev); |
| 836 | uint pin = npcm8xx_pins[selector].gpio_num; |
| 837 | uint bank = pin / NPCM8XX_GPIO_PER_BANK; |
| 838 | uint gpio = (pin % NPCM8XX_GPIO_PER_BANK); |
| 839 | void __iomem *base = priv->gpio_base + (0x1000 * bank); |
| 840 | u32 flags = npcm8xx_pins[selector].flags; |
| 841 | int ret = 0; |
| 842 | |
| 843 | dev_dbg(dev, "set_conf [pin %d][param 0x%x, arg 0x%x]\n", |
| 844 | pin, param, arg); |
| 845 | |
| 846 | /* Configure pin as gpio function */ |
| 847 | if (param != PIN_CONFIG_SLEW_RATE) |
| 848 | npcm8xx_set_gpio_func(dev, selector); |
| 849 | |
| 850 | if (is_gpio_persist(dev, bank) && |
| 851 | param != PIN_CONFIG_EVENT_CLEAR) { |
| 852 | dev_dbg(dev, "retain the state\n"); |
| 853 | return 0; |
| 854 | } |
| 855 | |
| 856 | switch (param) { |
| 857 | case PIN_CONFIG_BIAS_DISABLE: |
| 858 | dev_dbg(dev, "set pin %d bias disable\n", pin); |
| 859 | clrbits_le32(base + GPIO_PU, BIT(gpio)); |
| 860 | clrbits_le32(base + GPIO_PD, BIT(gpio)); |
| 861 | break; |
| 862 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 863 | dev_dbg(dev, "set pin %d bias pull down\n", pin); |
| 864 | clrbits_le32(base + GPIO_PU, BIT(gpio)); |
| 865 | setbits_le32(base + GPIO_PD, BIT(gpio)); |
| 866 | break; |
| 867 | case PIN_CONFIG_BIAS_PULL_UP: |
| 868 | dev_dbg(dev, "set pin %d bias pull up\n", pin); |
| 869 | setbits_le32(base + GPIO_PU, BIT(gpio)); |
| 870 | clrbits_le32(base + GPIO_PD, BIT(gpio)); |
| 871 | break; |
| 872 | case PIN_CONFIG_INPUT_ENABLE: |
| 873 | dev_dbg(dev, "set pin %d input enable\n", pin); |
| 874 | setbits_le32(base + GPIO_OEC, BIT(gpio)); |
| 875 | setbits_le32(base + GPIO_IEM, BIT(gpio)); |
| 876 | break; |
| 877 | case PIN_CONFIG_OUTPUT_ENABLE: |
| 878 | dev_dbg(dev, "set pin %d output enable\n", pin); |
| 879 | clrbits_le32(base + GPIO_IEM, BIT(gpio)); |
| 880 | setbits_le32(base + GPIO_OES, BIT(gpio)); |
| 881 | case PIN_CONFIG_OUTPUT: |
| 882 | dev_dbg(dev, "set pin %d output %d\n", pin, arg); |
| 883 | clrbits_le32(base + GPIO_IEM, BIT(gpio)); |
| 884 | setbits_le32(base + GPIO_OES, BIT(gpio)); |
| 885 | if (arg) |
| 886 | setbits_le32(base + GPIO_DOUT, BIT(gpio)); |
| 887 | else |
| 888 | clrbits_le32(base + GPIO_DOUT, BIT(gpio)); |
| 889 | break; |
| 890 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
| 891 | dev_dbg(dev, "set pin %d push pull\n", pin); |
| 892 | clrbits_le32(base + GPIO_OTYP, BIT(gpio)); |
| 893 | break; |
| 894 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
| 895 | dev_dbg(dev, "set pin %d open drain\n", pin); |
| 896 | setbits_le32(base + GPIO_OTYP, BIT(gpio)); |
| 897 | break; |
| 898 | case PIN_CONFIG_INPUT_DEBOUNCE: |
| 899 | dev_dbg(dev, "set pin %d input debounce\n", pin); |
| 900 | setbits_le32(base + GPIO_DBNC, BIT(gpio)); |
| 901 | break; |
| 902 | case PIN_CONFIG_POLARITY_STATE: |
| 903 | dev_dbg(dev, "set pin %d active %d\n", pin, arg); |
| 904 | if (arg) |
| 905 | setbits_le32(base + GPIO_POL, BIT(gpio)); |
| 906 | else |
| 907 | clrbits_le32(base + GPIO_POL, BIT(gpio)); |
| 908 | break; |
| 909 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 910 | dev_dbg(dev, "set pin %d driver strength %d\n", pin, arg); |
| 911 | if (DSLO(flags) == arg) |
| 912 | clrbits_le32(base + GPIO_ODSC, BIT(gpio)); |
| 913 | else if (DSHI(flags) == arg) |
| 914 | setbits_le32(base + GPIO_ODSC, BIT(gpio)); |
| 915 | else |
| 916 | ret = -EOPNOTSUPP; |
| 917 | break; |
| 918 | case PIN_CONFIG_SLEW_RATE: |
| 919 | dev_dbg(dev, "set pin %d slew rate %d\n", pin, arg); |
| 920 | if (!(flags & SLEW)) { |
| 921 | ret = -EOPNOTSUPP; |
| 922 | break; |
| 923 | } |
| 924 | if (arg) |
| 925 | setbits_le32(base + GPIO_OSRC, BIT(gpio)); |
| 926 | else |
| 927 | clrbits_le32(base + GPIO_OSRC, BIT(gpio)); |
| 928 | break; |
| 929 | case PIN_CONFIG_EVENT_CLEAR: |
| 930 | dev_dbg(dev, "set pin %d event clear\n", pin); |
| 931 | clrbits_le32(base + GPIO_EVEN, BIT(gpio)); |
| 932 | setbits_le32(base + GPIO_EVST, BIT(gpio)); |
| 933 | break; |
| 934 | case PIN_CONFIG_PERSIST_STATE: |
| 935 | npcm8xx_gpio_reset_persist(dev, bank, arg); |
| 936 | break; |
| 937 | |
| 938 | default: |
| 939 | ret = -EOPNOTSUPP; |
| 940 | } |
| 941 | |
| 942 | return ret; |
| 943 | } |
| 944 | #endif |
| 945 | |
| 946 | static struct pinctrl_ops npcm8xx_pinctrl_ops = { |
| 947 | .set_state = pinctrl_generic_set_state, |
| 948 | .get_pins_count = npcm8xx_get_pins_count, |
| 949 | .get_pin_name = npcm8xx_get_pin_name, |
| 950 | .get_groups_count = npcm8xx_get_groups_count, |
| 951 | .get_group_name = npcm8xx_get_group_name, |
| 952 | .get_functions_count = npcm8xx_get_functions_count, |
| 953 | .get_function_name = npcm8xx_get_function_name, |
| 954 | .pinmux_set = npcm8xx_pinmux_set, |
| 955 | .pinmux_group_set = npcm8xx_pinmux_group_set, |
| 956 | #if CONFIG_IS_ENABLED(PINCONF) |
| 957 | .pinconf_num_params = ARRAY_SIZE(npcm8xx_conf_params), |
| 958 | .pinconf_params = npcm8xx_conf_params, |
| 959 | .pinconf_set = npcm8xx_pinconf_set, |
| 960 | .pinconf_group_set = npcm8xx_pinconf_set, |
| 961 | #endif |
| 962 | }; |
| 963 | |
| 964 | static int npcm8xx_pinctrl_probe(struct udevice *dev) |
| 965 | { |
| 966 | struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev); |
| 967 | |
| 968 | priv->gpio_base = dev_read_addr_ptr(dev); |
| 969 | if (!priv->gpio_base) |
| 970 | return -EINVAL; |
| 971 | |
| 972 | priv->gcr_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-gcr"); |
| 973 | if (IS_ERR(priv->gcr_regmap)) |
| 974 | return -EINVAL; |
| 975 | |
| 976 | priv->rst_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-rst"); |
| 977 | if (IS_ERR(priv->rst_regmap)) |
| 978 | return -EINVAL; |
| 979 | |
| 980 | return 0; |
| 981 | } |
| 982 | |
| 983 | static const struct udevice_id npcm8xx_pinctrl_ids[] = { |
| 984 | { .compatible = "nuvoton,npcm845-pinctrl" }, |
| 985 | { } |
| 986 | }; |
| 987 | |
| 988 | U_BOOT_DRIVER(pinctrl_npcm8xx) = { |
| 989 | .name = "nuvoton_npcm8xx_pinctrl", |
| 990 | .id = UCLASS_PINCTRL, |
| 991 | .of_match = npcm8xx_pinctrl_ids, |
| 992 | .priv_auto = sizeof(struct npcm8xx_pinctrl_priv), |
| 993 | .ops = &npcm8xx_pinctrl_ops, |
| 994 | .probe = npcm8xx_pinctrl_probe, |
| 995 | }; |