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wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk3edb6202014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf4675562002-10-02 14:20:15 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
21#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
22
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0x40000000
24
wdenkf4675562002-10-02 14:20:15 +000025#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denkf0d526a2009-07-28 22:13:52 +020026#define CONFIG_SYS_SMC_RXBUFLEN 128
27#define CONFIG_SYS_MAXIDLE 10
wdenk34b613e2002-12-17 01:51:00 +000028
wdenkfb229ae2003-08-07 22:18:11 +000029#define CONFIG_BOOTCOUNT_LIMIT
wdenkf4675562002-10-02 14:20:15 +000030
wdenkf4675562002-10-02 14:20:15 +000031
32#define CONFIG_BOARD_TYPES 1 /* support board types */
33
wdenk34b613e2002-12-17 01:51:00 +000034#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +010035 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk34b613e2002-12-17 01:51:00 +000036 "echo"
wdenkf4675562002-10-02 14:20:15 +000037
38#undef CONFIG_BOOTARGS
wdenk34b613e2002-12-17 01:51:00 +000039
40#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkfb229ae2003-08-07 22:18:11 +000041 "netdev=eth0\0" \
wdenk34b613e2002-12-17 01:51:00 +000042 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010043 "nfsroot=${serverip}:${rootpath}\0" \
wdenk34b613e2002-12-17 01:51:00 +000044 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010045 "addip=setenv bootargs ${bootargs} " \
46 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
47 ":${hostname}:${netdev}:off panic=1\0" \
wdenk34b613e2002-12-17 01:51:00 +000048 "flash_nfs=run nfsargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010049 "bootm ${kernel_addr}\0" \
wdenk34b613e2002-12-17 01:51:00 +000050 "flash_self=run ramargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010051 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
52 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk34b613e2002-12-17 01:51:00 +000053 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +020054 "hostname=TQM855L\0" \
55 "bootfile=TQM855L/uImage\0" \
Wolfgang Denk64ab5182007-09-16 02:39:35 +020056 "fdt_addr=40040000\0" \
57 "kernel_addr=40060000\0" \
58 "ramdisk_addr=40200000\0" \
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +020059 "u-boot=TQM855L/u-image.bin\0" \
60 "load=tftp 200000 ${u-boot}\0" \
61 "update=prot off 40000000 +${filesize};" \
62 "era 40000000 +${filesize};" \
63 "cp.b 200000 40000000 ${filesize};" \
64 "sete filesize;save\0" \
wdenk34b613e2002-12-17 01:51:00 +000065 ""
66#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000067
68#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000070
71#undef CONFIG_WATCHDOG /* watchdog disabled */
72
wdenkf4675562002-10-02 14:20:15 +000073#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
74
Jon Loeliger530ca672007-07-09 21:38:02 -050075/*
76 * BOOTP options
77 */
78#define CONFIG_BOOTP_SUBNETMASK
79#define CONFIG_BOOTP_GATEWAY
80#define CONFIG_BOOTP_HOSTNAME
81#define CONFIG_BOOTP_BOOTPATH
82#define CONFIG_BOOTP_BOOTFILESIZE
83
wdenkf4675562002-10-02 14:20:15 +000084#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
85
Jon Loeligeredccb462007-07-04 22:30:50 -050086/*
87 * Command line configuration.
88 */
Jon Loeligeredccb462007-07-04 22:30:50 -050089#define CONFIG_CMD_IDE
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +020090#define CONFIG_CMD_JFFS2
wdenkf4675562002-10-02 14:20:15 +000091
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +020092#define CONFIG_NETCONSOLE
93
wdenkf4675562002-10-02 14:20:15 +000094/*
95 * Miscellaneous configurable options
96 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020097#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk34b613e2002-12-17 01:51:00 +000098
Wolfgang Denk274bac52006-10-28 02:29:14 +020099#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
wdenk34b613e2002-12-17 01:51:00 +0000100
Jon Loeligeredccb462007-07-04 22:30:50 -0500101#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000103#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000105#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
107#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
108#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000109
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
111#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000112
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200113#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000114
wdenkf4675562002-10-02 14:20:15 +0000115/*
116 * Low Level Configuration Settings
117 * (address mappings, register initial values, etc.)
118 * You should know what you are doing if you make changes here.
119 */
120/*-----------------------------------------------------------------------
121 * Internal Memory Mapped Register
122 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000124
125/*-----------------------------------------------------------------------
126 * Definitions for initial stack pointer and data area (in DPRAM)
127 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200128#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200129#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200130#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000132
133/*-----------------------------------------------------------------------
134 * Start addresses for the final memory configuration
135 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000137 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_SDRAM_BASE 0x00000000
139#define CONFIG_SYS_FLASH_BASE 0x40000000
140#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
141#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
142#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000143
144/*
145 * For booting Linux, the board info and command line data
146 * have to be in the first 8 MB of memory, since this is
147 * the maximum mapped by the Linux kernel during initialization.
148 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000150
151/*-----------------------------------------------------------------------
152 * FLASH organization
153 */
wdenkf4675562002-10-02 14:20:15 +0000154
Martin Krausec098b0e2007-09-27 11:10:08 +0200155/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200157#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
159#define CONFIG_SYS_FLASH_EMPTY_INFO
160#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
161#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
162#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000163
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200164#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200165#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
166#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000167
168/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200169#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
170#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000171
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk4ed40bb2007-09-16 17:10:04 +0200173
Wolfgang Denk8d82cc02008-09-16 18:02:19 +0200174#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
175
wdenkf4675562002-10-02 14:20:15 +0000176/*-----------------------------------------------------------------------
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200177 * Dynamic MTD partition support
178 */
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100179#define CONFIG_CMD_MTDPARTS
Stefan Roese5dc958f2009-05-12 14:32:58 +0200180#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
181#define CONFIG_FLASH_CFI_MTD
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200182#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
183
184#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
185 "128k(dtb)," \
186 "1664k(kernel)," \
187 "2m(rootfs)," \
Wolfgang Denk1ec16772008-08-12 16:08:38 +0200188 "4m(data)"
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200189
190/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000191 * Hardware Information Block
192 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
194#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
195#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000196
197/*-----------------------------------------------------------------------
198 * Cache Configuration
199 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligeredccb462007-07-04 22:30:50 -0500201#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000203#endif
204
205/*-----------------------------------------------------------------------
206 * SYPCR - System Protection Control 11-9
207 * SYPCR can only be written once after reset!
208 *-----------------------------------------------------------------------
209 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
210 */
211#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000213 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
214#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200215#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000216#endif
217
218/*-----------------------------------------------------------------------
219 * SIUMCR - SIU Module Configuration 11-6
220 *-----------------------------------------------------------------------
221 * PCMCIA config., multi-function pin tri-state
222 */
223#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000225#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000227#endif /* CONFIG_CAN_DRIVER */
228
229/*-----------------------------------------------------------------------
230 * TBSCR - Time Base Status and Control 11-26
231 *-----------------------------------------------------------------------
232 * Clear Reference Interrupt Status, Timebase freezing enabled
233 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200234#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000235
236/*-----------------------------------------------------------------------
237 * RTCSC - Real-Time Clock Status and Control Register 11-27
238 *-----------------------------------------------------------------------
239 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000241
242/*-----------------------------------------------------------------------
243 * PISCR - Periodic Interrupt Status and Control 11-31
244 *-----------------------------------------------------------------------
245 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
246 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200247#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000248
249/*-----------------------------------------------------------------------
250 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
251 *-----------------------------------------------------------------------
252 * Reset PLL lock status sticky bit, timer expired status bit and timer
253 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000254 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000256
257/*-----------------------------------------------------------------------
258 * SCCR - System Clock and reset Control Register 15-27
259 *-----------------------------------------------------------------------
260 * Set clock output, timebase and RTC source and divider,
261 * power management and some other internal clocks
262 */
263#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000265 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
266 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000267
268/*-----------------------------------------------------------------------
269 * PCMCIA stuff
270 *-----------------------------------------------------------------------
271 *
272 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200273#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
274#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
275#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
276#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
277#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
278#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
279#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
280#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000281
282/*-----------------------------------------------------------------------
283 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
284 *-----------------------------------------------------------------------
285 */
286
Pavel Herrmann2c13c4a2012-10-09 07:01:56 +0000287#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf4675562002-10-02 14:20:15 +0000288#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
289
290#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
291#undef CONFIG_IDE_LED /* LED for ide not supported */
292#undef CONFIG_IDE_RESET /* reset for ide not supported */
293
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200294#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
295#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000296
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200297#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000298
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000300
301/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200302#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000303
304/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000306
307/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200308#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000309
wdenkf4675562002-10-02 14:20:15 +0000310/*-----------------------------------------------------------------------
311 *
312 *-----------------------------------------------------------------------
313 *
314 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200315#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000316
317/*
318 * Init Memory Controller:
319 *
320 * BR0/1 and OR0/1 (FLASH)
321 */
322
323#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
324#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
325
326/* used to re-map FLASH both when starting from SRAM or FLASH:
327 * restrict access enough to keep SRAM working (if any)
328 * but not too much to meddle with FLASH accesses
329 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200330#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
331#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000332
333/*
334 * FLASH timing:
335 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200336#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000337 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000338
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200339#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
340#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
341#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000342
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200343#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
344#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
345#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000346
347/*
348 * BR2/3 and OR2/3 (SDRAM)
349 *
350 */
351#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
352#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
353#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
354
355/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200356#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000357
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200358#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
359#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000360
361#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200362#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
363#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000364#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200365#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
366#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
367#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
368#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000369 BR_PS_8 | BR_MS_UPMB | BR_V )
370#endif /* CONFIG_CAN_DRIVER */
371
372/*
373 * Memory Periodic Timer Prescaler
374 *
375 * The Divider for PTA (refresh timer) configuration is based on an
376 * example SDRAM configuration (64 MBit, one bank). The adjustment to
377 * the number of chip selects (NCS) and the actually needed refresh
378 * rate is done by setting MPTPR.
379 *
380 * PTA is calculated from
381 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
382 *
383 * gclk CPU clock (not bus clock!)
384 * Trefresh Refresh cycle * 4 (four word bursts used)
385 *
386 * 4096 Rows from SDRAM example configuration
387 * 1000 factor s -> ms
388 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
389 * 4 Number of refresh cycles per period
390 * 64 Refresh cycle in ms per number of rows
391 * --------------------------------------------
392 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
393 *
394 * 50 MHz => 50.000.000 / Divider = 98
395 * 66 Mhz => 66.000.000 / Divider = 129
396 * 80 Mhz => 80.000.000 / Divider = 156
397 */
wdenkc78bf132004-04-24 23:23:30 +0000398
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200399#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
400#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000401
402/*
403 * For 16 MBit, refresh rates could be 31.3 us
404 * (= 64 ms / 2K = 125 / quad bursts).
405 * For a simpler initialization, 15.6 us is used instead.
406 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200407 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
408 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000409 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200410#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
411#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000412
413/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200414#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
415#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000416
417/*
418 * MAMR settings for SDRAM
419 */
420
421/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200422#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000423 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
424 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
425/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200426#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000427 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
428 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
429
wdenkf4675562002-10-02 14:20:15 +0000430#define CONFIG_SCC1_ENET
wdenk34b613e2002-12-17 01:51:00 +0000431#define CONFIG_FEC_ENET
Heiko Schocherc5e84052010-07-20 17:45:02 +0200432#define CONFIG_ETHPRIME "SCC"
wdenkf4675562002-10-02 14:20:15 +0000433
Heiko Schocherc95fa8b2010-02-09 15:50:27 +0100434#define CONFIG_HWCONFIG 1
435
wdenkf4675562002-10-02 14:20:15 +0000436#endif /* __CONFIG_H */