blob: 425b3f93c865b6addf7807b583d014a3762fd0ac [file] [log] [blame]
Lokesh Vutla32886442018-08-27 15:57:09 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
Andrew F. Davis2dbe3892020-01-10 14:35:20 -05003 * AM6: SoC specific initialization
Lokesh Vutla32886442018-08-27 15:57:09 +05304 *
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
7 */
8
9#include <common.h>
Faiz Abbas3385a862020-08-03 11:35:09 +053010#include <fdt_support.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Lokesh Vutlac7bfb852018-08-27 15:57:11 +053013#include <asm/io.h>
Lokesh Vutla32886442018-08-27 15:57:09 +053014#include <spl.h>
Lokesh Vutlac7bfb852018-08-27 15:57:11 +053015#include <asm/arch/hardware.h>
Andreas Dannenbergea91da12019-06-04 17:55:50 -050016#include <asm/arch/sysfw-loader.h>
Andreas Dannenberg63f5c852019-06-04 18:08:26 -050017#include <asm/arch/sys_proto.h>
Lokesh Vutlac1e60e82018-11-02 19:51:03 +053018#include "common.h"
Lokesh Vutla2c69d5c2018-11-02 19:51:06 +053019#include <dm.h>
Andreas Dannenbergea91da12019-06-04 17:55:50 -050020#include <dm/uclass-internal.h>
21#include <dm/pinctrl.h>
Andreas Dannenberg31175f82019-06-07 19:24:42 +053022#include <linux/soc/ti/ti_sci_protocol.h>
Faiz Abbasfe1217e2020-08-03 11:35:06 +053023#include <log.h>
Faiz Abbas68393212020-02-26 13:44:36 +053024#include <mmc.h>
Faiz Abbasfe1217e2020-08-03 11:35:06 +053025#include <stdlib.h>
Lokesh Vutla32886442018-08-27 15:57:09 +053026
Faiz Abbas3385a862020-08-03 11:35:09 +053027DECLARE_GLOBAL_DATA_PTR;
28
Lokesh Vutla32886442018-08-27 15:57:09 +053029#ifdef CONFIG_SPL_BUILD
Andrew F. Davisf0bcb662020-01-10 14:35:21 -050030#ifdef CONFIG_K3_LOAD_SYSFW
31#ifdef CONFIG_TI_SECURE_DEVICE
32struct fwl_data main_cbass_fwls[] = {
33 { "MMCSD1_CFG", 2057, 1 },
34 { "MMCSD0_CFG", 2058, 1 },
35 { "USB3SS0_SLV0", 2176, 2 },
36 { "PCIE0_SLV", 2336, 8 },
37 { "PCIE1_SLV", 2337, 8 },
38 { "PCIE0_CFG", 2688, 1 },
39 { "PCIE1_CFG", 2689, 1 },
40}, mcu_cbass_fwls[] = {
41 { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
42 { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
43 { "MCU_FSS0_S1", 1033, 8 },
44 { "MCU_FSS0_S0", 1036, 8 },
45 { "MCU_CPSW0", 1220, 1 },
46};
47#endif
48#endif
49
Andreas Dannenberg1c855c12018-08-27 15:57:12 +053050static void ctrl_mmr_unlock(void)
51{
52 /* Unlock all WKUP_CTRL_MMR0 module registers */
53 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
54 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
55 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
56 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
57 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
58 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
59
60 /* Unlock all MCU_CTRL_MMR0 module registers */
61 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
62 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
63 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
64 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
65
66 /* Unlock all CTRL_MMR0 module registers */
67 mmr_unlock(CTRL_MMR0_BASE, 0);
68 mmr_unlock(CTRL_MMR0_BASE, 1);
69 mmr_unlock(CTRL_MMR0_BASE, 2);
70 mmr_unlock(CTRL_MMR0_BASE, 3);
71 mmr_unlock(CTRL_MMR0_BASE, 6);
72 mmr_unlock(CTRL_MMR0_BASE, 7);
73}
74
Andrew F. Davis9ffea342019-04-12 12:54:42 -040075/*
76 * This uninitialized global variable would normal end up in the .bss section,
77 * but the .bss is cleared between writing and reading this variable, so move
78 * it to the .data section.
79 */
Marek BehĂșn4bebdd32021-05-20 13:23:52 +020080u32 bootindex __section(".data");
Andrew F. Davis9ffea342019-04-12 12:54:42 -040081
Lokesh Vutlac7bfb852018-08-27 15:57:11 +053082static void store_boot_index_from_rom(void)
83{
Andrew F. Davis9ffea342019-04-12 12:54:42 -040084 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
Lokesh Vutlac7bfb852018-08-27 15:57:11 +053085}
86
Faiz Abbasb4372bf2020-08-03 11:35:08 +053087#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
Faiz Abbas68393212020-02-26 13:44:36 +053088void k3_mmc_stop_clock(void)
89{
90 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
91 struct mmc *mmc = find_mmc_device(0);
92
93 if (!mmc)
94 return;
95
96 mmc->saved_clock = mmc->clock;
97 mmc_set_clock(mmc, 0, true);
98 }
99}
100
101void k3_mmc_restart_clock(void)
102{
103 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
104 struct mmc *mmc = find_mmc_device(0);
105
106 if (!mmc)
107 return;
108
109 mmc_set_clock(mmc, mmc->saved_clock, false);
110 }
111}
Faiz Abbasb4372bf2020-08-03 11:35:08 +0530112#else
113void k3_mmc_stop_clock(void) {}
114void k3_mmc_restart_clock(void) {}
Faiz Abbas68393212020-02-26 13:44:36 +0530115#endif
Faiz Abbas3385a862020-08-03 11:35:09 +0530116#if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
117#define CTRLMMR_SERDES0_CTRL 0x00104080
118#define PCIE_LANE0 0x1
119static int fixup_usb_boot(void)
120{
121 int ret;
Faiz Abbas68393212020-02-26 13:44:36 +0530122
Faiz Abbas3385a862020-08-03 11:35:09 +0530123 switch (spl_boot_device()) {
124 case BOOT_DEVICE_USB:
125 /*
126 * If bootmode is Host bootmode, fixup the dr_mode to host
127 * before the dwc3 bind takes place
128 */
129 ret = fdt_find_and_setprop((void *)gd->fdt_blob,
130 "/interconnect@100000/dwc3@4000000/usb@10000",
131 "dr_mode", "host", 11, 0);
132 if (ret)
133 printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
134 ret);
135 fallthrough;
136 case BOOT_DEVICE_DFU:
137 /*
138 * The serdes mux between PCIe and USB3 needs to be set to PCIe for
139 * accessing the interface at USB 2.0
140 */
141 writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
142 default:
143 break;
144 }
145
146 return 0;
147}
148
149int fdtdec_board_setup(const void *fdt_blob)
150{
151 return fixup_usb_boot();
152}
153#endif
Lokesh Vutla32886442018-08-27 15:57:09 +0530154void board_init_f(ulong dummy)
155{
Andreas Dannenbergea91da12019-06-04 17:55:50 -0500156#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
Lokesh Vutla2c69d5c2018-11-02 19:51:06 +0530157 struct udevice *dev;
Faiz Abbasfe1217e2020-08-03 11:35:06 +0530158 size_t pool_size;
159 void *pool_addr;
Lokesh Vutla2c69d5c2018-11-02 19:51:06 +0530160 int ret;
161#endif
Lokesh Vutlac7bfb852018-08-27 15:57:11 +0530162 /*
163 * Cannot delay this further as there is a chance that
164 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
165 */
166 store_boot_index_from_rom();
167
Andreas Dannenberg1c855c12018-08-27 15:57:12 +0530168 /* Make all control module registers accessible */
169 ctrl_mmr_unlock();
170
Lokesh Vutlac1e60e82018-11-02 19:51:03 +0530171#ifdef CONFIG_CPU_V7R
Lokesh Vutla5fbd6fe2019-12-31 15:49:55 +0530172 disable_linefill_optimization();
Lokesh Vutlac1e60e82018-11-02 19:51:03 +0530173 setup_k3_mpu_regions();
174#endif
175
Lokesh Vutla32886442018-08-27 15:57:09 +0530176 /* Init DM early in-order to invoke system controller */
177 spl_early_init();
178
Andreas Dannenbergb45d2cd2018-12-04 22:29:47 -0600179#ifdef CONFIG_K3_EARLY_CONS
180 /*
181 * Allow establishing an early console as required for example when
182 * doing a UART-based boot. Note that this console may not "survive"
183 * through a SYSFW PM-init step and will need a re-init in some way
184 * due to changing module clock frequencies.
185 */
186 early_console_init();
187#endif
188
Andreas Dannenbergea91da12019-06-04 17:55:50 -0500189#ifdef CONFIG_K3_LOAD_SYSFW
190 /*
Faiz Abbasfe1217e2020-08-03 11:35:06 +0530191 * Initialize an early full malloc environment. Do so by allocating a
192 * new malloc area inside the currently active pre-relocation "first"
193 * malloc pool of which we use all that's left.
194 */
195 pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
196 pool_addr = malloc(pool_size);
197 if (!pool_addr)
198 panic("ERROR: Can't allocate full malloc pool!\n");
199
200 mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
201 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
202 debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx bytes\n",
203 __func__, (unsigned long)pool_addr, (unsigned long)pool_size);
204 /*
Andreas Dannenbergea91da12019-06-04 17:55:50 -0500205 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
206 * regardless of the result of pinctrl. Do this without probing the
207 * device, but instead by searching the device that would request the
208 * given sequence number if probed. The UART will be used by the system
209 * firmware (SYSFW) image for various purposes and SYSFW depends on us
210 * to initialize its pin settings.
211 */
Simon Glass07e13382020-12-16 21:20:29 -0700212 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
Andreas Dannenbergea91da12019-06-04 17:55:50 -0500213 if (!ret)
214 pinctrl_select_state(dev, "default");
215
216 /*
Lokesh Vutla5fafe442020-03-10 16:50:58 +0530217 * Load, start up, and configure system controller firmware while
218 * also populating the SYSFW post-PM configuration callback hook.
Andreas Dannenbergea91da12019-06-04 17:55:50 -0500219 */
Lokesh Vutla17951b72020-08-05 22:44:18 +0530220 k3_sysfw_loader(false, k3_mmc_stop_clock, k3_mmc_restart_clock);
Faiz Abbas68393212020-02-26 13:44:36 +0530221
222 /* Prepare console output */
223 preloader_console_init();
Andrew F. Davisf0bcb662020-01-10 14:35:21 -0500224
225 /* Disable ROM configured firewalls right after loading sysfw */
226#ifdef CONFIG_TI_SECURE_DEVICE
227 remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
228 remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
229#endif
Andreas Dannenbergea91da12019-06-04 17:55:50 -0500230#else
Lokesh Vutla32886442018-08-27 15:57:09 +0530231 /* Prepare console output */
232 preloader_console_init();
Andreas Dannenbergea91da12019-06-04 17:55:50 -0500233#endif
Lokesh Vutla2c69d5c2018-11-02 19:51:06 +0530234
Lokesh Vutla5fafe442020-03-10 16:50:58 +0530235 /* Output System Firmware version info */
236 k3_sysfw_print_ver();
237
Andreas Dannenberg63f5c852019-06-04 18:08:26 -0500238 /* Perform EEPROM-based board detection */
239 do_board_detect();
240
Keerthy2cd50972019-10-24 15:00:52 +0530241#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
Simon Glass65130cd2020-12-28 20:34:56 -0700242 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
Keerthy2cd50972019-10-24 15:00:52 +0530243 &dev);
244 if (ret)
245 printf("AVS init failed: %d\n", ret);
246#endif
247
Lokesh Vutla2c69d5c2018-11-02 19:51:06 +0530248#ifdef CONFIG_K3_AM654_DDRSS
249 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
Andreas Dannenberg7f6b62e2019-03-11 15:15:43 -0500250 if (ret)
251 panic("DRAM init failed: %d\n", ret);
Lokesh Vutla2c69d5c2018-11-02 19:51:06 +0530252#endif
Jan Kiszka7ce99f72020-05-18 07:57:22 +0200253 spl_enable_dcache();
Lokesh Vutla32886442018-08-27 15:57:09 +0530254}
255
Harald Seiler0bf7ab12020-04-15 11:33:30 +0200256u32 spl_mmc_boot_mode(const u32 boot_device)
Andrew F. Davisc5161462018-10-03 10:03:23 -0500257{
258#if defined(CONFIG_SUPPORT_EMMC_BOOT)
259 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
Andrew F. Davisc5161462018-10-03 10:03:23 -0500260
261 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
262 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
263
264 /* eMMC boot0 mode is only supported for primary boot */
265 if (bootindex == K3_PRIMARY_BOOTMODE &&
266 bootmode == BOOT_DEVICE_MMC1)
267 return MMCSD_MODE_EMMCBOOT;
268#endif
269
270 /* Everything else use filesystem if available */
Tien Fong Chee6091dd12019-01-23 14:20:05 +0800271#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
Andrew F. Davisc5161462018-10-03 10:03:23 -0500272 return MMCSD_MODE_FS;
273#else
274 return MMCSD_MODE_RAW;
275#endif
276}
277
Lokesh Vutlac7bfb852018-08-27 15:57:11 +0530278static u32 __get_backup_bootmedia(u32 devstat)
Lokesh Vutla32886442018-08-27 15:57:09 +0530279{
Lokesh Vutlac7bfb852018-08-27 15:57:11 +0530280 u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
281 CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
282
283 switch (bkup_boot) {
284 case BACKUP_BOOT_DEVICE_USB:
285 return BOOT_DEVICE_USB;
286 case BACKUP_BOOT_DEVICE_UART:
287 return BOOT_DEVICE_UART;
288 case BACKUP_BOOT_DEVICE_ETHERNET:
289 return BOOT_DEVICE_ETHERNET;
290 case BACKUP_BOOT_DEVICE_MMC2:
Andrew F. Davisf515cf02018-10-03 10:03:22 -0500291 {
292 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
293 CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
294 if (port == 0x0)
295 return BOOT_DEVICE_MMC1;
Lokesh Vutlac7bfb852018-08-27 15:57:11 +0530296 return BOOT_DEVICE_MMC2;
Andrew F. Davisf515cf02018-10-03 10:03:22 -0500297 }
Lokesh Vutlac7bfb852018-08-27 15:57:11 +0530298 case BACKUP_BOOT_DEVICE_SPI:
299 return BOOT_DEVICE_SPI;
300 case BACKUP_BOOT_DEVICE_HYPERFLASH:
301 return BOOT_DEVICE_HYPERFLASH;
302 case BACKUP_BOOT_DEVICE_I2C:
303 return BOOT_DEVICE_I2C;
304 };
305
Lokesh Vutla32886442018-08-27 15:57:09 +0530306 return BOOT_DEVICE_RAM;
307}
Lokesh Vutlac7bfb852018-08-27 15:57:11 +0530308
309static u32 __get_primary_bootmedia(u32 devstat)
310{
Andrew F. Davisf515cf02018-10-03 10:03:22 -0500311 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
312 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
Lokesh Vutlac7bfb852018-08-27 15:57:11 +0530313
314 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
315 bootmode = BOOT_DEVICE_SPI;
316
Andrew F. Davisf515cf02018-10-03 10:03:22 -0500317 if (bootmode == BOOT_DEVICE_MMC2) {
318 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
319 CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
320 if (port == 0x0)
321 bootmode = BOOT_DEVICE_MMC1;
322 } else if (bootmode == BOOT_DEVICE_MMC1) {
323 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
324 CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
325 if (port == 0x1)
326 bootmode = BOOT_DEVICE_MMC2;
Faiz Abbas0ae20ed2020-08-03 11:35:10 +0530327 } else if (bootmode == BOOT_DEVICE_DFU) {
328 u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
329 CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
330 if (mode == 0x2)
331 bootmode = BOOT_DEVICE_USB;
Andrew F. Davisf515cf02018-10-03 10:03:22 -0500332 }
333
Lokesh Vutlac7bfb852018-08-27 15:57:11 +0530334 return bootmode;
335}
336
337u32 spl_boot_device(void)
338{
339 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
Lokesh Vutlac7bfb852018-08-27 15:57:11 +0530340
341 if (bootindex == K3_PRIMARY_BOOTMODE)
342 return __get_primary_bootmedia(devstat);
343 else
344 return __get_backup_bootmedia(devstat);
345}
Lokesh Vutla32886442018-08-27 15:57:09 +0530346#endif
347
Andreas Dannenberg31175f82019-06-07 19:24:42 +0530348#ifdef CONFIG_SYS_K3_SPL_ATF
349
350#define AM6_DEV_MCU_RTI0 134
351#define AM6_DEV_MCU_RTI1 135
352#define AM6_DEV_MCU_ARMSS0_CPU0 159
353#define AM6_DEV_MCU_ARMSS0_CPU1 245
354
355void release_resources_for_core_shutdown(void)
356{
Lokesh Vutlaac9ca952019-09-09 12:47:38 +0530357 struct ti_sci_handle *ti_sci = get_ti_sci_handle();
358 struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
359 struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
Andreas Dannenberg31175f82019-06-07 19:24:42 +0530360 int ret;
361 u32 i;
362
363 const u32 put_device_ids[] = {
364 AM6_DEV_MCU_RTI0,
365 AM6_DEV_MCU_RTI1,
366 };
367
Andreas Dannenberg31175f82019-06-07 19:24:42 +0530368 /* Iterate through list of devices to put (shutdown) */
369 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
370 u32 id = put_device_ids[i];
371
372 ret = dev_ops->put_device(ti_sci, id);
373 if (ret)
374 panic("Failed to put device %u (%d)\n", id, ret);
375 }
376
377 const u32 put_core_ids[] = {
378 AM6_DEV_MCU_ARMSS0_CPU1,
379 AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
380 };
381
382 /* Iterate through list of cores to put (shutdown) */
383 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
384 u32 id = put_core_ids[i];
385
386 /*
387 * Queue up the core shutdown request. Note that this call
388 * needs to be followed up by an actual invocation of an WFE
389 * or WFI CPU instruction.
390 */
391 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
392 if (ret)
393 panic("Failed sending core %u shutdown message (%d)\n",
394 id, ret);
395 }
396}
397#endif