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Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +09001/*
2 * Configuation settings for the Renesas Solutions AP-325RXA board
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +09008 */
9
10#ifndef __AP325RXA_H
11#define __AP325RXA_H
12
13#undef DEBUG
14#define CONFIG_SH 1
15#define CONFIG_SH4 1
16#define CONFIG_CPU_SH7723 1
17#define CONFIG_AP325RXA 1
18
19#define CONFIG_CMD_LOADB
20#define CONFIG_CMD_LOADS
21#define CONFIG_CMD_FLASH
22#define CONFIG_CMD_MEMORY
23#define CONFIG_CMD_NET
24#define CONFIG_CMD_PING
25#define CONFIG_CMD_NFS
26#define CONFIG_CMD_SDRAM
Mike Frysinger78dcaf42009-01-28 19:08:14 -050027#define CONFIG_CMD_SAVEENV
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090028#define CONFIG_CMD_IDE
29#define CONFIG_CMD_EXT2
30#define CONFIG_DOS_PARTITION
31
32#define CONFIG_BAUDRATE 38400
33#define CONFIG_BOOTDELAY 3
34#define CONFIG_BOOTARGS "console=ttySC2,38400"
35
36#define CONFIG_VERSION_VARIABLE
37#undef CONFIG_SHOW_BOOT_PROGRESS
38
39/* SMC9118 */
Ben Warrenfbfdd3a2009-07-20 22:01:11 -070040#define CONFIG_SMC911X 1
41#define CONFIG_SMC911X_32_BIT 1
42#define CONFIG_SMC911X_BASE 0xB6080000
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090043
44/* MEMORY */
45#define AP325RXA_SDRAM_BASE (0x88000000)
46#define AP325RXA_FLASH_BASE_1 (0xA0000000)
47#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
48
Nobuhiro Iwamatsuf9386d52011-01-17 20:46:35 +090049#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
50
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090051/* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020052#define CONFIG_SYS_LONGHELP
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090053/* Monitor Command Prompt */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054#define CONFIG_SYS_PROMPT "=> "
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090055/* Buffer size for input from the Console */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#define CONFIG_SYS_CBSIZE 256
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090057/* Buffer size for Console output */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090059/* max args accepted for monitor commands */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_MAXARGS 16
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090061/* Buffer size for Boot Arguments passed to kernel */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062#define CONFIG_SYS_BARGSIZE 512
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090063/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090065
66/* SCIF */
67#define CONFIG_SCIF_CONSOLE 1
68#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
69#define CONFIG_CONS_SCIF5 1
70
71/* Suppress display of console information at boot */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#undef CONFIG_SYS_CONSOLE_INFO_QUIET
73#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
74#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090075
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
77#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090078
79/* Enable alternate, more extensive, memory test */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080#undef CONFIG_SYS_ALT_MEMTEST
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090081/* Scratch address used by the alternate memory test */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#undef CONFIG_SYS_MEMTEST_SCRATCH
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090083
84/* Enable temporary baudrate change while serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#undef CONFIG_SYS_LOADS_BAUD_CHANGE
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090086
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090088/* maybe more, but if so u-boot doesn't know about it... */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090090/* default load address for scripts ?!? */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090092
93/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090095/* Monitor size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090097/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900100
101/* FLASH */
102#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200103#define CONFIG_SYS_FLASH_CFI
104#undef CONFIG_SYS_FLASH_QUIET_TEST
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900105/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_FLASH_EMPTY_INFO
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900107/* Physical start address of Flash memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900109/* Max number of sectors on each Flash chip */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#define CONFIG_SYS_MAX_FLASH_SECT 512
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900111
112/*
113 * IDE support
114 */
115#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_PIO_MODE 1
117#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
118#define CONFIG_SYS_IDE_MAXDEVICE 1
119#define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
120#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
121#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
122#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
123#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
Albert Aribaud036c6b42010-08-08 05:17:05 +0530124#define CONFIG_IDE_SWAP_IO
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900125
126/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_MAX_FLASH_BANKS 1
128#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900129
130/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900132/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900134/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900136/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900138
139/*
140 * Use hardware flash sectors protection instead
141 * of U-Boot software protection
142 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#undef CONFIG_SYS_FLASH_PROTECTION
144#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900145
146/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200147#define CONFIG_ENV_IS_IN_FLASH
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900148#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200149#define CONFIG_ENV_SECT_SIZE (128 * 1024)
150#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
152/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
153#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200154#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900155
156/* Board Clock */
157#define CONFIG_SYS_CLK_FREQ 33333333
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +0200158#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Jean-Christophe PLAGNIOL-VILLARD51704102009-06-04 12:06:47 +0200159#define CONFIG_SYS_HZ 1000
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900160
161#endif /* __AP325RXA_H */