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wdenkf1d0ff42005-04-13 23:15:10 +00001/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf1d0ff42005-04-13 23:15:10 +00006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*
12 * High Level Configuration Options
13 * (easy to change)
14 */
15
Masahiro Yamada608ed2c2014-01-16 11:03:07 +090016#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
Wolfgang Denka1be4762008-05-20 16:00:29 +020017#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
wdenkf1d0ff42005-04-13 23:15:10 +000018
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020019/*
20 * allowed and functional CONFIG_SYS_TEXT_BASE values:
21 * 0xfe000000 low boot at 0x00000100 (default board setting)
22 * 0x00100000 RAM load and test
23 */
24#define CONFIG_SYS_TEXT_BASE 0xFE000000
25
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020026#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenkf1d0ff42005-04-13 23:15:10 +000027
wdenkf1d0ff42005-04-13 23:15:10 +000028#define CONFIG_BOARD_EARLY_INIT_R
29
Becky Bruce03ea1be2008-05-08 19:02:12 -050030#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31
wdenkf1d0ff42005-04-13 23:15:10 +000032/*
33 * Serial console configuration
34 */
35#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
36#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020037#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkf1d0ff42005-04-13 23:15:10 +000038
39/*
Jon Loeligere54e77a2007-07-10 09:29:01 -050040 * BOOTP options
41 */
42#define CONFIG_BOOTP_BOOTFILESIZE
43#define CONFIG_BOOTP_BOOTPATH
44#define CONFIG_BOOTP_GATEWAY
45#define CONFIG_BOOTP_HOSTNAME
46
Jon Loeligere54e77a2007-07-10 09:29:01 -050047/*
Jon Loeliger37ec35e2007-07-04 22:31:56 -050048 * Command line configuration.
wdenkf1d0ff42005-04-13 23:15:10 +000049 */
Jon Loeliger37ec35e2007-07-04 22:31:56 -050050#define CONFIG_CMD_DATE
Jon Loeliger37ec35e2007-07-04 22:31:56 -050051#define CONFIG_CMD_IMMAP
Jon Loeliger37ec35e2007-07-04 22:31:56 -050052#define CONFIG_CMD_REGINFO
wdenkf1d0ff42005-04-13 23:15:10 +000053
54/*
55 * MUST be low boot - HIGHBOOT is not supported anymore
56 */
Wolfgang Denk0708bc62010-10-07 21:51:12 +020057#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058# define CONFIG_SYS_LOWBOOT 1
59# define CONFIG_SYS_LOWBOOT16 1
wdenkf1d0ff42005-04-13 23:15:10 +000060#else
Wolfgang Denk0708bc62010-10-07 21:51:12 +020061# error "CONFIG_SYS_TEXT_BASE must be 0xFE000000"
wdenkf1d0ff42005-04-13 23:15:10 +000062#endif
63
64/*
65 * Autobooting
66 */
wdenkf1d0ff42005-04-13 23:15:10 +000067
68#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +010069 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkf1d0ff42005-04-13 23:15:10 +000070 "echo"
71
72#undef CONFIG_BOOTARGS
73
74#define CONFIG_EXTRA_ENV_SETTINGS \
75 "netdev=eth0\0" \
76 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010077 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf1d0ff42005-04-13 23:15:10 +000078 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010079 "addip=setenv bootargs ${bootargs} " \
80 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
81 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf1d0ff42005-04-13 23:15:10 +000082 "flash_nfs=run nfsargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010083 "bootm ${kernel_addr}\0" \
wdenkf1d0ff42005-04-13 23:15:10 +000084 "flash_self=run ramargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010085 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
86 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf1d0ff42005-04-13 23:15:10 +000087 "rootpath=/opt/eldk/ppc_6xx\0" \
88 "bootfile=/tftpboot/canmb/uImage\0" \
89 ""
90
91#define CONFIG_BOOTCOMMAND "run flash_self"
92
93/*
94 * IPB Bus clocking configuration.
95 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkf1d0ff42005-04-13 23:15:10 +000097
98/*
99 * Flash configuration, expect one 16 Megabyte Bank at most
100 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_FLASH_BASE 0xFE000000
102#define CONFIG_SYS_FLASH_SIZE 0x02000000
103#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
104#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
wdenkf1d0ff42005-04-13 23:15:10 +0000105
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
107#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenkf1d0ff42005-04-13 23:15:10 +0000108
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200109#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#define CONFIG_SYS_FLASH_CFI
111#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenkf1d0ff42005-04-13 23:15:10 +0000112
113/*
wdenkf1d0ff42005-04-13 23:15:10 +0000114 * Environment settings
115 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200116#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200117#define CONFIG_ENV_OFFSET (2*128*1024)
118#define CONFIG_ENV_SIZE 0x2000
119#define CONFIG_ENV_SECT_SIZE (128*1024)
wdenkf1d0ff42005-04-13 23:15:10 +0000120
121/*
122 * Memory map
123 *
124 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
125 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
127#define CONFIG_SYS_SDRAM_BASE 0x00000000
128#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenkf1d0ff42005-04-13 23:15:10 +0000129
130/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200132#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
wdenkf1d0ff42005-04-13 23:15:10 +0000133
Wolfgang Denk0191e472010-10-26 14:34:52 +0200134#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf1d0ff42005-04-13 23:15:10 +0000136
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200137#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
139# define CONFIG_SYS_RAMBOOT 1
wdenkf1d0ff42005-04-13 23:15:10 +0000140#endif
141
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
143#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
144#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf1d0ff42005-04-13 23:15:10 +0000145
146/*
147 * Ethernet configuration
148 */
149#define CONFIG_MPC5xxx_FEC 1
Ben Warrenbc1b9172009-02-05 23:58:25 -0800150#define CONFIG_MPC5xxx_FEC_MII100
wdenkfaaa6022005-04-21 21:10:22 +0000151#define CONFIG_PHY_ADDR 0x0
wdenkf1d0ff42005-04-13 23:15:10 +0000152/*
153 * GPIO configuration:
154 * PSC1,2,3 predefined as UART
155 * PCI disabled
156 * Ethernet 100 with MD
157 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058444
wdenkf1d0ff42005-04-13 23:15:10 +0000159
160/*
161 * Miscellaneous configurable options
162 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500164#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf1d0ff42005-04-13 23:15:10 +0000166#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf1d0ff42005-04-13 23:15:10 +0000168#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200169#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
170#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
171#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf1d0ff42005-04-13 23:15:10 +0000172
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
174#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
wdenkf1d0ff42005-04-13 23:15:10 +0000175
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
wdenkf1d0ff42005-04-13 23:15:10 +0000177
wdenkf1d0ff42005-04-13 23:15:10 +0000178#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
179
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500181#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500183#endif
184
wdenkf1d0ff42005-04-13 23:15:10 +0000185/*
186 * Various low-level settings
187 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
189#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenkf1d0ff42005-04-13 23:15:10 +0000190
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
192#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
193#define CONFIG_SYS_BOOTCS_CFG 0x00047D01
194#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
195#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
wdenkf1d0ff42005-04-13 23:15:10 +0000196
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#define CONFIG_SYS_CS_BURST 0x00000000
198#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenkf1d0ff42005-04-13 23:15:10 +0000199
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
wdenkf1d0ff42005-04-13 23:15:10 +0000201
202#endif /* __CONFIG_H */