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wdenk12490652004-04-18 21:13:41 +00001/*
Michal Simek403d6192008-07-11 10:10:31 +02002 * (C) Copyright 2008 Michal Simek <monstr@monstr.eu>
3 * Clean driver and add xilinx constant from header file
wdenk12490652004-04-18 21:13:41 +00004 *
Michal Simek403d6192008-07-11 10:10:31 +02005 * (C) Copyright 2004 Atmark Techno, Inc.
wdenk12490652004-04-18 21:13:41 +00006 * Yasushi SHOJI <yashi@atmark-techno.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Michal Simek403d6192008-07-11 10:10:31 +020018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk12490652004-04-18 21:13:41 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <config.h>
Michal Simek403d6192008-07-11 10:10:31 +020028#include <asm/io.h>
wdenke44b9112004-04-18 23:32:11 +000029
Michal Simek403d6192008-07-11 10:10:31 +020030#define RX_FIFO_OFFSET 0 /* receive FIFO, read only */
31#define TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
32#define STATUS_REG_OFFSET 8 /* status register, read only */
wdenk12490652004-04-18 21:13:41 +000033
Michal Simek403d6192008-07-11 10:10:31 +020034#define SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
35#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
36#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
wdenk12490652004-04-18 21:13:41 +000037
Michal Simek403d6192008-07-11 10:10:31 +020038#define UARTLITE_STATUS (CONFIG_SERIAL_BASE + STATUS_REG_OFFSET)
39#define UARTLITE_TX_FIFO (CONFIG_SERIAL_BASE + TX_FIFO_OFFSET)
40#define UARTLITE_RX_FIFO (CONFIG_SERIAL_BASE + RX_FIFO_OFFSET)
wdenk12490652004-04-18 21:13:41 +000041
42int serial_init(void)
43{
44 /* FIXME: Nothing for now. We should initialize fifo, etc */
45 return 0;
46}
47
48void serial_setbrg(void)
49{
50 /* FIXME: what's this for? */
51}
52
53void serial_putc(const char c)
54{
Michal Simek403d6192008-07-11 10:10:31 +020055 if (c == '\n')
56 serial_putc('\r');
Stefan Roese37628252008-08-06 14:05:38 +020057 while (in_be32((u32 *) UARTLITE_STATUS) & SR_TX_FIFO_FULL);
58 out_be32((u32 *) UARTLITE_TX_FIFO, (unsigned char) (c & 0xff));
wdenk12490652004-04-18 21:13:41 +000059}
60
61void serial_puts(const char * s)
62{
63 while (*s) {
64 serial_putc(*s++);
65 }
66}
67
68int serial_getc(void)
69{
Stefan Roese37628252008-08-06 14:05:38 +020070 while (!(in_be32((u32 *) UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA));
71 return in_be32((u32 *) UARTLITE_RX_FIFO) & 0xff;
wdenk12490652004-04-18 21:13:41 +000072}
73
74int serial_tstc(void)
75{
Stefan Roese37628252008-08-06 14:05:38 +020076 return (in_be32((u32 *) UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA);
wdenk12490652004-04-18 21:13:41 +000077}