blob: 007f5ce7757fbd275ffaddf010c3b8d202614724 [file] [log] [blame]
Mike Frysinger94bae5c2008-03-30 15:46:13 -04001/*
2 * initcode.c - Initialize the processor. This is usually entails things
3 * like external memory, voltage regulators, etc... Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
6 *
7 * Copyright (c) 2004-2008 Analog Devices Inc.
8 *
9 * Licensed under the GPL-2 or later.
10 */
11
Mike Frysinger3343bfa2009-11-09 19:44:04 -050012#define BFIN_IN_INITCODE
13
Mike Frysinger94bae5c2008-03-30 15:46:13 -040014#include <config.h>
15#include <asm/blackfin.h>
16#include <asm/mach-common/bits/bootrom.h>
Mike Frysinger268dbf52008-10-11 21:58:33 -040017#include <asm/mach-common/bits/core.h>
Mike Frysinger94bae5c2008-03-30 15:46:13 -040018#include <asm/mach-common/bits/ebiu.h>
19#include <asm/mach-common/bits/pll.h>
20#include <asm/mach-common/bits/uart.h>
21
Mike Frysinger94bae5c2008-03-30 15:46:13 -040022#include "serial.h"
23
24__attribute__((always_inline))
Mike Frysinger84451302008-12-10 12:33:54 -050025static inline void serial_init(void)
Mike Frysinger94bae5c2008-03-30 15:46:13 -040026{
27#ifdef __ADSPBF54x__
28# ifdef BFIN_BOOT_UART_USE_RTS
29# define BFIN_UART_USE_RTS 1
30# else
31# define BFIN_UART_USE_RTS 0
32# endif
33 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
34 size_t i;
35
36 /* force RTS rather than relying on auto RTS */
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050037 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
Mike Frysinger94bae5c2008-03-30 15:46:13 -040038
39 /* Wait for the line to clear up. We cannot rely on UART
40 * registers as none of them reflect the status of the RSR.
41 * Instead, we'll sleep for ~10 bit times at 9600 baud.
42 * We can precalc things here by assuming boot values for
43 * PLL rather than loading registers and calculating.
44 * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
45 * EDB0 = 0
46 * Divisor = (SCLK / baud) / 16
47 * SCLK = baud * 16 * Divisor
48 * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
49 * CCLK = (16 * Divisor * 5) * (9600 / 10)
50 * In reality, this will probably be just about 1 second delay,
51 * so assuming 9600 baud is OK (both as a very low and too high
52 * speed as this will buffer things enough).
53 */
54#define _NUMBITS (10) /* how many bits to delay */
55#define _LOWBAUD (9600) /* low baud rate */
56#define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
57#define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
58#define _NUMINS (3) /* how many instructions in loop */
59#define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
60 i = _CCLK;
61 while (i--)
62 asm volatile("" : : : "memory");
63 }
64#endif
65
Mike Frysinger94bae5c2008-03-30 15:46:13 -040066 if (BFIN_DEBUG_EARLY_SERIAL) {
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050067 int ucen = bfin_read16(&pUART->gctl) & UCEN;
Mike Frysinger94bae5c2008-03-30 15:46:13 -040068 serial_early_init();
69
70 /* If the UART is off, that means we need to program
71 * the baud rate ourselves initially.
72 */
Mike Frysinger84451302008-12-10 12:33:54 -050073 if (ucen != UCEN)
Mike Frysinger94bae5c2008-03-30 15:46:13 -040074 serial_early_set_baud(CONFIG_BAUDRATE);
Mike Frysinger94bae5c2008-03-30 15:46:13 -040075 }
Mike Frysinger94bae5c2008-03-30 15:46:13 -040076}
77
78__attribute__((always_inline))
79static inline void serial_deinit(void)
80{
81#ifdef __ADSPBF54x__
82 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
83 /* clear forced RTS rather than relying on auto RTS */
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050084 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
Mike Frysinger94bae5c2008-03-30 15:46:13 -040085 }
86#endif
Mike Frysinger94bae5c2008-03-30 15:46:13 -040087}
88
89__attribute__((always_inline))
90static inline void serial_putc(char c)
91{
92 if (!BFIN_DEBUG_EARLY_SERIAL)
93 return;
94
95 if (c == '\n')
Mike Frysingere7851d02009-04-24 23:22:48 -040096 serial_putc('\r');
Mike Frysinger94bae5c2008-03-30 15:46:13 -040097
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050098 bfin_write16(&pUART->thr, c);
Mike Frysinger94bae5c2008-03-30 15:46:13 -040099
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -0500100 while (!(bfin_read16(&pUART->lsr) & TEMT))
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400101 continue;
102}
103
Mike Frysingereb2a3992010-05-05 02:07:44 -0400104__attribute__((always_inline)) static inline void
105program_nmi_handler(void)
106{
107 u32 tmp1, tmp2;
108
109 /* Older bootroms don't create a dummy NMI handler,
110 * so make one ourselves ASAP in case it fires.
111 */
112 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
113 return;
114
115 asm volatile (
116 "%0 = RETS;" /* Save current RETS */
117 "CALL 1f;" /* Figure out current PC */
118 "RTN;" /* The simple NMI handler */
119 "1:"
120 "%1 = RETS;" /* Load addr of NMI handler */
121 "RETS = %0;" /* Restore RETS */
122 "[%2] = %1;" /* Write NMI handler */
123 : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2)
124 );
125}
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400126
Mike Frysinger2c001972008-12-09 17:21:08 -0500127/* Max SCLK can be 133MHz ... dividing that by (2*4) gives
128 * us a freq of 16MHz for SPI which should generally be
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400129 * slow enough for the slow reads the bootrom uses.
130 */
Mike Frysinger2c001972008-12-09 17:21:08 -0500131#if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
132 ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
133 (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
134# define BOOTROM_SUPPORTS_SPI_FAST_READ 1
135#else
136# define BOOTROM_SUPPORTS_SPI_FAST_READ 0
137#endif
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400138#ifndef CONFIG_SPI_BAUD_INITBLOCK
Mike Frysinger2c001972008-12-09 17:21:08 -0500139# define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
140#endif
141#ifdef SPI0_BAUD
142# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400143#endif
144
145/* PLL_DIV defines */
146#ifndef CONFIG_PLL_DIV_VAL
147# if (CONFIG_CCLK_DIV == 1)
148# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
149# elif (CONFIG_CCLK_DIV == 2)
150# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
151# elif (CONFIG_CCLK_DIV == 4)
152# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
153# elif (CONFIG_CCLK_DIV == 8)
154# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
155# else
156# define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
157# endif
158# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
159#endif
160
161#ifndef CONFIG_PLL_LOCKCNT_VAL
162# define CONFIG_PLL_LOCKCNT_VAL 0x0300
163#endif
164
165#ifndef CONFIG_PLL_CTL_VAL
Mike Frysingerc13fc442008-06-01 01:26:29 -0400166# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400167#endif
168
169#ifndef CONFIG_EBIU_RSTCTL_VAL
170# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
171#endif
Mike Frysinger4f7fb332008-10-11 21:46:52 -0400172#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
173# error invalid EBIU_RSTCTL value: must not set reserved bits
174#endif
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400175
176#ifndef CONFIG_EBIU_MBSCTL_VAL
177# define CONFIG_EBIU_MBSCTL_VAL 0
178#endif
179
Mike Frysinger4f7fb332008-10-11 21:46:52 -0400180#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
181# error invalid EBIU_DDRQUE value: must not set reserved bits
182#endif
183
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400184/* Make sure our voltage value is sane so we don't blow up! */
185#ifndef CONFIG_VR_CTL_VAL
186# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
187# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
188# define CCLK_VLEV_120 400000000
189# define CCLK_VLEV_125 533000000
190# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
191# define CCLK_VLEV_120 401000000
192# define CCLK_VLEV_125 401000000
193# elif defined(__ADSPBF561__)
194# define CCLK_VLEV_120 300000000
195# define CCLK_VLEV_125 501000000
196# endif
197# if BFIN_CCLK < CCLK_VLEV_120
198# define CONFIG_VR_CTL_VLEV VLEV_120
199# elif BFIN_CCLK < CCLK_VLEV_125
200# define CONFIG_VR_CTL_VLEV VLEV_125
201# else
202# define CONFIG_VR_CTL_VLEV VLEV_130
203# endif
204# if defined(__ADSPBF52x__) /* TBD; use default */
205# undef CONFIG_VR_CTL_VLEV
206# define CONFIG_VR_CTL_VLEV VLEV_110
207# elif defined(__ADSPBF54x__) /* TBD; use default */
208# undef CONFIG_VR_CTL_VLEV
209# define CONFIG_VR_CTL_VLEV VLEV_120
Mike Frysingera7ab10a2008-10-11 21:54:00 -0400210# elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
211# undef CONFIG_VR_CTL_VLEV
212# define CONFIG_VR_CTL_VLEV VLEV_125
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400213# endif
214
215# ifdef CONFIG_BFIN_MAC
216# define CONFIG_VR_CTL_CLKBUF CLKBUFOE
217# else
218# define CONFIG_VR_CTL_CLKBUF 0
219# endif
220
221# if defined(__ADSPBF52x__)
222# define CONFIG_VR_CTL_FREQ FREQ_1000
223# else
224# define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
225# endif
226
227# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
228#endif
229
Mike Frysinger446d5702008-10-11 21:56:08 -0400230/* some parts do not have an on-chip voltage regulator */
231#if defined(__ADSPBF51x__)
232# define CONFIG_HAS_VR 0
233# undef CONFIG_VR_CTL_VAL
234# define CONFIG_VR_CTL_VAL 0
235#else
236# define CONFIG_HAS_VR 1
237#endif
238
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500239#if CONFIG_MEM_SIZE
Mike Frysingerb0f14682008-06-01 01:28:24 -0400240#ifndef EBIU_RSTCTL
241/* Blackfin with SDRAM */
242#ifndef CONFIG_EBIU_SDBCTL_VAL
243# if CONFIG_MEM_SIZE == 16
244# define CONFIG_EBSZ_VAL EBSZ_16
245# elif CONFIG_MEM_SIZE == 32
246# define CONFIG_EBSZ_VAL EBSZ_32
247# elif CONFIG_MEM_SIZE == 64
248# define CONFIG_EBSZ_VAL EBSZ_64
249# elif CONFIG_MEM_SIZE == 128
250# define CONFIG_EBSZ_VAL EBSZ_128
251# elif CONFIG_MEM_SIZE == 256
252# define CONFIG_EBSZ_VAL EBSZ_256
253# elif CONFIG_MEM_SIZE == 512
254# define CONFIG_EBSZ_VAL EBSZ_512
255# else
256# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
257# endif
258# if CONFIG_MEM_ADD_WDTH == 8
259# define CONFIG_EBCAW_VAL EBCAW_8
260# elif CONFIG_MEM_ADD_WDTH == 9
261# define CONFIG_EBCAW_VAL EBCAW_9
262# elif CONFIG_MEM_ADD_WDTH == 10
263# define CONFIG_EBCAW_VAL EBCAW_10
264# elif CONFIG_MEM_ADD_WDTH == 11
265# define CONFIG_EBCAW_VAL EBCAW_11
266# else
267# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
268# endif
269# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
270#endif
271#endif
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500272#endif
Mike Frysingerb0f14682008-06-01 01:28:24 -0400273
Mike Frysinger8c10be42009-04-04 08:40:13 -0400274/* Conflicting Column Address Widths Causes SDRAM Errors:
275 * EB2CAW and EB3CAW must be the same
276 */
277#if ANOMALY_05000362
278# if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
279# error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
280# endif
281#endif
282
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500283__attribute__((always_inline)) static inline void
284program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400285{
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500286 serial_putc('a');
Mike Frysinger01986762009-02-13 17:10:58 -0500287
Mike Frysinger84451302008-12-10 12:33:54 -0500288 /* Save the clock pieces that are used in baud rate calculation */
Mike Frysinger84451302008-12-10 12:33:54 -0500289 if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500290 serial_putc('b');
291 *sdivB = bfin_read_PLL_DIV() & 0xf;
292 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
293 *divB = serial_early_get_div();
294 serial_putc('c');
Mike Frysinger84451302008-12-10 12:33:54 -0500295 }
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400296
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500297 serial_putc('d');
Mike Frysinger01986762009-02-13 17:10:58 -0500298
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400299#ifdef CONFIG_HW_WATCHDOG
300# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
301# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
302# endif
303 /* Program the watchdog with an initial timeout of ~20 seconds.
304 * Hopefully that should be long enough to load the u-boot LDR
305 * (from wherever) and then the common u-boot code can take over.
306 * In bypass mode, the start.S would have already set a much lower
307 * timeout, so don't clobber that.
308 */
309 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500310 serial_putc('e');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400311 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
312 bfin_write_WDOG_CTL(0);
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500313 serial_putc('f');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400314 }
315#endif
316
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500317 serial_putc('g');
318
319 /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
320 * fast read, so we need to slow down the SPI clock a lot more during
321 * boot. Once we switch over to u-boot's SPI flash driver, we'll
322 * increase the speed appropriately.
323 */
324 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
325 serial_putc('h');
326 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
327 bs->dFlags |= BFLAG_FASTREAD;
328 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
329 serial_putc('i');
330 }
331
332 serial_putc('j');
333}
334
335__attribute__((always_inline)) static inline bool
336maybe_self_refresh(ADI_BOOT_DATA *bs)
337{
338 serial_putc('a');
339
340 if (!CONFIG_MEM_SIZE)
341 return false;
Mike Frysinger268dbf52008-10-11 21:58:33 -0400342
343 /* If external memory is enabled, put it into self refresh first. */
Mike Frysinger268dbf52008-10-11 21:58:33 -0400344#ifdef EBIU_RSTCTL
345 if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500346 serial_putc('b');
Mike Frysinger268dbf52008-10-11 21:58:33 -0400347 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500348 return true;
Mike Frysinger268dbf52008-10-11 21:58:33 -0400349 }
350#else
351 if (bfin_read_EBIU_SDBCTL() & EBE) {
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500352 serial_putc('b');
Mike Frysinger268dbf52008-10-11 21:58:33 -0400353 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500354 return true;
Mike Frysinger268dbf52008-10-11 21:58:33 -0400355 }
356#endif
357
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500358 serial_putc('c');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400359
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500360 return false;
361}
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400362
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500363__attribute__((always_inline)) static inline u16
364program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
365{
366 u16 vr_ctl;
367
368 serial_putc('a');
369
370 vr_ctl = bfin_read_VR_CTL();
371
372 serial_putc('b');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400373
Mike Frysinger268dbf52008-10-11 21:58:33 -0400374 /* If we're entering self refresh, make sure it has happened. */
375 if (put_into_srfs)
376#ifdef EBIU_RSTCTL
377 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400378#else
Mike Frysinger268dbf52008-10-11 21:58:33 -0400379 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400380#endif
Mike Frysinger268dbf52008-10-11 21:58:33 -0400381 continue;
382
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500383 serial_putc('c');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400384
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400385 /* With newer bootroms, we use the helper function to set up
386 * the memory controller. Older bootroms lacks such helpers
387 * so we do it ourselves.
388 */
Mike Frysinger268dbf52008-10-11 21:58:33 -0400389 if (!ANOMALY_05000386) {
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500390 serial_putc('d');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400391
Mike Frysingere8aea4a2009-04-04 08:29:55 -0400392 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400393 ADI_SYSCTRL_VALUES memory_settings;
Mike Frysinger446d5702008-10-11 21:56:08 -0400394 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;
395 if (CONFIG_HAS_VR) {
396 actions |= SYSCTRL_VRCTL;
397 if (CONFIG_VR_CTL_VAL & FREQ_MASK)
398 actions |= SYSCTRL_INTVOLTAGE;
399 else
400 actions |= SYSCTRL_EXTVOLTAGE;
401 memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
402 } else
403 actions |= SYSCTRL_EXTVOLTAGE;
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400404 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
405 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
406 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
Mike Frysingerf9d004b2008-12-06 18:06:58 -0500407#if ANOMALY_05000432
408 bfin_write_SIC_IWR1(0);
409#endif
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500410 serial_putc('e');
Mike Frysinger446d5702008-10-11 21:56:08 -0400411 bfrom_SysControl(actions, &memory_settings, NULL);
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500412 serial_putc('f');
Mike Frysingerf9d004b2008-12-06 18:06:58 -0500413#if ANOMALY_05000432
414 bfin_write_SIC_IWR1(-1);
415#endif
Mike Frysinger1f1ac0a2009-04-04 08:09:24 -0400416#if ANOMALY_05000171
417 bfin_write_SICA_IWR0(-1);
418 bfin_write_SICA_IWR1(-1);
419#endif
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500420 serial_putc('g');
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400421 } else {
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500422 serial_putc('h');
Mike Frysinger268dbf52008-10-11 21:58:33 -0400423
424 /* Disable all peripheral wakeups except for the PLL event. */
425#ifdef SIC_IWR0
426 bfin_write_SIC_IWR0(1);
427 bfin_write_SIC_IWR1(0);
428# ifdef SIC_IWR2
429 bfin_write_SIC_IWR2(0);
430# endif
431#elif defined(SICA_IWR0)
432 bfin_write_SICA_IWR0(1);
433 bfin_write_SICA_IWR1(0);
434#else
435 bfin_write_SIC_IWR(1);
436#endif
437
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500438 serial_putc('i');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400439
Mike Frysingere8aea4a2009-04-04 08:29:55 -0400440 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400441 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400442
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500443 serial_putc('j');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400444
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400445 /* Only reprogram when needed to avoid triggering unnecessary
446 * PLL relock sequences.
447 */
Mike Frysinger268dbf52008-10-11 21:58:33 -0400448 if (vr_ctl != CONFIG_VR_CTL_VAL) {
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500449 serial_putc('?');
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400450 bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
451 asm("idle;");
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500452 serial_putc('!');
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400453 }
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400454
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500455 serial_putc('k');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400456
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400457 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400458
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500459 serial_putc('l');
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400460
461 /* Only reprogram when needed to avoid triggering unnecessary
462 * PLL relock sequences.
463 */
Mike Frysinger43ed6962009-04-04 08:10:22 -0400464 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500465 serial_putc('?');
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400466 bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
467 asm("idle;");
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500468 serial_putc('!');
Mike Frysinger1114d0e2008-06-01 01:29:57 -0400469 }
Mike Frysinger268dbf52008-10-11 21:58:33 -0400470
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500471 serial_putc('m');
Mike Frysinger268dbf52008-10-11 21:58:33 -0400472
473 /* Restore all peripheral wakeups. */
474#ifdef SIC_IWR0
475 bfin_write_SIC_IWR0(-1);
476 bfin_write_SIC_IWR1(-1);
477# ifdef SIC_IWR2
478 bfin_write_SIC_IWR2(-1);
479# endif
480#elif defined(SICA_IWR0)
481 bfin_write_SICA_IWR0(-1);
482 bfin_write_SICA_IWR1(-1);
483#else
484 bfin_write_SIC_IWR(-1);
485#endif
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500486
487 serial_putc('n');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400488 }
489
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500490 serial_putc('o');
491
492 return vr_ctl;
493}
494
495__attribute__((always_inline)) static inline void
496update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
497{
498 serial_putc('a');
Mike Frysinger268dbf52008-10-11 21:58:33 -0400499
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400500 /* Since we've changed the SCLK above, we may need to update
501 * the UART divisors (UART baud rates are based on SCLK).
Mike Frysinger84451302008-12-10 12:33:54 -0500502 * Do the division by hand as there are no native instructions
503 * for dividing which means we'd generate a libgcc reference.
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400504 */
Mike Frysinger84451302008-12-10 12:33:54 -0500505 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500506 serial_putc('b');
Mike Frysinger84451302008-12-10 12:33:54 -0500507 unsigned int sdivR, vcoR;
508 sdivR = bfin_read_PLL_DIV() & 0xf;
509 vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
510 int dividend = sdivB * divB * vcoR;
511 int divisor = vcoB * sdivR;
512 unsigned int quotient;
513 for (quotient = 0; dividend > 0; ++quotient)
514 dividend -= divisor;
515 serial_early_put_div(quotient - ANOMALY_05000230);
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500516 serial_putc('c');
Mike Frysinger84451302008-12-10 12:33:54 -0500517 }
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400518
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500519 serial_putc('d');
520}
521
522__attribute__((always_inline)) static inline void
523program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
524{
525 serial_putc('a');
526
527 if (!CONFIG_MEM_SIZE)
528 return;
529
530 serial_putc('b');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400531
Mike Frysinger268dbf52008-10-11 21:58:33 -0400532 /* Program the external memory controller before we come out of
533 * self-refresh. This only works with our SDRAM controller.
534 */
535#ifndef EBIU_RSTCTL
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500536# ifdef CONFIG_EBIU_SDRRC_VAL
Mike Frysinger268dbf52008-10-11 21:58:33 -0400537 bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500538# endif
539# ifdef CONFIG_EBIU_SDBCTL_VAL
Mike Frysinger268dbf52008-10-11 21:58:33 -0400540 bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500541# endif
542# ifdef CONFIG_EBIU_SDGCTL_VAL
Mike Frysinger268dbf52008-10-11 21:58:33 -0400543 bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500544# endif
Mike Frysinger268dbf52008-10-11 21:58:33 -0400545#endif
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400546
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500547 serial_putc('c');
Mike Frysinger268dbf52008-10-11 21:58:33 -0400548
549 /* Now that we've reprogrammed, take things out of self refresh. */
550 if (put_into_srfs)
551#ifdef EBIU_RSTCTL
552 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
553#else
554 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400555#endif
556
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500557 serial_putc('d');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400558
Mike Frysinger268dbf52008-10-11 21:58:33 -0400559 /* Our DDR controller sucks and cannot be programmed while in
560 * self-refresh. So we have to pull it out before programming.
561 */
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400562#ifdef EBIU_RSTCTL
Mike Frysinger4368ea22009-11-09 19:38:23 -0500563# ifdef CONFIG_EBIU_RSTCTL_VAL
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400564 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
Mike Frysinger4368ea22009-11-09 19:38:23 -0500565# endif
566# ifdef CONFIG_EBIU_DDRCTL0_VAL
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400567 bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
Mike Frysinger4368ea22009-11-09 19:38:23 -0500568# endif
569# ifdef CONFIG_EBIU_DDRCTL1_VAL
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400570 bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
Mike Frysinger4368ea22009-11-09 19:38:23 -0500571# endif
572# ifdef CONFIG_EBIU_DDRCTL2_VAL
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400573 bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
Mike Frysinger4368ea22009-11-09 19:38:23 -0500574# endif
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400575# ifdef CONFIG_EBIU_DDRCTL3_VAL
576 /* default is disable, so don't need to force this */
577 bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
578# endif
Mike Frysinger268dbf52008-10-11 21:58:33 -0400579# ifdef CONFIG_EBIU_DDRQUE_VAL
580 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
581# endif
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400582#endif
583
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500584 serial_putc('e');
585}
586
587__attribute__((always_inline)) static inline void
588check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
589{
590 serial_putc('a');
591
592 if (!CONFIG_MEM_SIZE)
593 return;
594
595 serial_putc('b');
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400596
Mike Frysinger268dbf52008-10-11 21:58:33 -0400597 /* Are we coming out of hibernate (suspend to memory) ?
598 * The memory layout is:
599 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
600 * 0x4: return address
601 * 0x8: stack pointer
602 *
603 * SCKELOW is unreliable on older parts (anomaly 307)
604 */
605 if (ANOMALY_05000307 || vr_ctl & 0x8000) {
606 uint32_t *hibernate_magic = 0;
607 __builtin_bfin_ssync(); /* make sure memory controller is done */
608 if (hibernate_magic[0] == 0xDEADBEEF) {
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500609 serial_putc('c');
Mike Frysinger268dbf52008-10-11 21:58:33 -0400610 bfin_write_EVT15(hibernate_magic[1]);
611 bfin_write_IMASK(EVT_IVG15);
612 __asm__ __volatile__ (
613 /* load reti early to avoid anomaly 281 */
614 "reti = %0;"
615 /* clear hibernate magic */
616 "[%0] = %1;"
617 /* load stack pointer */
618 "SP = [%0 + 8];"
619 /* lower ourselves from reset ivg to ivg15 */
620 "raise 15;"
621 "rti;"
622 :
623 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
624 );
625 }
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500626 serial_putc('d');
Mike Frysinger268dbf52008-10-11 21:58:33 -0400627 }
628
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500629 serial_putc('e');
630}
631
632__attribute__((always_inline)) static inline void
633program_async_controller(ADI_BOOT_DATA *bs)
634{
635 serial_putc('a');
Mike Frysinger268dbf52008-10-11 21:58:33 -0400636
637 /* Program the async banks controller. */
638 bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
639 bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
640 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
641
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500642 serial_putc('b');
643
Mike Frysinger268dbf52008-10-11 21:58:33 -0400644 /* Not all parts have these additional MMRs. */
Mike Frysinger4368ea22009-11-09 19:38:23 -0500645#ifdef EBIU_MODE
646# ifdef CONFIG_EBIU_MBSCTL_VAL
Mike Frysinger268dbf52008-10-11 21:58:33 -0400647 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
Mike Frysinger4368ea22009-11-09 19:38:23 -0500648# endif
649# ifdef CONFIG_EBIU_MODE_VAL
Mike Frysinger268dbf52008-10-11 21:58:33 -0400650 bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
Mike Frysinger4368ea22009-11-09 19:38:23 -0500651# endif
652# ifdef CONFIG_EBIU_FCTL_VAL
Mike Frysinger268dbf52008-10-11 21:58:33 -0400653 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
Mike Frysinger4368ea22009-11-09 19:38:23 -0500654# endif
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400655#endif
656
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500657 serial_putc('c');
658}
659
660BOOTROM_CALLED_FUNC_ATTR
661void initcode(ADI_BOOT_DATA *bs)
662{
663 ADI_BOOT_DATA bootstruct_scratch;
664
Mike Frysingereb2a3992010-05-05 02:07:44 -0400665 /* Setup NMI handler before anything else */
666 program_nmi_handler();
667
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500668 serial_init();
669
670 serial_putc('A');
671
672 /* If the bootstruct is NULL, then it's because we're loading
673 * dynamically and not via LDR (bootrom). So set the struct to
674 * some scratch space.
675 */
676 if (!bs)
677 bs = &bootstruct_scratch;
678
679 serial_putc('B');
680 bool put_into_srfs = maybe_self_refresh(bs);
681
682 serial_putc('C');
683 uint sdivB, divB, vcoB;
684 program_early_devices(bs, &sdivB, &divB, &vcoB);
685
686 serial_putc('D');
687 u16 vr_ctl = program_clocks(bs, put_into_srfs);
688
689 serial_putc('E');
690 update_serial_clocks(bs, sdivB, divB, vcoB);
691
692 serial_putc('F');
693 program_memory_controller(bs, put_into_srfs);
694
695 serial_putc('G');
696 check_hibernation(bs, vr_ctl, put_into_srfs);
697
698 serial_putc('H');
699 program_async_controller(bs);
Mike Frysinger268dbf52008-10-11 21:58:33 -0400700
Mike Frysingera48e0ed2009-04-24 23:39:41 -0400701#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
Mike Frysinger3343bfa2009-11-09 19:44:04 -0500702 serial_putc('I');
Mike Frysinger1100b692010-04-29 02:49:41 -0400703 /* Tell the bootrom where our entry point is so that it knows
704 * where to jump to when finishing processing the LDR. This
705 * allows us to avoid small jump blocks in the LDR, and also
706 * works around anomaly 05000389 (init address in external
707 * memory causes bootrom to trigger external addressing IVHW).
708 */
Mike Frysinger99593682008-10-18 04:04:49 -0400709 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
710 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
Mike Frysingera48e0ed2009-04-24 23:39:41 -0400711#endif
Mike Frysinger99593682008-10-18 04:04:49 -0400712
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400713 serial_putc('>');
714 serial_putc('\n');
715
716 serial_deinit();
717}