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git01.mediatek.com / filogic / uboot / 76dd6c78ce2d2313343fce5f7e984a6c4a17a941 / . / board / ispan / ispan.c
blob: e41a7c45a82eb6ffa45538bc0796d2919f480915 [file] [log] [blame]
wdenk76dd6c72004-06-09 14:47:54 +0000[diff] [blame^]1/*
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * Support for Interphase iSPAN Communications Controllers
6 * (453x and others). Tested on 4532.
7 *
8 * Derived from iSPAN 4539 port (iphase4539) by
9 * Wolfgang Grandegger <wg@denx.de>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <common.h>
31#include <ioports.h>
32#include <mpc8260.h>
33#include <asm/io.h>
34
35/*
36 * I/O Ports configuration table
37 *
38 * If conf is 1, then that port pin will be configured at boot time
39 * according to the five values podr/pdir/ppar/psor/pdat for that entry
40 */
41
42#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
43#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
44#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
45
46const iop_conf_t iop_conf_tab[4][32] = {
47 /* Port A */
48 { /* conf ppar psor pdir podr pdat */
49 /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
50 /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
51 /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
52 /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
53 /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
54 /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
55 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
56 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
57 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
58 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
59 /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
60 /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
61 /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
62 /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
63 /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
64 /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
65 /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
66 /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
67 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
68 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
69 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
70 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
71 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */
72 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */
73 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
74 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
75 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
76 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
77 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
78 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
79 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
80 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
81 },
82
83 /* Port B */
84 { /* conf ppar psor pdir podr pdat */
85 /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
86 /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
87 /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
88 /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
89 /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
90 /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
91 /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
92 /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
93 /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
94 /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
95 /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
96 /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
97 /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
98 /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
99 /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
100 /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
101 /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
102 /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
103 /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
104 /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
105 /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
106 /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
107 /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
108 /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
109 /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
110 /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
111 /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
112 /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
113 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
114 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
115 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
116 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
117 },
118
119 /* Port C */
120 { /* conf ppar psor pdir podr pdat */
121 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
122 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
123 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
124 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
125 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
126 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
127 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
128 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
129 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
130 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
131 /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
132 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
133 /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
134 /* PC18 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */
135 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
136 /* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */
137 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
138 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
139 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
140 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
141 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
142 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
143 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
144 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
145 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
146 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
147 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
148 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
149 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
150 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
151 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
152 /* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */
153 },
154
155 /* Port D */
156 { /* conf ppar psor pdir podr pdat */
157 /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
158 /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
159 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
160 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
161 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
162 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
163 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
164 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
165 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
166 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
167 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
168 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
169 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
170 /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */
171 /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */
172 /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */
173 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
174 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
175 /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */
176 /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */
177 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
178 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
179 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */
180 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */
181 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
182 /* PD6 */ { CFG_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */
183 /* PD5 */ { CFG_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */
184 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
185 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
186 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
187 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
188 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
189 }
190};
191
192#define PSPAN_ADDR 0xF0020000
193#define EEPROM_REG 0x408
194#define EEPROM_READ_CMD 0xA000
195#define PSPAN_WRITE(a,v) \
196 *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
197#define PSPAN_READ(a) \
198 *((volatile unsigned long *)(PSPAN_ADDR+(a)))
199
200static int seeprom_read (int addr, uchar * data, int size)
201{
202 ulong val, cmd;
203 int i;
204
205 for (i = 0; i < size; i++) {
206
207 cmd = EEPROM_READ_CMD;
208 cmd |= ((addr + i) << 24) & 0xff000000;
209
210 /* Wait for ACT to authorize write */
211 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
212 eieio ();
213
214 /* Write command */
215 PSPAN_WRITE (EEPROM_REG, cmd);
216
217 /* Wait for data to be valid */
218 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
219 eieio ();
220 /* Do it twice, first read might be erratic */
221 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
222 eieio ();
223
224 /* Read error */
225 if (val & 0x00000040) {
226 return -1;
227 } else {
228 data[i] = (val >> 16) & 0xff;
229 }
230 }
231 return 0;
232}
233
234/***************************************************************
235 * We take some basic Hardware Configuration Parameter from the
236 * Serial EEPROM conected to the PSpan bridge. We keep it as
237 * simple as possible.
238 */
239static int hwc_flash_size (void)
240{
241 uchar byte;
242
243 if (!seeprom_read (0x40, &byte, sizeof (byte))) {
244 switch ((byte >> 2) & 0x3) {
245 case 0x1:
246 return 0x0400000;
247 break;
248 case 0x2:
249 return 0x0800000;
250 break;
251 case 0x3:
252 return 0x1000000;
253 default:
254 return 0x0100000;
255 }
256 }
257 return -1;
258}
259
260static int hwc_local_sdram_size (void)
261{
262 uchar byte;
263
264 if (!seeprom_read (0x40, &byte, sizeof (byte))) {
265 switch ((byte & 0x03)) {
266 case 0x1:
267 return 0x0800000;
268 case 0x2:
269 return 0x1000000;
270 default:
271 return 0; /* not present */
272 }
273 }
274 return -1;
275}
276
277static int hwc_main_sdram_size (void)
278{
279 uchar byte;
280
281 if (!seeprom_read (0x41, &byte, sizeof (byte))) {
282 return 0x1000000 << ((byte >> 5) & 0x7);
283 }
284 return -1;
285}
286
287static int hwc_serial_number (void)
288{
289 int sn = -1;
290
291 if (!seeprom_read (0xa0, (char *) &sn, sizeof (sn))) {
292 sn = cpu_to_le32 (sn);
293 }
294 return sn;
295}
296
297static int hwc_mac_address (char *str)
298{
299 char mac[6];
300
301 if (!seeprom_read (0xb0, mac, sizeof (mac))) {
302 sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
303 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
304 } else {
305 strcpy (str, "ERROR");
306 return -1;
307 }
308 return 0;
309}
310
311static int hwc_manufact_date (char *str)
312{
313 uchar byte;
314 int value;
315
316 if (seeprom_read (0x92, &byte, sizeof (byte)))
317 goto out;
318 value = byte;
319 if (seeprom_read (0x93, &byte, sizeof (byte)))
320 goto out;
321 value += byte << 8;
322 sprintf (str, "%02d/%02d/%04d",
323 value & 0x1F, (value >> 5) & 0xF,
324 1980 + ((value >> 9) & 0x1FF));
325 return 0;
326
327out:
328 strcpy (str, "ERROR");
329 return -1;
330}
331
332static int hwc_board_type (char **str)
333{
334 ushort id = 0;
335
336 if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
337 switch (id) {
338 case 0x9080:
339 *str = "4532-002";
340 break;
341 case 0x9081:
342 *str = "4532-001";
343 break;
344 case 0x9082:
345 *str = "4532-000";
346 break;
347 default:
348 *str = "Unknown";
349 }
350 } else {
351 *str = "Unknown";
352 }
353
354 return id;
355}
356
357long int initdram (int board_type)
358{
359 long maxsize = hwc_main_sdram_size();
360
361#if !defined(CFG_RAMBOOT) && !defined(CFG_USE_FIRMWARE)
362 volatile immap_t *immap = (immap_t *) CFG_IMMR;
363 volatile memctl8260_t *memctl = &immap->im_memctl;
364 volatile uchar *base;
365 int i;
366
367 immap->im_siu_conf.sc_ppc_acr = 0x00000026;
368 immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
369 immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
370 immap->im_siu_conf.sc_lcl_acr = 0x00000000;
371 immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
372 immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
373 immap->im_siu_conf.sc_tescr1 = 0x00004000;
374 immap->im_siu_conf.sc_ltescr1 = 0x00004000;
375
376 memctl->memc_mptpr = CFG_MPTPR;
377
378 /* Initialise 60x bus SDRAM */
379 base = (uchar *)(CFG_SDRAM_BASE | 0x110);
380 memctl->memc_psrt = CFG_PSRT;
381 memctl->memc_or1 = CFG_60x_OR;
382 memctl->memc_br1 = CFG_SDRAM_BASE | CFG_60x_BR;
383
384 memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
385 *base = 0xFF;
386 memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
387 for (i = 0; i < 8; i++)
388 *base = 0xFF;
389 memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
390 *base = 0xFF;
391 memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
392
393 /* Initialise local bus SDRAM */
394 base = (uchar *)CFG_LSDRAM_BASE;
395 memctl->memc_lsrt = CFG_LSRT;
396 memctl->memc_or2 = CFG_LOC_OR;
397 memctl->memc_br2 = CFG_LSDRAM_BASE | CFG_LOC_BR;
398
399 memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
400 *base = 0xFF;
401 memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
402 for (i = 0; i < 8; i++)
403 *base = 0xFF;
404 memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
405 *base = 0xFF;
406 memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
407
408 /* We must be able to test a location outsize the maximum legal size
409 * to find out THAT we are outside; but this address still has to be
410 * mapped by the controller. That means, that the initial mapping has
411 * to be (at least) twice as large as the maximum expected size.
412 */
413 maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
414
415 maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
416
417 memctl->memc_or1 |= ~(maxsize - 1);
418
419 if (maxsize != hwc_main_sdram_size())
420 puts("Oops: memory test has not found all memory!\n");
421#endif /* !CFG_RAMBOOT && !CFG_USE_FIRMWARE */
422
423 /* Return total RAM size (size of 60x SDRAM) */
424 return maxsize;
425}
426
427int checkboard(void)
428{
429 char string[32], *id;
430
431 hwc_manufact_date(string);
432 hwc_board_type(&id);
433 printf("Board: Interphase iSPAN %s (#%d %s)\n",
434 id, hwc_serial_number(), string);
435#ifdef DEBUG
436 printf("Manufacturing date: %s\n", string);
437 printf("Serial number : %d\n", hwc_serial_number());
438 printf("FLASH size : %d MB\n", hwc_flash_size() >> 20);
439 printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20);
440 printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20);
441 hwc_mac_address(string);
442 printf("MAC address : %s\n", string);
443#endif
444 return 0;
445}
446
447int misc_init_r(void)
448{
449 char *s, str[32];
450 int num;
451
452 if ((s = getenv("serial#")) == NULL &&
453 (num = hwc_serial_number()) != -1) {
454 sprintf(str, "%06d", num);
455 setenv("serial#", str);
456 }
457 if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
458 setenv("ethaddr", str);
459 }
460
461 return 0;
462}