Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 2 | /* |
| 3 | * Common configuration header file for all Keystone II EVM platforms |
| 4 | * |
| 5 | * (C) Copyright 2012-2014 |
| 6 | * Texas Instruments Incorporated, <www.ti.com> |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_KS2_EVM_H |
| 10 | #define __CONFIG_KS2_EVM_H |
| 11 | |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 12 | /* U-Boot Build Configuration */ |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 13 | |
| 14 | /* SoC Configuration */ |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 15 | |
| 16 | /* Memory Configuration */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 17 | #define CFG_SYS_LPAE_SDRAM_BASE 0x800000000 |
Tom Rini | db9c39e | 2022-12-04 10:04:51 -0500 | [diff] [blame] | 18 | #define CFG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 19 | |
Lokesh Vutla | e020861 | 2015-09-19 15:00:17 +0530 | [diff] [blame] | 20 | #ifdef CONFIG_SYS_MALLOC_F_LEN |
| 21 | #define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN |
| 22 | #else |
| 23 | #define SPL_MALLOC_F_SIZE 0 |
| 24 | #endif |
| 25 | |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 26 | /* SPL SPI Loader Configuration */ |
Phil Edworthy | 4f91f36 | 2017-02-03 12:31:46 +0000 | [diff] [blame] | 27 | #define KEYSTONE_SPL_STACK_SIZE (8 * 1024) |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 28 | |
Franklin S Cooper Jr | 29f7313 | 2017-03-13 15:04:26 +0200 | [diff] [blame] | 29 | /* SRAM scratch space entries */ |
Tom Rini | 0cb89e7 | 2022-05-19 15:09:22 -0400 | [diff] [blame] | 30 | #define SRAM_SCRATCH_SPACE_ADDR 0xc0c23fc |
Franklin S Cooper Jr | 29f7313 | 2017-03-13 15:04:26 +0200 | [diff] [blame] | 31 | |
| 32 | #define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR) |
| 33 | #define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) |
| 34 | #define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) |
| 35 | |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 36 | /* UART Configuration */ |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 37 | #define CFG_SYS_NS16550_COM1 KS2_UART0_BASE |
| 38 | #define CFG_SYS_NS16550_COM2 KS2_UART1_BASE |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 39 | |
Vitaly Andrianov | 7fd5b64 | 2015-09-19 16:26:41 +0530 | [diff] [blame] | 40 | #ifndef CONFIG_SOC_K2G |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 41 | #define CFG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) |
Vitaly Andrianov | 7fd5b64 | 2015-09-19 16:26:41 +0530 | [diff] [blame] | 42 | #else |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 43 | #define CFG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 |
Vitaly Andrianov | 7fd5b64 | 2015-09-19 16:26:41 +0530 | [diff] [blame] | 44 | #endif |
| 45 | |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 46 | /* SPI Configuration */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 47 | #define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 48 | |
Khoronzhuk, Ivan | f2c13ba | 2014-09-29 22:17:22 +0300 | [diff] [blame] | 49 | /* Keystone net */ |
Tom Rini | 5e22334 | 2022-12-04 10:04:26 -0500 | [diff] [blame] | 50 | #define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR |
Tom Rini | cdc9e0f | 2022-12-04 10:04:27 -0500 | [diff] [blame] | 51 | #define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE |
Tom Rini | c71cb12 | 2022-12-04 10:04:30 -0500 | [diff] [blame] | 52 | #define CFG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE |
Tom Rini | c2e481e | 2022-12-04 10:04:29 -0500 | [diff] [blame] | 53 | #define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE |
Tom Rini | fd130b8 | 2022-12-04 10:04:28 -0500 | [diff] [blame] | 54 | #define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES |
Khoronzhuk, Ivan | f2c13ba | 2014-09-29 22:17:22 +0300 | [diff] [blame] | 55 | |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 56 | /* EEPROM definitions */ |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 57 | |
| 58 | /* NAND Configuration */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 59 | #define CFG_SYS_NAND_MASK_CLE 0x4000 |
| 60 | #define CFG_SYS_NAND_MASK_ALE 0x2000 |
| 61 | #define CFG_SYS_NAND_CS 2 |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 62 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 63 | #define CFG_SYS_NAND_LARGEPAGE |
| 64 | #define CFG_SYS_NAND_BASE_LIST { 0x30000000, } |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 65 | |
Jean-Jacques Hiblot | 97603e6 | 2018-12-04 11:13:01 +0100 | [diff] [blame] | 66 | |
Jean-Jacques Hiblot | 97603e6 | 2018-12-04 11:13:01 +0100 | [diff] [blame] | 67 | |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 68 | /* U-Boot general configuration */ |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 69 | |
| 70 | /* EDMA3 */ |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 71 | |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 72 | |
Nishanth Menon | b447151 | 2015-07-22 18:05:45 -0500 | [diff] [blame] | 73 | /* Now for the remaining common defines */ |
| 74 | #include <configs/ti_armv7_common.h> |
| 75 | |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 76 | /* we may include files below only after all above definitions */ |
| 77 | #include <asm/arch/hardware.h> |
| 78 | #include <asm/arch/clock.h> |
Vitaly Andrianov | 7fd5b64 | 2015-09-19 16:26:41 +0530 | [diff] [blame] | 79 | #ifndef CONFIG_SOC_K2G |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 80 | #define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) |
Vitaly Andrianov | 7fd5b64 | 2015-09-19 16:26:41 +0530 | [diff] [blame] | 81 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 82 | #define CFG_SYS_HZ_CLOCK get_external_clk(sys_clk) |
Vitaly Andrianov | 7fd5b64 | 2015-09-19 16:26:41 +0530 | [diff] [blame] | 83 | #endif |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 84 | |
Hao Zhang | eb01de2 | 2014-07-09 23:44:48 +0300 | [diff] [blame] | 85 | #endif /* __CONFIG_KS2_EVM_H */ |