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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Hao Zhangeb01de22014-07-09 23:44:48 +03002/*
3 * Common configuration header file for all Keystone II EVM platforms
4 *
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
Hao Zhangeb01de22014-07-09 23:44:48 +03007 */
8
9#ifndef __CONFIG_KS2_EVM_H
10#define __CONFIG_KS2_EVM_H
11
Hao Zhangeb01de22014-07-09 23:44:48 +030012/* U-Boot Build Configuration */
Hao Zhangeb01de22014-07-09 23:44:48 +030013
14/* SoC Configuration */
Hao Zhangeb01de22014-07-09 23:44:48 +030015
16/* Memory Configuration */
Tom Rini6a5dccc2022-11-16 13:10:41 -050017#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000
Tom Rinidb9c39e2022-12-04 10:04:51 -050018#define CFG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
Hao Zhangeb01de22014-07-09 23:44:48 +030019
Lokesh Vutlae0208612015-09-19 15:00:17 +053020#ifdef CONFIG_SYS_MALLOC_F_LEN
21#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN
22#else
23#define SPL_MALLOC_F_SIZE 0
24#endif
25
Hao Zhangeb01de22014-07-09 23:44:48 +030026/* SPL SPI Loader Configuration */
Phil Edworthy4f91f362017-02-03 12:31:46 +000027#define KEYSTONE_SPL_STACK_SIZE (8 * 1024)
Hao Zhangeb01de22014-07-09 23:44:48 +030028
Franklin S Cooper Jr29f73132017-03-13 15:04:26 +020029/* SRAM scratch space entries */
Tom Rini0cb89e72022-05-19 15:09:22 -040030#define SRAM_SCRATCH_SPACE_ADDR 0xc0c23fc
Franklin S Cooper Jr29f73132017-03-13 15:04:26 +020031
32#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR)
33#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
34#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
35
Hao Zhangeb01de22014-07-09 23:44:48 +030036/* UART Configuration */
Tom Rinidf6a2152022-11-16 13:10:28 -050037#define CFG_SYS_NS16550_COM1 KS2_UART0_BASE
38#define CFG_SYS_NS16550_COM2 KS2_UART1_BASE
Hao Zhangeb01de22014-07-09 23:44:48 +030039
Vitaly Andrianov7fd5b642015-09-19 16:26:41 +053040#ifndef CONFIG_SOC_K2G
Tom Rinidf6a2152022-11-16 13:10:28 -050041#define CFG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6)
Vitaly Andrianov7fd5b642015-09-19 16:26:41 +053042#else
Tom Rinidf6a2152022-11-16 13:10:28 -050043#define CFG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2
Vitaly Andrianov7fd5b642015-09-19 16:26:41 +053044#endif
45
Hao Zhangeb01de22014-07-09 23:44:48 +030046/* SPI Configuration */
Tom Rini6a5dccc2022-11-16 13:10:41 -050047#define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
Hao Zhangeb01de22014-07-09 23:44:48 +030048
Khoronzhuk, Ivanf2c13ba2014-09-29 22:17:22 +030049/* Keystone net */
Tom Rini5e223342022-12-04 10:04:26 -050050#define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
Tom Rinicdc9e0f2022-12-04 10:04:27 -050051#define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE
Tom Rinic71cb122022-12-04 10:04:30 -050052#define CFG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
Tom Rinic2e481e2022-12-04 10:04:29 -050053#define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
Tom Rinifd130b82022-12-04 10:04:28 -050054#define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
Khoronzhuk, Ivanf2c13ba2014-09-29 22:17:22 +030055
Hao Zhangeb01de22014-07-09 23:44:48 +030056/* EEPROM definitions */
Hao Zhangeb01de22014-07-09 23:44:48 +030057
58/* NAND Configuration */
Tom Rinib4213492022-11-12 17:36:51 -050059#define CFG_SYS_NAND_MASK_CLE 0x4000
60#define CFG_SYS_NAND_MASK_ALE 0x2000
61#define CFG_SYS_NAND_CS 2
Hao Zhangeb01de22014-07-09 23:44:48 +030062
Tom Rinib4213492022-11-12 17:36:51 -050063#define CFG_SYS_NAND_LARGEPAGE
64#define CFG_SYS_NAND_BASE_LIST { 0x30000000, }
Hao Zhangeb01de22014-07-09 23:44:48 +030065
Jean-Jacques Hiblot97603e62018-12-04 11:13:01 +010066
Jean-Jacques Hiblot97603e62018-12-04 11:13:01 +010067
Hao Zhangeb01de22014-07-09 23:44:48 +030068/* U-Boot general configuration */
Hao Zhangeb01de22014-07-09 23:44:48 +030069
70/* EDMA3 */
Hao Zhangeb01de22014-07-09 23:44:48 +030071
Hao Zhangeb01de22014-07-09 23:44:48 +030072
Nishanth Menonb4471512015-07-22 18:05:45 -050073/* Now for the remaining common defines */
74#include <configs/ti_armv7_common.h>
75
Hao Zhangeb01de22014-07-09 23:44:48 +030076/* we may include files below only after all above definitions */
77#include <asm/arch/hardware.h>
78#include <asm/arch/clock.h>
Vitaly Andrianov7fd5b642015-09-19 16:26:41 +053079#ifndef CONFIG_SOC_K2G
Tom Rini6a5dccc2022-11-16 13:10:41 -050080#define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
Vitaly Andrianov7fd5b642015-09-19 16:26:41 +053081#else
Tom Rini6a5dccc2022-11-16 13:10:41 -050082#define CFG_SYS_HZ_CLOCK get_external_clk(sys_clk)
Vitaly Andrianov7fd5b642015-09-19 16:26:41 +053083#endif
Hao Zhangeb01de22014-07-09 23:44:48 +030084
Hao Zhangeb01de22014-07-09 23:44:48 +030085#endif /* __CONFIG_KS2_EVM_H */