| Stefan Kristiansson | 6e560bb | 2011-11-26 19:04:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation; either version 2 of |
| 7 | * the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 17 | * MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef __ASM_OPENRISC_CACHE_H_ |
| 21 | #define __ASM_OPENRISC_CACHE_H_ |
| 22 | |
| 23 | /* |
| 24 | * Valid L1 data cache line sizes for the OpenRISC architecture are |
| 25 | * 16 and 32 bytes. |
| 26 | * If the board configuration has not specified one we default to the |
| 27 | * largest of these values for alignment of DMA buffers. |
| 28 | */ |
| 29 | #ifdef CONFIG_SYS_CACHELINE_SIZE |
| 30 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
| 31 | #else |
| 32 | #define ARCH_DMA_MINALIGN 32 |
| 33 | #endif |
| 34 | |
| 35 | #endif /* __ASM_OPENRISC_CACHE_H_ */ |