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git01.mediatek.com / filogic / uboot / 76c28d93006856fd37539878cb21f9701ecf274b / . / drivers / ddr / marvell / a38x / old / ddr3_training.c
blob: c5ebd7c16d549c9e516e07b5f0257a80d1b38964 [file] [log] [blame]
Marek Behún76c28d92024-06-18 17:34:35 +0200[diff] [blame^]1/*
2 * Copyright (C) Marvell International Ltd. and its affiliates
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <spl.h>
8#include <asm/io.h>
9#include <asm/arch/cpu.h>
10#include <asm/arch/soc.h>
11
12#include "ddr3_init.h"
13
14#define GET_MAX_VALUE(x, y) \
15 ((x) > (y)) ? (x) : (y)
16#define CEIL_DIVIDE(x, y) \
17 ((x - (x / y) * y) == 0) ? ((x / y) - 1) : (x / y)
18
19#define TIME_2_CLOCK_CYCLES CEIL_DIVIDE
20
21#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask])
22#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
23
24u32 window_mem_addr = 0;
25u32 phy_reg0_val = 0;
26u32 phy_reg1_val = 8;
27u32 phy_reg2_val = 0;
28u32 phy_reg3_val = 0xa;
29enum hws_ddr_freq init_freq = DDR_FREQ_667;
30enum hws_ddr_freq low_freq = DDR_FREQ_LOW_FREQ;
31enum hws_ddr_freq medium_freq;
32u32 debug_dunit = 0;
33u32 odt_additional = 1;
34u32 *dq_map_table = NULL;
35u32 odt_config = 1;
36
37#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || \
38 defined(CONFIG_ARMADA_39X)
39u32 is_pll_before_init = 0, is_adll_calib_before_init = 0, is_dfs_in_init = 0;
40u32 dfs_low_freq = 130;
41#else
42u32 is_pll_before_init = 0, is_adll_calib_before_init = 1, is_dfs_in_init = 0;
43u32 dfs_low_freq = 100;
44#endif
45u32 g_rtt_nom_c_s0, g_rtt_nom_c_s1;
46u8 calibration_update_control; /* 2 external only, 1 is internal only */
47
48enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
49enum auto_tune_stage training_stage = INIT_CONTROLLER;
50u32 finger_test = 0, p_finger_start = 11, p_finger_end = 64,
51 n_finger_start = 11, n_finger_end = 64,
52 p_finger_step = 3, n_finger_step = 3;
53u32 clamp_tbl[] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
54
55/* Initiate to 0xff, this variable is define by user in debug mode */
56u32 mode2_t = 0xff;
57u32 xsb_validate_type = 0;
58u32 xsb_validation_base_address = 0xf000;
59u32 first_active_if = 0;
60u32 dfs_low_phy1 = 0x1f;
61u32 multicast_id = 0;
62int use_broadcast = 0;
63struct hws_tip_freq_config_info *freq_info_table = NULL;
64u8 is_cbe_required = 0;
65u32 debug_mode = 0;
66u32 delay_enable = 0;
67int rl_mid_freq_wa = 0;
68
69u32 effective_cs = 0;
70
71u32 mask_tune_func = (SET_MEDIUM_FREQ_MASK_BIT |
72 WRITE_LEVELING_MASK_BIT |
73 LOAD_PATTERN_2_MASK_BIT |
74 READ_LEVELING_MASK_BIT |
75 SET_TARGET_FREQ_MASK_BIT | WRITE_LEVELING_TF_MASK_BIT |
76 READ_LEVELING_TF_MASK_BIT |
77 CENTRALIZATION_RX_MASK_BIT | CENTRALIZATION_TX_MASK_BIT);
78
79void ddr3_print_version(void)
80{
81 printf(DDR3_TIP_VERSION_STRING);
82}
83
84static int ddr3_tip_ddr3_training_main_flow(u32 dev_num);
85static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
86 u32 if_id, u32 cl_value, u32 cwl_value);
87static int ddr3_tip_ddr3_auto_tune(u32 dev_num);
88static int is_bus_access_done(u32 dev_num, u32 if_id,
89 u32 dunit_reg_adrr, u32 bit);
90#ifdef ODT_TEST_SUPPORT
91static int odt_test(u32 dev_num, enum hws_algo_type algo_type);
92#endif
93
94int adll_calibration(u32 dev_num, enum hws_access_type access_type,
95 u32 if_id, enum hws_ddr_freq frequency);
96static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
97 u32 if_id, enum hws_ddr_freq frequency);
98
99static struct page_element page_param[] = {
100 /*
101 * 8bits 16 bits
102 * page-size(K) page-size(K) mask
103 */
104 { 1, 2, 2},
105 /* 512M */
106 { 1, 2, 3},
107 /* 1G */
108 { 1, 2, 0},
109 /* 2G */
110 { 1, 2, 4},
111 /* 4G */
112 { 2, 2, 5}
113 /* 8G */
114};
115
116static u8 mem_size_config[MEM_SIZE_LAST] = {
117 0x2, /* 512Mbit */
118 0x3, /* 1Gbit */
119 0x0, /* 2Gbit */
120 0x4, /* 4Gbit */
121 0x5 /* 8Gbit */
122};
123
124static u8 cs_mask2_num[] = { 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 };
125
126static struct reg_data odpg_default_value[] = {
127 {0x1034, 0x38000, MASK_ALL_BITS},
128 {0x1038, 0x0, MASK_ALL_BITS},
129 {0x10b0, 0x0, MASK_ALL_BITS},
130 {0x10b8, 0x0, MASK_ALL_BITS},
131 {0x10c0, 0x0, MASK_ALL_BITS},
132 {0x10f0, 0x0, MASK_ALL_BITS},
133 {0x10f4, 0x0, MASK_ALL_BITS},
134 {0x10f8, 0xff, MASK_ALL_BITS},
135 {0x10fc, 0xffff, MASK_ALL_BITS},
136 {0x1130, 0x0, MASK_ALL_BITS},
137 {0x1830, 0x2000000, MASK_ALL_BITS},
138 {0x14d0, 0x0, MASK_ALL_BITS},
139 {0x14d4, 0x0, MASK_ALL_BITS},
140 {0x14d8, 0x0, MASK_ALL_BITS},
141 {0x14dc, 0x0, MASK_ALL_BITS},
142 {0x1454, 0x0, MASK_ALL_BITS},
143 {0x1594, 0x0, MASK_ALL_BITS},
144 {0x1598, 0x0, MASK_ALL_BITS},
145 {0x159c, 0x0, MASK_ALL_BITS},
146 {0x15a0, 0x0, MASK_ALL_BITS},
147 {0x15a4, 0x0, MASK_ALL_BITS},
148 {0x15a8, 0x0, MASK_ALL_BITS},
149 {0x15ac, 0x0, MASK_ALL_BITS},
150 {0x1604, 0x0, MASK_ALL_BITS},
151 {0x1608, 0x0, MASK_ALL_BITS},
152 {0x160c, 0x0, MASK_ALL_BITS},
153 {0x1610, 0x0, MASK_ALL_BITS},
154 {0x1614, 0x0, MASK_ALL_BITS},
155 {0x1618, 0x0, MASK_ALL_BITS},
156 {0x1624, 0x0, MASK_ALL_BITS},
157 {0x1690, 0x0, MASK_ALL_BITS},
158 {0x1694, 0x0, MASK_ALL_BITS},
159 {0x1698, 0x0, MASK_ALL_BITS},
160 {0x169c, 0x0, MASK_ALL_BITS},
161 {0x14b8, 0x6f67, MASK_ALL_BITS},
162 {0x1630, 0x0, MASK_ALL_BITS},
163 {0x1634, 0x0, MASK_ALL_BITS},
164 {0x1638, 0x0, MASK_ALL_BITS},
165 {0x163c, 0x0, MASK_ALL_BITS},
166 {0x16b0, 0x0, MASK_ALL_BITS},
167 {0x16b4, 0x0, MASK_ALL_BITS},
168 {0x16b8, 0x0, MASK_ALL_BITS},
169 {0x16bc, 0x0, MASK_ALL_BITS},
170 {0x16c0, 0x0, MASK_ALL_BITS},
171 {0x16c4, 0x0, MASK_ALL_BITS},
172 {0x16c8, 0x0, MASK_ALL_BITS},
173 {0x16cc, 0x1, MASK_ALL_BITS},
174 {0x16f0, 0x1, MASK_ALL_BITS},
175 {0x16f4, 0x0, MASK_ALL_BITS},
176 {0x16f8, 0x0, MASK_ALL_BITS},
177 {0x16fc, 0x0, MASK_ALL_BITS}
178};
179
180static int ddr3_tip_bus_access(u32 dev_num, enum hws_access_type interface_access,
181 u32 if_id, enum hws_access_type phy_access,
182 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
183 u32 data_value, enum hws_operation oper_type);
184static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id);
185static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
186
187/*
188 * Update global training parameters by data from user
189 */
190int ddr3_tip_tune_training_params(u32 dev_num,
191 struct tune_train_params *params)
192{
193 if (params->ck_delay != -1)
194 ck_delay = params->ck_delay;
195 if (params->ck_delay_16 != -1)
196 ck_delay_16 = params->ck_delay_16;
197 if (params->phy_reg3_val != -1)
198 phy_reg3_val = params->phy_reg3_val;
199
200 return MV_OK;
201}
202
203/*
204 * Configure CS
205 */
206int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
207{
208 u32 data, addr_hi, data_high;
209 u32 mem_index;
210 struct hws_topology_map *tm = ddr3_get_topology_map();
211
212 if (enable == 1) {
213 data = (tm->interface_params[if_id].bus_width ==
214 BUS_WIDTH_8) ? 0 : 1;
215 CHECK_STATUS(ddr3_tip_if_write
216 (dev_num, ACCESS_TYPE_UNICAST, if_id,
217 SDRAM_ACCESS_CONTROL_REG, (data << (cs_num * 4)),
218 0x3 << (cs_num * 4)));
219 mem_index = tm->interface_params[if_id].memory_size;
220
221 addr_hi = mem_size_config[mem_index] & 0x3;
222 CHECK_STATUS(ddr3_tip_if_write
223 (dev_num, ACCESS_TYPE_UNICAST, if_id,
224 SDRAM_ACCESS_CONTROL_REG,
225 (addr_hi << (2 + cs_num * 4)),
226 0x3 << (2 + cs_num * 4)));
227
228 data_high = (mem_size_config[mem_index] & 0x4) >> 2;
229 CHECK_STATUS(ddr3_tip_if_write
230 (dev_num, ACCESS_TYPE_UNICAST, if_id,
231 SDRAM_ACCESS_CONTROL_REG,
232 data_high << (20 + cs_num), 1 << (20 + cs_num)));
233
234 /* Enable Address Select Mode */
235 CHECK_STATUS(ddr3_tip_if_write
236 (dev_num, ACCESS_TYPE_UNICAST, if_id,
237 SDRAM_ACCESS_CONTROL_REG, 1 << (16 + cs_num),
238 1 << (16 + cs_num)));
239 }
240 switch (cs_num) {
241 case 0:
242 case 1:
243 case 2:
244 CHECK_STATUS(ddr3_tip_if_write
245 (dev_num, ACCESS_TYPE_UNICAST, if_id,
246 DDR_CONTROL_LOW_REG, (enable << (cs_num + 11)),
247 1 << (cs_num + 11)));
248 break;
249 case 3:
250 CHECK_STATUS(ddr3_tip_if_write
251 (dev_num, ACCESS_TYPE_UNICAST, if_id,
252 DDR_CONTROL_LOW_REG, (enable << 15), 1 << 15));
253 break;
254 }
255
256 return MV_OK;
257}
258
259/*
260 * Calculate number of CS
261 */
262static int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num)
263{
264 u32 cs;
265 u32 bus_cnt;
266 u32 cs_count;
267 u32 cs_bitmask;
268 u32 curr_cs_num = 0;
269 struct hws_topology_map *tm = ddr3_get_topology_map();
270
271 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) {
272 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
273 cs_count = 0;
274 cs_bitmask = tm->interface_params[if_id].
275 as_bus_params[bus_cnt].cs_bitmask;
276 for (cs = 0; cs < MAX_CS_NUM; cs++) {
277 if ((cs_bitmask >> cs) & 1)
278 cs_count++;
279 }
280
281 if (curr_cs_num == 0) {
282 curr_cs_num = cs_count;
283 } else if (cs_count != curr_cs_num) {
284 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
285 ("CS number is different per bus (IF %d BUS %d cs_num %d curr_cs_num %d)\n",
286 if_id, bus_cnt, cs_count,
287 curr_cs_num));
288 return MV_NOT_SUPPORTED;
289 }
290 }
291 *cs_num = curr_cs_num;
292
293 return MV_OK;
294}
295
296/*
297 * Init Controller Flow
298 */
299int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm)
300{
301 u32 if_id;
302 u32 cs_num;
303 u32 t_refi = 0, t_hclk = 0, t_ckclk = 0, t_faw = 0, t_pd = 0,
304 t_wr = 0, t2t = 0, txpdll = 0;
305 u32 data_value = 0, bus_width = 0, page_size = 0, cs_cnt = 0,
306 mem_mask = 0, bus_index = 0;
307 enum hws_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N;
308 enum hws_mem_size memory_size = MEM_2G;
309 enum hws_ddr_freq freq = init_freq;
310 enum hws_timing timing;
311 u32 cs_mask = 0;
312 u32 cl_value = 0, cwl_val = 0;
313 u32 refresh_interval_cnt = 0, bus_cnt = 0, adll_tap = 0;
314 enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
315 u32 data_read[MAX_INTERFACE_NUM];
316 struct hws_topology_map *tm = ddr3_get_topology_map();
317
318 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
319 ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
320 init_cntr_prm->do_mrs_phy,
321 init_cntr_prm->is_ctrl64_bit));
322
323 if (init_cntr_prm->init_phy == 1) {
324 CHECK_STATUS(ddr3_tip_configure_phy(dev_num));
325 }
326
327 if (generic_init_controller == 1) {
328 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
329 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
330 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
331 ("active IF %d\n", if_id));
332 mem_mask = 0;
333 for (bus_index = 0;
334 bus_index < GET_TOPOLOGY_NUM_OF_BUSES();
335 bus_index++) {
336 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
337 mem_mask |=
338 tm->interface_params[if_id].
339 as_bus_params[bus_index].mirror_enable_bitmask;
340 }
341
342 if (mem_mask != 0) {
343 CHECK_STATUS(ddr3_tip_if_write
344 (dev_num, ACCESS_TYPE_MULTICAST,
345 if_id, CS_ENABLE_REG, 0,
346 0x8));
347 }
348
349 memory_size =
350 tm->interface_params[if_id].
351 memory_size;
352 speed_bin_index =
353 tm->interface_params[if_id].
354 speed_bin_index;
355 freq = init_freq;
356 t_refi =
357 (tm->interface_params[if_id].
358 interface_temp ==
359 HWS_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW;
360 t_refi *= 1000; /* psec */
361 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
362 ("memy_size %d speed_bin_ind %d freq %d t_refi %d\n",
363 memory_size, speed_bin_index, freq,
364 t_refi));
365 /* HCLK & CK CLK in 2:1[ps] */
366 /* t_ckclk is external clock */
367 t_ckclk = (MEGA / freq_val[freq]);
368 /* t_hclk is internal clock */
369 t_hclk = 2 * t_ckclk;
370 refresh_interval_cnt = t_refi / t_hclk; /* no units */
371 bus_width =
372 (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)
373 == 1) ? (16) : (32);
374
375 if (init_cntr_prm->is_ctrl64_bit)
376 bus_width = 64;
377
378 data_value =
379 (refresh_interval_cnt | 0x4000 |
380 ((bus_width ==
381 32) ? 0x8000 : 0) | 0x1000000) & ~(1 << 26);
382
383 /* Interface Bus Width */
384 /* SRMode */
385 CHECK_STATUS(ddr3_tip_if_write
386 (dev_num, access_type, if_id,
387 SDRAM_CONFIGURATION_REG, data_value,
388 0x100ffff));
389
390 /* Interleave first command pre-charge enable (TBD) */
391 CHECK_STATUS(ddr3_tip_if_write
392 (dev_num, access_type, if_id,
393 SDRAM_OPEN_PAGE_CONTROL_REG, (1 << 10),
394 (1 << 10)));
395
396 /* PHY configuration */
397 /*
398 * Postamble Length = 1.5cc, Addresscntl to clk skew
399 * \BD, Preamble length normal, parralal ADLL enable
400 */
401 CHECK_STATUS(ddr3_tip_if_write
402 (dev_num, access_type, if_id,
403 DRAM_PHY_CONFIGURATION, 0x28, 0x3e));
404 if (init_cntr_prm->is_ctrl64_bit) {
405 /* positive edge */
406 CHECK_STATUS(ddr3_tip_if_write
407 (dev_num, access_type, if_id,
408 DRAM_PHY_CONFIGURATION, 0x0,
409 0xff80));
410 }
411
412 /* calibration block disable */
413 /* Xbar Read buffer select (for Internal access) */
414 CHECK_STATUS(ddr3_tip_if_write
415 (dev_num, access_type, if_id,
416 CALIB_MACHINE_CTRL_REG, 0x1200c,
417 0x7dffe01c));
418 CHECK_STATUS(ddr3_tip_if_write
419 (dev_num, access_type, if_id,
420 CALIB_MACHINE_CTRL_REG,
421 calibration_update_control << 3, 0x3 << 3));
422
423 /* Pad calibration control - enable */
424 CHECK_STATUS(ddr3_tip_if_write
425 (dev_num, access_type, if_id,
426 CALIB_MACHINE_CTRL_REG, 0x1, 0x1));
427
428 cs_mask = 0;
429 data_value = 0x7;
430 /*
431 * Address ctrl \96 Part of the Generic code
432 * The next configuration is done:
433 * 1) Memory Size
434 * 2) Bus_width
435 * 3) CS#
436 * 4) Page Number
437 * 5) t_faw
438 * Per Dunit get from the Map_topology the parameters:
439 * Bus_width
440 * t_faw is per Dunit not per CS
441 */
442 page_size =
443 (tm->interface_params[if_id].
444 bus_width ==
445 BUS_WIDTH_8) ? page_param[memory_size].
446 page_size_8bit : page_param[memory_size].
447 page_size_16bit;
448
449 t_faw =
450 (page_size == 1) ? speed_bin_table(speed_bin_index,
451 SPEED_BIN_TFAW1K)
452 : speed_bin_table(speed_bin_index,
453 SPEED_BIN_TFAW2K);
454
455 data_value = TIME_2_CLOCK_CYCLES(t_faw, t_ckclk);
456 data_value = data_value << 24;
457 CHECK_STATUS(ddr3_tip_if_write
458 (dev_num, access_type, if_id,
459 SDRAM_ACCESS_CONTROL_REG, data_value,
460 0x7f000000));
461
462 data_value =
463 (tm->interface_params[if_id].
464 bus_width == BUS_WIDTH_8) ? 0 : 1;
465
466 /* create merge cs mask for all cs available in dunit */
467 for (bus_cnt = 0;
468 bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES();
469 bus_cnt++) {
470 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
471 cs_mask |=
472 tm->interface_params[if_id].
473 as_bus_params[bus_cnt].cs_bitmask;
474 }
475 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
476 ("Init_controller IF %d cs_mask %d\n",
477 if_id, cs_mask));
478 /*
479 * Configure the next upon the Map Topology \96 If the
480 * Dunit is CS0 Configure CS0 if it is multi CS
481 * configure them both: The Bust_width it\92s the
482 * Memory Bus width \96 x8 or x16
483 */
484 for (cs_cnt = 0; cs_cnt < NUM_OF_CS; cs_cnt++) {
485 ddr3_tip_configure_cs(dev_num, if_id, cs_cnt,
486 ((cs_mask & (1 << cs_cnt)) ? 1
487 : 0));
488 }
489
490 if (init_cntr_prm->do_mrs_phy) {
491 /*
492 * MR0 \96 Part of the Generic code
493 * The next configuration is done:
494 * 1) Burst Length
495 * 2) CAS Latency
496 * get for each dunit what is it Speed_bin &
497 * Target Frequency. From those both parameters
498 * get the appropriate Cas_l from the CL table
499 */
500 cl_value =
501 tm->interface_params[if_id].
502 cas_l;
503 cwl_val =
504 tm->interface_params[if_id].
505 cas_wl;
506 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
507 ("cl_value 0x%x cwl_val 0x%x\n",
508 cl_value, cwl_val));
509
510 data_value =
511 ((cl_mask_table[cl_value] & 0x1) << 2) |
512 ((cl_mask_table[cl_value] & 0xe) << 3);
513 CHECK_STATUS(ddr3_tip_if_write
514 (dev_num, access_type, if_id,
515 MR0_REG, data_value,
516 (0x7 << 4) | (1 << 2)));
517 CHECK_STATUS(ddr3_tip_if_write
518 (dev_num, access_type, if_id,
519 MR0_REG, twr_mask_table[t_wr + 1],
520 0xe00));
521
522 /*
523 * MR1: Set RTT and DIC Design GL values
524 * configured by user
525 */
526 CHECK_STATUS(ddr3_tip_if_write
527 (dev_num, ACCESS_TYPE_MULTICAST,
528 PARAM_NOT_CARE, MR1_REG,
529 g_dic | g_rtt_nom, 0x266));
530
531 /* MR2 - Part of the Generic code */
532 /*
533 * The next configuration is done:
534 * 1) SRT
535 * 2) CAS Write Latency
536 */
537 data_value = (cwl_mask_table[cwl_val] << 3);
538 data_value |=
539 ((tm->interface_params[if_id].
540 interface_temp ==
541 HWS_TEMP_HIGH) ? (1 << 7) : 0);
542 CHECK_STATUS(ddr3_tip_if_write
543 (dev_num, access_type, if_id,
544 MR2_REG, data_value,
545 (0x7 << 3) | (0x1 << 7) | (0x3 <<
546 9)));
547 }
548
549 ddr3_tip_write_odt(dev_num, access_type, if_id,
550 cl_value, cwl_val);
551 ddr3_tip_set_timing(dev_num, access_type, if_id, freq);
552
553 CHECK_STATUS(ddr3_tip_if_write
554 (dev_num, access_type, if_id,
555 DUNIT_CONTROL_HIGH_REG, 0x177,
556 0x1000177));
557
558 if (init_cntr_prm->is_ctrl64_bit) {
559 /* disable 0.25 cc delay */
560 CHECK_STATUS(ddr3_tip_if_write
561 (dev_num, access_type, if_id,
562 DUNIT_CONTROL_HIGH_REG, 0x0,
563 0x800));
564 }
565
566 /* reset bit 7 */
567 CHECK_STATUS(ddr3_tip_if_write
568 (dev_num, access_type, if_id,
569 DUNIT_CONTROL_HIGH_REG,
570 (init_cntr_prm->msys_init << 7), (1 << 7)));
571
572 timing = tm->interface_params[if_id].timing;
573
574 if (mode2_t != 0xff) {
575 t2t = mode2_t;
576 } else if (timing != HWS_TIM_DEFAULT) {
577 /* Board topology map is forcing timing */
578 t2t = (timing == HWS_TIM_2T) ? 1 : 0;
579 } else {
580 /* calculate number of CS (per interface) */
581 CHECK_STATUS(calc_cs_num
582 (dev_num, if_id, &cs_num));
583 t2t = (cs_num == 1) ? 0 : 1;
584 }
585
586 CHECK_STATUS(ddr3_tip_if_write
587 (dev_num, access_type, if_id,
588 DDR_CONTROL_LOW_REG, t2t << 3,
589 0x3 << 3));
590 /* move the block to ddr3_tip_set_timing - start */
591 t_pd = GET_MAX_VALUE(t_ckclk * 3,
592 speed_bin_table(speed_bin_index,
593 SPEED_BIN_TPD));
594 t_pd = TIME_2_CLOCK_CYCLES(t_pd, t_ckclk);
595 txpdll = GET_MAX_VALUE(t_ckclk * 10, 24);
596 txpdll = CEIL_DIVIDE((txpdll - 1), t_ckclk);
597 CHECK_STATUS(ddr3_tip_if_write
598 (dev_num, access_type, if_id,
599 DDR_TIMING_REG, txpdll << 4,
600 0x1f << 4));
601 CHECK_STATUS(ddr3_tip_if_write
602 (dev_num, access_type, if_id,
603 DDR_TIMING_REG, 0x28 << 9, 0x3f << 9));
604 CHECK_STATUS(ddr3_tip_if_write
605 (dev_num, access_type, if_id,
606 DDR_TIMING_REG, 0xa << 21, 0xff << 21));
607
608 /* move the block to ddr3_tip_set_timing - end */
609 /* AUTO_ZQC_TIMING */
610 CHECK_STATUS(ddr3_tip_if_write
611 (dev_num, access_type, if_id,
612 TIMING_REG, (AUTO_ZQC_TIMING | (2 << 20)),
613 0x3fffff));
614 CHECK_STATUS(ddr3_tip_if_read
615 (dev_num, access_type, if_id,
616 DRAM_PHY_CONFIGURATION, data_read, 0x30));
617 data_value =
618 (data_read[if_id] == 0) ? (1 << 11) : 0;
619 CHECK_STATUS(ddr3_tip_if_write
620 (dev_num, access_type, if_id,
621 DUNIT_CONTROL_HIGH_REG, data_value,
622 (1 << 11)));
623
624 /* Set Active control for ODT write transactions */
625 CHECK_STATUS(ddr3_tip_if_write
626 (dev_num, ACCESS_TYPE_MULTICAST,
627 PARAM_NOT_CARE, 0x1494, g_odt_config,
628 MASK_ALL_BITS));
629 }
630 } else {
631#ifdef STATIC_ALGO_SUPPORT
632 CHECK_STATUS(ddr3_tip_static_init_controller(dev_num));
633#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
634 CHECK_STATUS(ddr3_tip_static_phy_init_controller(dev_num));
635#endif
636#endif /* STATIC_ALGO_SUPPORT */
637 }
638
639 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
640 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
641 CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id));
642
643 if (init_cntr_prm->do_mrs_phy) {
644 CHECK_STATUS(ddr3_tip_pad_inv(dev_num, if_id));
645 }
646
647 /* Pad calibration control - disable */
648 CHECK_STATUS(ddr3_tip_if_write
649 (dev_num, access_type, if_id,
650 CALIB_MACHINE_CTRL_REG, 0x0, 0x1));
651 CHECK_STATUS(ddr3_tip_if_write
652 (dev_num, access_type, if_id,
653 CALIB_MACHINE_CTRL_REG,
654 calibration_update_control << 3, 0x3 << 3));
655 }
656
657 CHECK_STATUS(ddr3_tip_enable_init_sequence(dev_num));
658
659 if (delay_enable != 0) {
660 adll_tap = MEGA / (freq_val[freq] * 64);
661 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
662 }
663
664 return MV_OK;
665}
666
667/*
668 * Load Topology map
669 */
670int hws_ddr3_tip_load_topology_map(u32 dev_num, struct hws_topology_map *tm)
671{
672 enum hws_speed_bin speed_bin_index;
673 enum hws_ddr_freq freq = DDR_FREQ_LIMIT;
674 u32 if_id;
675
676 freq_val[DDR_FREQ_LOW_FREQ] = dfs_low_freq;
677 tm = ddr3_get_topology_map();
678 CHECK_STATUS(ddr3_tip_get_first_active_if
679 ((u8)dev_num, tm->if_act_mask,
680 &first_active_if));
681 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
682 ("board IF_Mask=0x%x num_of_bus_per_interface=0x%x\n",
683 tm->if_act_mask,
684 tm->num_of_bus_per_interface));
685
686 /*
687 * if CL, CWL values are missing in topology map, then fill them
688 * according to speedbin tables
689 */
690 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
691 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
692 speed_bin_index =
693 tm->interface_params[if_id].speed_bin_index;
694 /* TBD memory frequency of interface 0 only is used ! */
695 freq = tm->interface_params[first_active_if].memory_freq;
696
697 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
698 ("speed_bin_index =%d freq=%d cl=%d cwl=%d\n",
699 speed_bin_index, freq_val[freq],
700 tm->interface_params[if_id].
701 cas_l,
702 tm->interface_params[if_id].
703 cas_wl));
704
705 if (tm->interface_params[if_id].cas_l == 0) {
706 tm->interface_params[if_id].cas_l =
707 cas_latency_table[speed_bin_index].cl_val[freq];
708 }
709
710 if (tm->interface_params[if_id].cas_wl == 0) {
711 tm->interface_params[if_id].cas_wl =
712 cas_write_latency_table[speed_bin_index].cl_val[freq];
713 }
714 }
715
716 return MV_OK;
717}
718
719/*
720 * RANK Control Flow
721 */
722static int ddr3_tip_rank_control(u32 dev_num, u32 if_id)
723{
724 u32 data_value = 0, bus_cnt;
725 struct hws_topology_map *tm = ddr3_get_topology_map();
726
727 for (bus_cnt = 1; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) {
728 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
729 if ((tm->interface_params[if_id].
730 as_bus_params[0].cs_bitmask !=
731 tm->interface_params[if_id].
732 as_bus_params[bus_cnt].cs_bitmask) ||
733 (tm->interface_params[if_id].
734 as_bus_params[0].mirror_enable_bitmask !=
735 tm->interface_params[if_id].
736 as_bus_params[bus_cnt].mirror_enable_bitmask))
737 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
738 ("WARNING:Wrong configuration for pup #%d CS mask and CS mirroring for all pups should be the same\n",
739 bus_cnt));
740 }
741
742 data_value |= tm->interface_params[if_id].
743 as_bus_params[0].cs_bitmask;
744 data_value |= tm->interface_params[if_id].
745 as_bus_params[0].mirror_enable_bitmask << 4;
746
747 CHECK_STATUS(ddr3_tip_if_write
748 (dev_num, ACCESS_TYPE_UNICAST, if_id, RANK_CTRL_REG,
749 data_value, 0xff));
750
751 return MV_OK;
752}
753
754/*
755 * PAD Inverse Flow
756 */
757static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id)
758{
759 u32 bus_cnt, data_value, ck_swap_pup_ctrl;
760 struct hws_topology_map *tm = ddr3_get_topology_map();
761
762 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) {
763 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
764 if (tm->interface_params[if_id].
765 as_bus_params[bus_cnt].is_dqs_swap == 1) {
766 /* dqs swap */
767 ddr3_tip_bus_read_modify_write(dev_num, ACCESS_TYPE_UNICAST,
768 if_id, bus_cnt,
769 DDR_PHY_DATA,
770 PHY_CONTROL_PHY_REG, 0xc0,
771 0xc0);
772 }
773
774 if (tm->interface_params[if_id].
775 as_bus_params[bus_cnt].is_ck_swap == 1) {
776 if (bus_cnt <= 1)
777 data_value = 0x5 << 2;
778 else
779 data_value = 0xa << 2;
780
781 /* mask equals data */
782 /* ck swap pup is only control pup #0 ! */
783 ck_swap_pup_ctrl = 0;
784 ddr3_tip_bus_read_modify_write(dev_num, ACCESS_TYPE_UNICAST,
785 if_id, ck_swap_pup_ctrl,
786 DDR_PHY_CONTROL,
787 PHY_CONTROL_PHY_REG,
788 data_value, data_value);
789 }
790 }
791
792 return MV_OK;
793}
794
795/*
796 * Run Training Flow
797 */
798int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type)
799{
800 int ret = MV_OK, ret_tune = MV_OK;
801
802#ifdef ODT_TEST_SUPPORT
803 if (finger_test == 1)
804 return odt_test(dev_num, algo_type);
805#endif
806
807 if (algo_type == ALGO_TYPE_DYNAMIC) {
808 ret = ddr3_tip_ddr3_auto_tune(dev_num);
809 } else {
810#ifdef STATIC_ALGO_SUPPORT
811 {
812 enum hws_ddr_freq freq;
813 freq = init_freq;
814
815 /* add to mask */
816 if (is_adll_calib_before_init != 0) {
817 printf("with adll calib before init\n");
818 adll_calibration(dev_num, ACCESS_TYPE_MULTICAST,
819 0, freq);
820 }
821 /*
822 * Frequency per interface is not relevant,
823 * only interface 0
824 */
825 ret = ddr3_tip_run_static_alg(dev_num,
826 freq);
827 }
828#endif
829 }
830
831 if (ret != MV_OK) {
832 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
833 ("Run_alg: tuning failed %d\n", ret_tune));
834 }
835
836 return ret;
837}
838
839#ifdef ODT_TEST_SUPPORT
840/*
841 * ODT Test
842 */
843static int odt_test(u32 dev_num, enum hws_algo_type algo_type)
844{
845 int ret = MV_OK, ret_tune = MV_OK;
846 int pfinger_val = 0, nfinger_val;
847
848 for (pfinger_val = p_finger_start; pfinger_val <= p_finger_end;
849 pfinger_val += p_finger_step) {
850 for (nfinger_val = n_finger_start; nfinger_val <= n_finger_end;
851 nfinger_val += n_finger_step) {
852 if (finger_test != 0) {
853 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
854 ("pfinger_val %d nfinger_val %d\n",
855 pfinger_val, nfinger_val));
856 p_finger = pfinger_val;
857 n_finger = nfinger_val;
858 }
859
860 if (algo_type == ALGO_TYPE_DYNAMIC) {
861 ret = ddr3_tip_ddr3_auto_tune(dev_num);
862 } else {
863 /*
864 * Frequency per interface is not relevant,
865 * only interface 0
866 */
867 ret = ddr3_tip_run_static_alg(dev_num,
868 init_freq);
869 }
870 }
871 }
872
873 if (ret_tune != MV_OK) {
874 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
875 ("Run_alg: tuning failed %d\n", ret_tune));
876 ret = (ret == MV_OK) ? ret_tune : ret;
877 }
878
879 return ret;
880}
881#endif
882
883/*
884 * Select Controller
885 */
886int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable)
887{
888 if (config_func_info[dev_num].tip_dunit_mux_select_func != NULL) {
889 return config_func_info[dev_num].
890 tip_dunit_mux_select_func((u8)dev_num, enable);
891 }
892
893 return MV_FAIL;
894}
895
896/*
897 * Dunit Register Write
898 */
899int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
900 u32 if_id, u32 reg_addr, u32 data_value, u32 mask)
901{
902 if (config_func_info[dev_num].tip_dunit_write_func != NULL) {
903 return config_func_info[dev_num].
904 tip_dunit_write_func((u8)dev_num, interface_access,
905 if_id, reg_addr,
906 data_value, mask);
907 }
908
909 return MV_FAIL;
910}
911
912/*
913 * Dunit Register Read
914 */
915int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
916 u32 if_id, u32 reg_addr, u32 *data, u32 mask)
917{
918 if (config_func_info[dev_num].tip_dunit_read_func != NULL) {
919 return config_func_info[dev_num].
920 tip_dunit_read_func((u8)dev_num, interface_access,
921 if_id, reg_addr,
922 data, mask);
923 }
924
925 return MV_FAIL;
926}
927
928/*
929 * Dunit Register Polling
930 */
931int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
932 u32 if_id, u32 exp_value, u32 mask, u32 offset,
933 u32 poll_tries)
934{
935 u32 poll_cnt = 0, interface_num = 0, start_if, end_if;
936 u32 read_data[MAX_INTERFACE_NUM];
937 int ret;
938 int is_fail = 0, is_if_fail;
939 struct hws_topology_map *tm = ddr3_get_topology_map();
940
941 if (access_type == ACCESS_TYPE_MULTICAST) {
942 start_if = 0;
943 end_if = MAX_INTERFACE_NUM - 1;
944 } else {
945 start_if = if_id;
946 end_if = if_id;
947 }
948
949 for (interface_num = start_if; interface_num <= end_if; interface_num++) {
950 /* polling bit 3 for n times */
951 VALIDATE_ACTIVE(tm->if_act_mask, interface_num);
952
953 is_if_fail = 0;
954 for (poll_cnt = 0; poll_cnt < poll_tries; poll_cnt++) {
955 ret =
956 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST,
957 interface_num, offset, read_data,
958 mask);
959 if (ret != MV_OK)
960 return ret;
961
962 if (read_data[interface_num] == exp_value)
963 break;
964 }
965
966 if (poll_cnt >= poll_tries) {
967 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
968 ("max poll IF #%d\n", interface_num));
969 is_fail = 1;
970 is_if_fail = 1;
971 }
972
973 training_result[training_stage][interface_num] =
974 (is_if_fail == 1) ? TEST_FAILED : TEST_SUCCESS;
975 }
976
977 return (is_fail == 0) ? MV_OK : MV_FAIL;
978}
979
980/*
981 * Bus read access
982 */
983int ddr3_tip_bus_read(u32 dev_num, u32 if_id,
984 enum hws_access_type phy_access, u32 phy_id,
985 enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data)
986{
987 u32 bus_index = 0;
988 u32 data_read[MAX_INTERFACE_NUM];
989 struct hws_topology_map *tm = ddr3_get_topology_map();
990
991 if (phy_access == ACCESS_TYPE_MULTICAST) {
992 for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES();
993 bus_index++) {
994 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
995 CHECK_STATUS(ddr3_tip_bus_access
996 (dev_num, ACCESS_TYPE_UNICAST,
997 if_id, ACCESS_TYPE_UNICAST,
998 bus_index, phy_type, reg_addr, 0,
999 OPERATION_READ));
1000 CHECK_STATUS(ddr3_tip_if_read
1001 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1002 PHY_REG_FILE_ACCESS, data_read,
1003 MASK_ALL_BITS));
1004 data[bus_index] = (data_read[if_id] & 0xffff);
1005 }
1006 } else {
1007 CHECK_STATUS(ddr3_tip_bus_access
1008 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1009 phy_access, phy_id, phy_type, reg_addr, 0,
1010 OPERATION_READ));
1011 CHECK_STATUS(ddr3_tip_if_read
1012 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1013 PHY_REG_FILE_ACCESS, data_read, MASK_ALL_BITS));
1014
1015 /*
1016 * only 16 lsb bit are valid in Phy (each register is different,
1017 * some can actually be less than 16 bits)
1018 */
1019 *data = (data_read[if_id] & 0xffff);
1020 }
1021
1022 return MV_OK;
1023}
1024
1025/*
1026 * Bus write access
1027 */
1028int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,
1029 u32 if_id, enum hws_access_type phy_access,
1030 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
1031 u32 data_value)
1032{
1033 CHECK_STATUS(ddr3_tip_bus_access
1034 (dev_num, interface_access, if_id, phy_access,
1035 phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE));
1036
1037 return MV_OK;
1038}
1039
1040/*
1041 * Bus access routine (relevant for both read & write)
1042 */
1043static int ddr3_tip_bus_access(u32 dev_num, enum hws_access_type interface_access,
1044 u32 if_id, enum hws_access_type phy_access,
1045 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
1046 u32 data_value, enum hws_operation oper_type)
1047{
1048 u32 addr_low = 0x3f & reg_addr;
1049 u32 addr_hi = ((0xc0 & reg_addr) >> 6);
1050 u32 data_p1 =
1051 (oper_type << 30) + (addr_hi << 28) + (phy_access << 27) +
1052 (phy_type << 26) + (phy_id << 22) + (addr_low << 16) +
1053 (data_value & 0xffff);
1054 u32 data_p2 = data_p1 + (1 << 31);
1055 u32 start_if, end_if;
1056 struct hws_topology_map *tm = ddr3_get_topology_map();
1057
1058 CHECK_STATUS(ddr3_tip_if_write
1059 (dev_num, interface_access, if_id, PHY_REG_FILE_ACCESS,
1060 data_p1, MASK_ALL_BITS));
1061 CHECK_STATUS(ddr3_tip_if_write
1062 (dev_num, interface_access, if_id, PHY_REG_FILE_ACCESS,
1063 data_p2, MASK_ALL_BITS));
1064
1065 if (interface_access == ACCESS_TYPE_UNICAST) {
1066 start_if = if_id;
1067 end_if = if_id;
1068 } else {
1069 start_if = 0;
1070 end_if = MAX_INTERFACE_NUM - 1;
1071 }
1072
1073 /* polling for read/write execution done */
1074 for (if_id = start_if; if_id <= end_if; if_id++) {
1075 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1076 CHECK_STATUS(is_bus_access_done
1077 (dev_num, if_id, PHY_REG_FILE_ACCESS, 31));
1078 }
1079
1080 return MV_OK;
1081}
1082
1083/*
1084 * Check bus access done
1085 */
1086static int is_bus_access_done(u32 dev_num, u32 if_id, u32 dunit_reg_adrr,
1087 u32 bit)
1088{
1089 u32 rd_data = 1;
1090 u32 cnt = 0;
1091 u32 data_read[MAX_INTERFACE_NUM];
1092
1093 CHECK_STATUS(ddr3_tip_if_read
1094 (dev_num, ACCESS_TYPE_UNICAST, if_id, dunit_reg_adrr,
1095 data_read, MASK_ALL_BITS));
1096 rd_data = data_read[if_id];
1097 rd_data &= (1 << bit);
1098
1099 while (rd_data != 0) {
1100 if (cnt++ >= MAX_POLLING_ITERATIONS)
1101 break;
1102
1103 CHECK_STATUS(ddr3_tip_if_read
1104 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1105 dunit_reg_adrr, data_read, MASK_ALL_BITS));
1106 rd_data = data_read[if_id];
1107 rd_data &= (1 << bit);
1108 }
1109
1110 if (cnt < MAX_POLLING_ITERATIONS)
1111 return MV_OK;
1112 else
1113 return MV_FAIL;
1114}
1115
1116/*
1117 * Phy read-modify-write
1118 */
1119int ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type,
1120 u32 interface_id, u32 phy_id,
1121 enum hws_ddr_phy phy_type, u32 reg_addr,
1122 u32 data_value, u32 reg_mask)
1123{
1124 u32 data_val = 0, if_id, start_if, end_if;
1125 struct hws_topology_map *tm = ddr3_get_topology_map();
1126
1127 if (access_type == ACCESS_TYPE_MULTICAST) {
1128 start_if = 0;
1129 end_if = MAX_INTERFACE_NUM - 1;
1130 } else {
1131 start_if = interface_id;
1132 end_if = interface_id;
1133 }
1134
1135 for (if_id = start_if; if_id <= end_if; if_id++) {
1136 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1137 CHECK_STATUS(ddr3_tip_bus_read
1138 (dev_num, if_id, ACCESS_TYPE_UNICAST, phy_id,
1139 phy_type, reg_addr, &data_val));
1140 data_value = (data_val & (~reg_mask)) | (data_value & reg_mask);
1141 CHECK_STATUS(ddr3_tip_bus_write
1142 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1143 ACCESS_TYPE_UNICAST, phy_id, phy_type, reg_addr,
1144 data_value));
1145 }
1146
1147 return MV_OK;
1148}
1149
1150/*
1151 * ADLL Calibration
1152 */
1153int adll_calibration(u32 dev_num, enum hws_access_type access_type,
1154 u32 if_id, enum hws_ddr_freq frequency)
1155{
1156 struct hws_tip_freq_config_info freq_config_info;
1157 u32 bus_cnt = 0;
1158 struct hws_topology_map *tm = ddr3_get_topology_map();
1159
1160 /* Reset Diver_b assert -> de-assert */
1161 CHECK_STATUS(ddr3_tip_if_write
1162 (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG,
1163 0, 0x10000000));
1164 mdelay(10);
1165 CHECK_STATUS(ddr3_tip_if_write
1166 (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG,
1167 0x10000000, 0x10000000));
1168
1169 if (config_func_info[dev_num].tip_get_freq_config_info_func != NULL) {
1170 CHECK_STATUS(config_func_info[dev_num].
1171 tip_get_freq_config_info_func((u8)dev_num, frequency,
1172 &freq_config_info));
1173 } else {
1174 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1175 ("tip_get_freq_config_info_func is NULL"));
1176 return MV_NOT_INITIALIZED;
1177 }
1178
1179 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) {
1180 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
1181 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1182 (dev_num, access_type, if_id, bus_cnt,
1183 DDR_PHY_DATA, BW_PHY_REG,
1184 freq_config_info.bw_per_freq << 8, 0x700));
1185 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1186 (dev_num, access_type, if_id, bus_cnt,
1187 DDR_PHY_DATA, RATE_PHY_REG,
1188 freq_config_info.rate_per_freq, 0x7));
1189 }
1190
1191 /* DUnit to Phy drive post edge, ADLL reset assert de-assert */
1192 CHECK_STATUS(ddr3_tip_if_write
1193 (dev_num, access_type, if_id, DRAM_PHY_CONFIGURATION,
1194 0, (0x80000000 | 0x40000000)));
1195 mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ]));
1196 CHECK_STATUS(ddr3_tip_if_write
1197 (dev_num, access_type, if_id, DRAM_PHY_CONFIGURATION,
1198 (0x80000000 | 0x40000000), (0x80000000 | 0x40000000)));
1199
1200 /* polling for ADLL Done */
1201 if (ddr3_tip_if_polling(dev_num, access_type, if_id,
1202 0x3ff03ff, 0x3ff03ff, PHY_LOCK_STATUS_REG,
1203 MAX_POLLING_ITERATIONS) != MV_OK) {
1204 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1205 ("Freq_set: DDR3 poll failed(1)"));
1206 }
1207
1208 /* pup data_pup reset assert-> deassert */
1209 CHECK_STATUS(ddr3_tip_if_write
1210 (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG,
1211 0, 0x60000000));
1212 mdelay(10);
1213 CHECK_STATUS(ddr3_tip_if_write
1214 (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG,
1215 0x60000000, 0x60000000));
1216
1217 return MV_OK;
1218}
1219
1220int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
1221 u32 if_id, enum hws_ddr_freq frequency)
1222{
1223 u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0,
1224 bus_cnt = 0, t_hclk = 0, t_wr = 0,
1225 refresh_interval_cnt = 0, cnt_id;
1226 u32 t_refi = 0, end_if, start_if;
1227 u32 bus_index = 0;
1228 int is_dll_off = 0;
1229 enum hws_speed_bin speed_bin_index = 0;
1230 struct hws_tip_freq_config_info freq_config_info;
1231 enum hws_result *flow_result = training_result[training_stage];
1232 u32 adll_tap = 0;
1233 u32 cs_mask[MAX_INTERFACE_NUM];
1234 struct hws_topology_map *tm = ddr3_get_topology_map();
1235
1236 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
1237 ("dev %d access %d IF %d freq %d\n", dev_num,
1238 access_type, if_id, frequency));
1239
1240 if (frequency == DDR_FREQ_LOW_FREQ)
1241 is_dll_off = 1;
1242 if (access_type == ACCESS_TYPE_MULTICAST) {
1243 start_if = 0;
1244 end_if = MAX_INTERFACE_NUM - 1;
1245 } else {
1246 start_if = if_id;
1247 end_if = if_id;
1248 }
1249
1250 /* calculate interface cs mask - Oferb 4/11 */
1251 /* speed bin can be different for each interface */
1252 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1253 /* cs enable is active low */
1254 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1255 cs_mask[if_id] = CS_BIT_MASK;
1256 training_result[training_stage][if_id] = TEST_SUCCESS;
1257 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs,
1258 &cs_mask[if_id]);
1259 }
1260
1261 /* speed bin can be different for each interface */
1262 /*
1263 * moti b - need to remove the loop for multicas access functions
1264 * and loop the unicast access functions
1265 */
1266 for (if_id = start_if; if_id <= end_if; if_id++) {
1267 if (IS_ACTIVE(tm->if_act_mask, if_id) == 0)
1268 continue;
1269
1270 flow_result[if_id] = TEST_SUCCESS;
1271 speed_bin_index =
1272 tm->interface_params[if_id].speed_bin_index;
1273 if (tm->interface_params[if_id].memory_freq ==
1274 frequency) {
1275 cl_value =
1276 tm->interface_params[if_id].cas_l;
1277 cwl_value =
1278 tm->interface_params[if_id].cas_wl;
1279 } else {
1280 cl_value =
1281 cas_latency_table[speed_bin_index].cl_val[frequency];
1282 cwl_value =
1283 cas_write_latency_table[speed_bin_index].
1284 cl_val[frequency];
1285 }
1286
1287 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
1288 ("Freq_set dev 0x%x access 0x%x if 0x%x freq 0x%x speed %d:\n\t",
1289 dev_num, access_type, if_id,
1290 frequency, speed_bin_index));
1291
1292 for (cnt_id = 0; cnt_id < DDR_FREQ_LIMIT; cnt_id++) {
1293 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
1294 ("%d ",
1295 cas_latency_table[speed_bin_index].
1296 cl_val[cnt_id]));
1297 }
1298
1299 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("\n"));
1300 mem_mask = 0;
1301 for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES();
1302 bus_index++) {
1303 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
1304 mem_mask |=
1305 tm->interface_params[if_id].
1306 as_bus_params[bus_index].mirror_enable_bitmask;
1307 }
1308
1309 if (mem_mask != 0) {
1310 /* motib redundant in KW28 */
1311 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1312 if_id,
1313 CS_ENABLE_REG, 0, 0x8));
1314 }
1315
1316 /* dll state after exiting SR */
1317 if (is_dll_off == 1) {
1318 CHECK_STATUS(ddr3_tip_if_write
1319 (dev_num, access_type, if_id,
1320 DFS_REG, 0x1, 0x1));
1321 } else {
1322 CHECK_STATUS(ddr3_tip_if_write
1323 (dev_num, access_type, if_id,
1324 DFS_REG, 0, 0x1));
1325 }
1326
1327 CHECK_STATUS(ddr3_tip_if_write
1328 (dev_num, access_type, if_id,
1329 DUNIT_MMASK_REG, 0, 0x1));
1330 /* DFS - block transactions */
1331 CHECK_STATUS(ddr3_tip_if_write
1332 (dev_num, access_type, if_id,
1333 DFS_REG, 0x2, 0x2));
1334
1335 /* disable ODT in case of dll off */
1336 if (is_dll_off == 1) {
1337 CHECK_STATUS(ddr3_tip_if_write
1338 (dev_num, access_type, if_id,
1339 0x1874, 0, 0x244));
1340 CHECK_STATUS(ddr3_tip_if_write
1341 (dev_num, access_type, if_id,
1342 0x1884, 0, 0x244));
1343 CHECK_STATUS(ddr3_tip_if_write
1344 (dev_num, access_type, if_id,
1345 0x1894, 0, 0x244));
1346 CHECK_STATUS(ddr3_tip_if_write
1347 (dev_num, access_type, if_id,
1348 0x18a4, 0, 0x244));
1349 }
1350
1351 /* DFS - Enter Self-Refresh */
1352 CHECK_STATUS(ddr3_tip_if_write
1353 (dev_num, access_type, if_id, DFS_REG, 0x4,
1354 0x4));
1355 /* polling on self refresh entry */
1356 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST,
1357 if_id, 0x8, 0x8, DFS_REG,
1358 MAX_POLLING_ITERATIONS) != MV_OK) {
1359 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1360 ("Freq_set: DDR3 poll failed on SR entry\n"));
1361 }
1362
1363 /* PLL configuration */
1364 if (config_func_info[dev_num].tip_set_freq_divider_func != NULL) {
1365 config_func_info[dev_num].
1366 tip_set_freq_divider_func(dev_num, if_id,
1367 frequency);
1368 }
1369
1370 /* PLL configuration End */
1371
1372 /* adjust t_refi to new frequency */
1373 t_refi = (tm->interface_params[if_id].interface_temp ==
1374 HWS_TEMP_HIGH) ? TREFI_LOW : TREFI_HIGH;
1375 t_refi *= 1000; /*psec */
1376
1377 /* HCLK in[ps] */
1378 t_hclk = MEGA / (freq_val[frequency] / 2);
1379 refresh_interval_cnt = t_refi / t_hclk; /* no units */
1380 val = 0x4000 | refresh_interval_cnt;
1381 CHECK_STATUS(ddr3_tip_if_write
1382 (dev_num, access_type, if_id,
1383 SDRAM_CONFIGURATION_REG, val, 0x7fff));
1384
1385 /* DFS - CL/CWL/WR parameters after exiting SR */
1386 CHECK_STATUS(ddr3_tip_if_write
1387 (dev_num, access_type, if_id, DFS_REG,
1388 (cl_mask_table[cl_value] << 8), 0xf00));
1389 CHECK_STATUS(ddr3_tip_if_write
1390 (dev_num, access_type, if_id, DFS_REG,
1391 (cwl_mask_table[cwl_value] << 12), 0x7000));
1392 t_wr = speed_bin_table(speed_bin_index, SPEED_BIN_TWR);
1393 t_wr = (t_wr / 1000);
1394 CHECK_STATUS(ddr3_tip_if_write
1395 (dev_num, access_type, if_id, DFS_REG,
1396 (twr_mask_table[t_wr + 1] << 16), 0x70000));
1397
1398 /* Restore original RTT values if returning from DLL OFF mode */
1399 if (is_dll_off == 1) {
1400 CHECK_STATUS(ddr3_tip_if_write
1401 (dev_num, access_type, if_id, 0x1874,
1402 g_dic | g_rtt_nom, 0x266));
1403 CHECK_STATUS(ddr3_tip_if_write
1404 (dev_num, access_type, if_id, 0x1884,
1405 g_dic | g_rtt_nom, 0x266));
1406 CHECK_STATUS(ddr3_tip_if_write
1407 (dev_num, access_type, if_id, 0x1894,
1408 g_dic | g_rtt_nom, 0x266));
1409 CHECK_STATUS(ddr3_tip_if_write
1410 (dev_num, access_type, if_id, 0x18a4,
1411 g_dic | g_rtt_nom, 0x266));
1412 }
1413
1414 /* Reset Diver_b assert -> de-assert */
1415 CHECK_STATUS(ddr3_tip_if_write
1416 (dev_num, access_type, if_id,
1417 SDRAM_CONFIGURATION_REG, 0, 0x10000000));
1418 mdelay(10);
1419 CHECK_STATUS(ddr3_tip_if_write
1420 (dev_num, access_type, if_id,
1421 SDRAM_CONFIGURATION_REG, 0x10000000, 0x10000000));
1422
1423 /* Adll configuration function of process and Frequency */
1424 if (config_func_info[dev_num].tip_get_freq_config_info_func != NULL) {
1425 CHECK_STATUS(config_func_info[dev_num].
1426 tip_get_freq_config_info_func(dev_num, frequency,
1427 &freq_config_info));
1428 }
1429 /* TBD check milo5 using device ID ? */
1430 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES();
1431 bus_cnt++) {
1432 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
1433 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1434 (dev_num, ACCESS_TYPE_UNICAST,
1435 if_id, bus_cnt, DDR_PHY_DATA,
1436 0x92,
1437 freq_config_info.
1438 bw_per_freq << 8
1439 /*freq_mask[dev_num][frequency] << 8 */
1440 , 0x700));
1441 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1442 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1443 bus_cnt, DDR_PHY_DATA, 0x94,
1444 freq_config_info.rate_per_freq, 0x7));
1445 }
1446
1447 /* DUnit to Phy drive post edge, ADLL reset assert de-assert */
1448 CHECK_STATUS(ddr3_tip_if_write
1449 (dev_num, access_type, if_id,
1450 DRAM_PHY_CONFIGURATION, 0,
1451 (0x80000000 | 0x40000000)));
1452 mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ]));
1453 CHECK_STATUS(ddr3_tip_if_write
1454 (dev_num, access_type, if_id,
1455 DRAM_PHY_CONFIGURATION, (0x80000000 | 0x40000000),
1456 (0x80000000 | 0x40000000)));
1457
1458 /* polling for ADLL Done */
1459 if (ddr3_tip_if_polling
1460 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x3ff03ff,
1461 0x3ff03ff, PHY_LOCK_STATUS_REG,
1462 MAX_POLLING_ITERATIONS) != MV_OK) {
1463 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1464 ("Freq_set: DDR3 poll failed(1)\n"));
1465 }
1466
1467 /* pup data_pup reset assert-> deassert */
1468 CHECK_STATUS(ddr3_tip_if_write
1469 (dev_num, access_type, if_id,
1470 SDRAM_CONFIGURATION_REG, 0, 0x60000000));
1471 mdelay(10);
1472 CHECK_STATUS(ddr3_tip_if_write
1473 (dev_num, access_type, if_id,
1474 SDRAM_CONFIGURATION_REG, 0x60000000, 0x60000000));
1475
1476 /* Set proper timing params before existing Self-Refresh */
1477 ddr3_tip_set_timing(dev_num, access_type, if_id, frequency);
1478 if (delay_enable != 0) {
1479 adll_tap = MEGA / (freq_val[frequency] * 64);
1480 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
1481 }
1482
1483 /* Exit SR */
1484 CHECK_STATUS(ddr3_tip_if_write
1485 (dev_num, access_type, if_id, DFS_REG, 0,
1486 0x4));
1487 if (ddr3_tip_if_polling
1488 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x8, DFS_REG,
1489 MAX_POLLING_ITERATIONS) != MV_OK) {
1490 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1491 ("Freq_set: DDR3 poll failed(2)"));
1492 }
1493
1494 /* Refresh Command */
1495 CHECK_STATUS(ddr3_tip_if_write
1496 (dev_num, access_type, if_id,
1497 SDRAM_OPERATION_REG, 0x2, 0xf1f));
1498 if (ddr3_tip_if_polling
1499 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f,
1500 SDRAM_OPERATION_REG, MAX_POLLING_ITERATIONS) != MV_OK) {
1501 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1502 ("Freq_set: DDR3 poll failed(3)"));
1503 }
1504
1505 /* Release DFS Block */
1506 CHECK_STATUS(ddr3_tip_if_write
1507 (dev_num, access_type, if_id, DFS_REG, 0,
1508 0x2));
1509 /* Controller to MBUS Retry - normal */
1510 CHECK_STATUS(ddr3_tip_if_write
1511 (dev_num, access_type, if_id, DUNIT_MMASK_REG,
1512 0x1, 0x1));
1513
1514 /* MRO: Burst Length 8, CL , Auto_precharge 0x16cc */
1515 val =
1516 ((cl_mask_table[cl_value] & 0x1) << 2) |
1517 ((cl_mask_table[cl_value] & 0xe) << 3);
1518 CHECK_STATUS(ddr3_tip_if_write
1519 (dev_num, access_type, if_id, MR0_REG,
1520 val, (0x7 << 4) | (1 << 2)));
1521 /* MR2: CWL = 10 , Auto Self-Refresh - disable */
1522 val = (cwl_mask_table[cwl_value] << 3);
1523 /*
1524 * nklein 24.10.13 - should not be here - leave value as set in
1525 * the init configuration val |= (1 << 9);
1526 * val |= ((tm->interface_params[if_id].
1527 * interface_temp == HWS_TEMP_HIGH) ? (1 << 7) : 0);
1528 */
1529 /* nklein 24.10.13 - see above comment */
1530 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1531 if_id, MR2_REG,
1532 val, (0x7 << 3)));
1533
1534 /* ODT TIMING */
1535 val = ((cl_value - cwl_value + 1) << 4) |
1536 ((cl_value - cwl_value + 6) << 8) |
1537 ((cl_value - 1) << 12) | ((cl_value + 6) << 16);
1538 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1539 if_id, ODT_TIMING_LOW,
1540 val, 0xffff0));
1541 val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
1542 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1543 if_id, ODT_TIMING_HI_REG,
1544 val, 0xffff));
1545
1546 /* ODT Active */
1547 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1548 if_id,
1549 DUNIT_ODT_CONTROL_REG,
1550 0xf, 0xf));
1551
1552 /* re-write CL */
1553 val = ((cl_mask_table[cl_value] & 0x1) << 2) |
1554 ((cl_mask_table[cl_value] & 0xe) << 3);
1555 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1556 0, MR0_REG, val,
1557 (0x7 << 4) | (1 << 2)));
1558
1559 /* re-write CWL */
1560 val = (cwl_mask_table[cwl_value] << 3);
1561 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MRS2_CMD,
1562 val, (0x7 << 3)));
1563 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1564 0, MR2_REG, val, (0x7 << 3)));
1565
1566 if (mem_mask != 0) {
1567 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1568 if_id,
1569 CS_ENABLE_REG,
1570 1 << 3, 0x8));
1571 }
1572 }
1573
1574 return MV_OK;
1575}
1576
1577/*
1578 * Set ODT values
1579 */
1580static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
1581 u32 if_id, u32 cl_value, u32 cwl_value)
1582{
1583 /* ODT TIMING */
1584 u32 val = (cl_value - cwl_value + 6);
1585
1586 val = ((cl_value - cwl_value + 1) << 4) | ((val & 0xf) << 8) |
1587 (((cl_value - 1) & 0xf) << 12) |
1588 (((cl_value + 6) & 0xf) << 16) | (((val & 0x10) >> 4) << 21);
1589 val |= (((cl_value - 1) >> 4) << 22) | (((cl_value + 6) >> 4) << 23);
1590
1591 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1592 ODT_TIMING_LOW, val, 0xffff0));
1593 val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
1594 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1595 ODT_TIMING_HI_REG, val, 0xffff));
1596 if (odt_additional == 1) {
1597 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1598 if_id,
1599 SDRAM_ODT_CONTROL_HIGH_REG,
1600 0xf, 0xf));
1601 }
1602
1603 /* ODT Active */
1604 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1605 DUNIT_ODT_CONTROL_REG, 0xf, 0xf));
1606
1607 return MV_OK;
1608}
1609
1610/*
1611 * Set Timing values for training
1612 */
1613static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
1614 u32 if_id, enum hws_ddr_freq frequency)
1615{
1616 u32 t_ckclk = 0, t_ras = 0;
1617 u32 t_rcd = 0, t_rp = 0, t_wr = 0, t_wtr = 0, t_rrd = 0, t_rtp = 0,
1618 t_rfc = 0, t_mod = 0;
1619 u32 val = 0, page_size = 0;
1620 enum hws_speed_bin speed_bin_index;
1621 enum hws_mem_size memory_size = MEM_2G;
1622 struct hws_topology_map *tm = ddr3_get_topology_map();
1623
1624 speed_bin_index = tm->interface_params[if_id].speed_bin_index;
1625 memory_size = tm->interface_params[if_id].memory_size;
1626 page_size =
1627 (tm->interface_params[if_id].bus_width ==
1628 BUS_WIDTH_8) ? page_param[memory_size].
1629 page_size_8bit : page_param[memory_size].page_size_16bit;
1630 t_ckclk = (MEGA / freq_val[frequency]);
1631 t_rrd = (page_size == 1) ? speed_bin_table(speed_bin_index,
1632 SPEED_BIN_TRRD1K) :
1633 speed_bin_table(speed_bin_index, SPEED_BIN_TRRD2K);
1634 t_rrd = GET_MAX_VALUE(t_ckclk * 4, t_rrd);
1635 t_rtp = GET_MAX_VALUE(t_ckclk * 4, speed_bin_table(speed_bin_index,
1636 SPEED_BIN_TRTP));
1637 t_wtr = GET_MAX_VALUE(t_ckclk * 4, speed_bin_table(speed_bin_index,
1638 SPEED_BIN_TWTR));
1639 t_ras = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
1640 SPEED_BIN_TRAS),
1641 t_ckclk);
1642 t_rcd = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
1643 SPEED_BIN_TRCD),
1644 t_ckclk);
1645 t_rp = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
1646 SPEED_BIN_TRP),
1647 t_ckclk);
1648 t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
1649 SPEED_BIN_TWR),
1650 t_ckclk);
1651 t_wtr = TIME_2_CLOCK_CYCLES(t_wtr, t_ckclk);
1652 t_rrd = TIME_2_CLOCK_CYCLES(t_rrd, t_ckclk);
1653 t_rtp = TIME_2_CLOCK_CYCLES(t_rtp, t_ckclk);
1654 t_rfc = TIME_2_CLOCK_CYCLES(rfc_table[memory_size] * 1000, t_ckclk);
1655 t_mod = GET_MAX_VALUE(t_ckclk * 24, 15000);
1656 t_mod = TIME_2_CLOCK_CYCLES(t_mod, t_ckclk);
1657
1658 /* SDRAM Timing Low */
1659 val = (t_ras & 0xf) | (t_rcd << 4) | (t_rp << 8) | (t_wr << 12) |
1660 (t_wtr << 16) | (((t_ras & 0x30) >> 4) << 20) | (t_rrd << 24) |
1661 (t_rtp << 28);
1662 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1663 SDRAM_TIMING_LOW_REG, val, 0xff3fffff));
1664
1665 /* SDRAM Timing High */
1666 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1667 SDRAM_TIMING_HIGH_REG,
1668 t_rfc & 0x7f, 0x7f));
1669 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1670 SDRAM_TIMING_HIGH_REG,
1671 0x180, 0x180));
1672 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1673 SDRAM_TIMING_HIGH_REG,
1674 0x600, 0x600));
1675 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1676 SDRAM_TIMING_HIGH_REG,
1677 0x1800, 0xf800));
1678 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1679 SDRAM_TIMING_HIGH_REG,
1680 ((t_rfc & 0x380) >> 7) << 16, 0x70000));
1681 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1682 SDRAM_TIMING_HIGH_REG, 0,
1683 0x380000));
1684 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1685 SDRAM_TIMING_HIGH_REG,
1686 (t_mod & 0xf) << 25, 0x1e00000));
1687 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1688 SDRAM_TIMING_HIGH_REG,
1689 (t_mod >> 4) << 30, 0xc0000000));
1690 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1691 SDRAM_TIMING_HIGH_REG,
1692 0x16000000, 0x1e000000));
1693 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1694 SDRAM_TIMING_HIGH_REG,
1695 0x40000000, 0xc0000000));
1696
1697 return MV_OK;
1698}
1699
1700/*
1701 * Mode Read
1702 */
1703int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info)
1704{
1705 u32 ret;
1706
1707 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1708 MR0_REG, mode_info->reg_mr0, MASK_ALL_BITS);
1709 if (ret != MV_OK)
1710 return ret;
1711
1712 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1713 MR1_REG, mode_info->reg_mr1, MASK_ALL_BITS);
1714 if (ret != MV_OK)
1715 return ret;
1716
1717 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1718 MR2_REG, mode_info->reg_mr2, MASK_ALL_BITS);
1719 if (ret != MV_OK)
1720 return ret;
1721
1722 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1723 MR3_REG, mode_info->reg_mr2, MASK_ALL_BITS);
1724 if (ret != MV_OK)
1725 return ret;
1726
1727 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1728 READ_DATA_SAMPLE_DELAY, mode_info->read_data_sample,
1729 MASK_ALL_BITS);
1730 if (ret != MV_OK)
1731 return ret;
1732
1733 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1734 READ_DATA_READY_DELAY, mode_info->read_data_ready,
1735 MASK_ALL_BITS);
1736 if (ret != MV_OK)
1737 return ret;
1738
1739 return MV_OK;
1740}
1741
1742/*
1743 * Get first active IF
1744 */
1745int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask,
1746 u32 *interface_id)
1747{
1748 u32 if_id;
1749 struct hws_topology_map *tm = ddr3_get_topology_map();
1750
1751 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1752 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1753 if (interface_mask & (1 << if_id)) {
1754 *interface_id = if_id;
1755 break;
1756 }
1757 }
1758
1759 return MV_OK;
1760}
1761
1762/*
1763 * Write CS Result
1764 */
1765int ddr3_tip_write_cs_result(u32 dev_num, u32 offset)
1766{
1767 u32 if_id, bus_num, cs_bitmask, data_val, cs_num;
1768 struct hws_topology_map *tm = ddr3_get_topology_map();
1769
1770 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1771 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1772 for (bus_num = 0; bus_num < tm->num_of_bus_per_interface;
1773 bus_num++) {
1774 VALIDATE_ACTIVE(tm->bus_act_mask, bus_num);
1775 cs_bitmask =
1776 tm->interface_params[if_id].
1777 as_bus_params[bus_num].cs_bitmask;
1778 if (cs_bitmask != effective_cs) {
1779 cs_num = GET_CS_FROM_MASK(cs_bitmask);
1780 ddr3_tip_bus_read(dev_num, if_id,
1781 ACCESS_TYPE_UNICAST, bus_num,
1782 DDR_PHY_DATA,
1783 offset +
1784 CS_REG_VALUE(effective_cs),
1785 &data_val);
1786 ddr3_tip_bus_write(dev_num,
1787 ACCESS_TYPE_UNICAST,
1788 if_id,
1789 ACCESS_TYPE_UNICAST,
1790 bus_num, DDR_PHY_DATA,
1791 offset +
1792 CS_REG_VALUE(cs_num),
1793 data_val);
1794 }
1795 }
1796 }
1797
1798 return MV_OK;
1799}
1800
1801/*
1802 * Write MRS
1803 */
1804int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, u32 cmd,
1805 u32 data, u32 mask)
1806{
1807 u32 if_id, reg;
1808 struct hws_topology_map *tm = ddr3_get_topology_map();
1809
1810 reg = (cmd == MRS1_CMD) ? MR1_REG : MR2_REG;
1811 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1812 PARAM_NOT_CARE, reg, data, mask));
1813 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1814 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1815 CHECK_STATUS(ddr3_tip_if_write
1816 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1817 SDRAM_OPERATION_REG,
1818 (cs_mask_arr[if_id] << 8) | cmd, 0xf1f));
1819 }
1820
1821 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1822 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1823 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0,
1824 0x1f, SDRAM_OPERATION_REG,
1825 MAX_POLLING_ITERATIONS) != MV_OK) {
1826 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1827 ("write_mrs_cmd: Poll cmd fail"));
1828 }
1829 }
1830
1831 return MV_OK;
1832}
1833
1834/*
1835 * Reset XSB Read FIFO
1836 */
1837int ddr3_tip_reset_fifo_ptr(u32 dev_num)
1838{
1839 u32 if_id = 0;
1840
1841 /* Configure PHY reset value to 0 in order to "clean" the FIFO */
1842 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1843 if_id, 0x15c8, 0, 0xff000000));
1844 /*
1845 * Move PHY to RL mode (only in RL mode the PHY overrides FIFO values
1846 * during FIFO reset)
1847 */
1848 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1849 if_id, TRAINING_SW_2_REG,
1850 0x1, 0x9));
1851 /* In order that above configuration will influence the PHY */
1852 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1853 if_id, 0x15b0,
1854 0x80000000, 0x80000000));
1855 /* Reset read fifo assertion */
1856 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1857 if_id, 0x1400, 0, 0x40000000));
1858 /* Reset read fifo deassertion */
1859 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1860 if_id, 0x1400,
1861 0x40000000, 0x40000000));
1862 /* Move PHY back to functional mode */
1863 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1864 if_id, TRAINING_SW_2_REG,
1865 0x8, 0x9));
1866 /* Stop training machine */
1867 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1868 if_id, 0x15b4, 0x10000, 0x10000));
1869
1870 return MV_OK;
1871}
1872
1873/*
1874 * Reset Phy registers
1875 */
1876int ddr3_tip_ddr3_reset_phy_regs(u32 dev_num)
1877{
1878 u32 if_id, phy_id, cs;
1879 struct hws_topology_map *tm = ddr3_get_topology_map();
1880
1881 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1882 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1883 for (phy_id = 0; phy_id < tm->num_of_bus_per_interface;
1884 phy_id++) {
1885 VALIDATE_ACTIVE(tm->bus_act_mask, phy_id);
1886 CHECK_STATUS(ddr3_tip_bus_write
1887 (dev_num, ACCESS_TYPE_UNICAST,
1888 if_id, ACCESS_TYPE_UNICAST,
1889 phy_id, DDR_PHY_DATA,
1890 WL_PHY_REG +
1891 CS_REG_VALUE(effective_cs),
1892 phy_reg0_val));
1893 CHECK_STATUS(ddr3_tip_bus_write
1894 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1895 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1896 RL_PHY_REG + CS_REG_VALUE(effective_cs),
1897 phy_reg2_val));
1898 CHECK_STATUS(ddr3_tip_bus_write
1899 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1900 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1901 READ_CENTRALIZATION_PHY_REG +
1902 CS_REG_VALUE(effective_cs), phy_reg3_val));
1903 CHECK_STATUS(ddr3_tip_bus_write
1904 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1905 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1906 WRITE_CENTRALIZATION_PHY_REG +
1907 CS_REG_VALUE(effective_cs), phy_reg3_val));
1908 }
1909 }
1910
1911 /* Set Receiver Calibration value */
1912 for (cs = 0; cs < MAX_CS_NUM; cs++) {
1913 /* PHY register 0xdb bits[5:0] - configure to 63 */
1914 CHECK_STATUS(ddr3_tip_bus_write
1915 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1916 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1917 DDR_PHY_DATA, CSN_IOB_VREF_REG(cs), 63));
1918 }
1919
1920 return MV_OK;
1921}
1922
1923/*
1924 * Restore Dunit registers
1925 */
1926int ddr3_tip_restore_dunit_regs(u32 dev_num)
1927{
1928 u32 index_cnt;
1929
1930 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1931 PARAM_NOT_CARE, CALIB_MACHINE_CTRL_REG,
1932 0x1, 0x1));
1933 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1934 PARAM_NOT_CARE, CALIB_MACHINE_CTRL_REG,
1935 calibration_update_control << 3,
1936 0x3 << 3));
1937 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1938 PARAM_NOT_CARE,
1939 ODPG_WRITE_READ_MODE_ENABLE_REG,
1940 0xffff, MASK_ALL_BITS));
1941
1942 for (index_cnt = 0; index_cnt < ARRAY_SIZE(odpg_default_value);
1943 index_cnt++) {
1944 CHECK_STATUS(ddr3_tip_if_write
1945 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1946 odpg_default_value[index_cnt].reg_addr,
1947 odpg_default_value[index_cnt].reg_data,
1948 odpg_default_value[index_cnt].reg_mask));
1949 }
1950
1951 return MV_OK;
1952}
1953
1954/*
1955 * Auto tune main flow
1956 */
1957static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
1958{
1959 enum hws_ddr_freq freq = init_freq;
1960 struct init_cntr_param init_cntr_prm;
1961 int ret = MV_OK;
1962 u32 if_id;
1963 u32 max_cs = hws_ddr3_tip_max_cs_get();
1964 struct hws_topology_map *tm = ddr3_get_topology_map();
1965
1966#ifndef EXCLUDE_SWITCH_DEBUG
1967 if (debug_training == DEBUG_LEVEL_TRACE) {
1968 CHECK_STATUS(print_device_info((u8)dev_num));
1969 }
1970#endif
1971
1972 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
1973 CHECK_STATUS(ddr3_tip_ddr3_reset_phy_regs(dev_num));
1974 }
1975 /* Set to 0 after each loop to avoid illegal value may be used */
1976 effective_cs = 0;
1977
1978 freq = init_freq;
1979 if (is_pll_before_init != 0) {
1980 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
1981 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1982 config_func_info[dev_num].tip_set_freq_divider_func(
1983 (u8)dev_num, if_id, freq);
1984 }
1985 }
1986
1987 if (is_adll_calib_before_init != 0) {
1988 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
1989 ("with adll calib before init\n"));
1990 adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
1991 }
1992
1993 if (is_reg_dump != 0) {
1994 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
1995 ("Dump before init controller\n"));
1996 ddr3_tip_reg_dump(dev_num);
1997 }
1998
1999 if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) {
2000 training_stage = INIT_CONTROLLER;
2001 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2002 ("INIT_CONTROLLER_MASK_BIT\n"));
2003 init_cntr_prm.do_mrs_phy = 1;
2004 init_cntr_prm.is_ctrl64_bit = 0;
2005 init_cntr_prm.init_phy = 1;
2006 init_cntr_prm.msys_init = 0;
2007 ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm);
2008 if (is_reg_dump != 0)
2009 ddr3_tip_reg_dump(dev_num);
2010 if (ret != MV_OK) {
2011 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2012 ("hws_ddr3_tip_init_controller failure\n"));
2013 if (debug_mode == 0)
2014 return MV_FAIL;
2015 }
2016 }
2017
2018#ifdef STATIC_ALGO_SUPPORT
2019 if (mask_tune_func & STATIC_LEVELING_MASK_BIT) {
2020 training_stage = STATIC_LEVELING;
2021 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2022 ("STATIC_LEVELING_MASK_BIT\n"));
2023 ret = ddr3_tip_run_static_alg(dev_num, freq);
2024 if (is_reg_dump != 0)
2025 ddr3_tip_reg_dump(dev_num);
2026 if (ret != MV_OK) {
2027 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2028 ("ddr3_tip_run_static_alg failure\n"));
2029 if (debug_mode == 0)
2030 return MV_FAIL;
2031 }
2032 }
2033#endif
2034
2035 if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) {
2036 training_stage = SET_LOW_FREQ;
2037 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2038 ("SET_LOW_FREQ_MASK_BIT %d\n",
2039 freq_val[low_freq]));
2040 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2041 PARAM_NOT_CARE, low_freq);
2042 if (is_reg_dump != 0)
2043 ddr3_tip_reg_dump(dev_num);
2044 if (ret != MV_OK) {
2045 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2046 ("ddr3_tip_freq_set failure\n"));
2047 if (debug_mode == 0)
2048 return MV_FAIL;
2049 }
2050 }
2051
2052 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2053 if (mask_tune_func & LOAD_PATTERN_MASK_BIT) {
2054 training_stage = LOAD_PATTERN;
2055 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2056 ("LOAD_PATTERN_MASK_BIT #%d\n",
2057 effective_cs));
2058 ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2059 if (is_reg_dump != 0)
2060 ddr3_tip_reg_dump(dev_num);
2061 if (ret != MV_OK) {
2062 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2063 ("ddr3_tip_load_all_pattern_to_mem failure CS #%d\n",
2064 effective_cs));
2065 if (debug_mode == 0)
2066 return MV_FAIL;
2067 }
2068 }
2069 }
2070 /* Set to 0 after each loop to avoid illegal value may be used */
2071 effective_cs = 0;
2072
2073 if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {
2074 training_stage = SET_MEDIUM_FREQ;
2075 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2076 ("SET_MEDIUM_FREQ_MASK_BIT %d\n",
2077 freq_val[medium_freq]));
2078 ret =
2079 ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2080 PARAM_NOT_CARE, medium_freq);
2081 if (is_reg_dump != 0)
2082 ddr3_tip_reg_dump(dev_num);
2083 if (ret != MV_OK) {
2084 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2085 ("ddr3_tip_freq_set failure\n"));
2086 if (debug_mode == 0)
2087 return MV_FAIL;
2088 }
2089 }
2090
2091 if (mask_tune_func & WRITE_LEVELING_MASK_BIT) {
2092 training_stage = WRITE_LEVELING;
2093 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2094 ("WRITE_LEVELING_MASK_BIT\n"));
2095 if ((rl_mid_freq_wa == 0) || (freq_val[medium_freq] == 533)) {
2096 ret = ddr3_tip_dynamic_write_leveling(dev_num);
2097 } else {
2098 /* Use old WL */
2099 ret = ddr3_tip_legacy_dynamic_write_leveling(dev_num);
2100 }
2101
2102 if (is_reg_dump != 0)
2103 ddr3_tip_reg_dump(dev_num);
2104 if (ret != MV_OK) {
2105 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2106 ("ddr3_tip_dynamic_write_leveling failure\n"));
2107 if (debug_mode == 0)
2108 return MV_FAIL;
2109 }
2110 }
2111
2112 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2113 if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) {
2114 training_stage = LOAD_PATTERN_2;
2115 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2116 ("LOAD_PATTERN_2_MASK_BIT CS #%d\n",
2117 effective_cs));
2118 ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2119 if (is_reg_dump != 0)
2120 ddr3_tip_reg_dump(dev_num);
2121 if (ret != MV_OK) {
2122 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2123 ("ddr3_tip_load_all_pattern_to_mem failure CS #%d\n",
2124 effective_cs));
2125 if (debug_mode == 0)
2126 return MV_FAIL;
2127 }
2128 }
2129 }
2130 /* Set to 0 after each loop to avoid illegal value may be used */
2131 effective_cs = 0;
2132
2133 if (mask_tune_func & READ_LEVELING_MASK_BIT) {
2134 training_stage = READ_LEVELING;
2135 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2136 ("READ_LEVELING_MASK_BIT\n"));
2137 if ((rl_mid_freq_wa == 0) || (freq_val[medium_freq] == 533)) {
2138 ret = ddr3_tip_dynamic_read_leveling(dev_num, medium_freq);
2139 } else {
2140 /* Use old RL */
2141 ret = ddr3_tip_legacy_dynamic_read_leveling(dev_num);
2142 }
2143
2144 if (is_reg_dump != 0)
2145 ddr3_tip_reg_dump(dev_num);
2146 if (ret != MV_OK) {
2147 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2148 ("ddr3_tip_dynamic_read_leveling failure\n"));
2149 if (debug_mode == 0)
2150 return MV_FAIL;
2151 }
2152 }
2153
2154 if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) {
2155 training_stage = WRITE_LEVELING_SUPP;
2156 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2157 ("WRITE_LEVELING_SUPP_MASK_BIT\n"));
2158 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
2159 if (is_reg_dump != 0)
2160 ddr3_tip_reg_dump(dev_num);
2161 if (ret != MV_OK) {
2162 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2163 ("ddr3_tip_dynamic_write_leveling_supp failure\n"));
2164 if (debug_mode == 0)
2165 return MV_FAIL;
2166 }
2167 }
2168
2169 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2170 if (mask_tune_func & PBS_RX_MASK_BIT) {
2171 training_stage = PBS_RX;
2172 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2173 ("PBS_RX_MASK_BIT CS #%d\n",
2174 effective_cs));
2175 ret = ddr3_tip_pbs_rx(dev_num);
2176 if (is_reg_dump != 0)
2177 ddr3_tip_reg_dump(dev_num);
2178 if (ret != MV_OK) {
2179 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2180 ("ddr3_tip_pbs_rx failure CS #%d\n",
2181 effective_cs));
2182 if (debug_mode == 0)
2183 return MV_FAIL;
2184 }
2185 }
2186 }
2187
2188 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2189 if (mask_tune_func & PBS_TX_MASK_BIT) {
2190 training_stage = PBS_TX;
2191 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2192 ("PBS_TX_MASK_BIT CS #%d\n",
2193 effective_cs));
2194 ret = ddr3_tip_pbs_tx(dev_num);
2195 if (is_reg_dump != 0)
2196 ddr3_tip_reg_dump(dev_num);
2197 if (ret != MV_OK) {
2198 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2199 ("ddr3_tip_pbs_tx failure CS #%d\n",
2200 effective_cs));
2201 if (debug_mode == 0)
2202 return MV_FAIL;
2203 }
2204 }
2205 }
2206 /* Set to 0 after each loop to avoid illegal value may be used */
2207 effective_cs = 0;
2208
2209 if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) {
2210 training_stage = SET_TARGET_FREQ;
2211 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2212 ("SET_TARGET_FREQ_MASK_BIT %d\n",
2213 freq_val[tm->
2214 interface_params[first_active_if].
2215 memory_freq]));
2216 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2217 PARAM_NOT_CARE,
2218 tm->interface_params[first_active_if].
2219 memory_freq);
2220 if (is_reg_dump != 0)
2221 ddr3_tip_reg_dump(dev_num);
2222 if (ret != MV_OK) {
2223 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2224 ("ddr3_tip_freq_set failure\n"));
2225 if (debug_mode == 0)
2226 return MV_FAIL;
2227 }
2228 }
2229
2230 if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) {
2231 training_stage = WRITE_LEVELING_TF;
2232 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2233 ("WRITE_LEVELING_TF_MASK_BIT\n"));
2234 ret = ddr3_tip_dynamic_write_leveling(dev_num);
2235 if (is_reg_dump != 0)
2236 ddr3_tip_reg_dump(dev_num);
2237 if (ret != MV_OK) {
2238 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2239 ("ddr3_tip_dynamic_write_leveling TF failure\n"));
2240 if (debug_mode == 0)
2241 return MV_FAIL;
2242 }
2243 }
2244
2245 if (mask_tune_func & LOAD_PATTERN_HIGH_MASK_BIT) {
2246 training_stage = LOAD_PATTERN_HIGH;
2247 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("LOAD_PATTERN_HIGH\n"));
2248 ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2249 if (is_reg_dump != 0)
2250 ddr3_tip_reg_dump(dev_num);
2251 if (ret != MV_OK) {
2252 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2253 ("ddr3_tip_load_all_pattern_to_mem failure\n"));
2254 if (debug_mode == 0)
2255 return MV_FAIL;
2256 }
2257 }
2258
2259 if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {
2260 training_stage = READ_LEVELING_TF;
2261 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2262 ("READ_LEVELING_TF_MASK_BIT\n"));
2263 ret = ddr3_tip_dynamic_read_leveling(dev_num, tm->
2264 interface_params[first_active_if].
2265 memory_freq);
2266 if (is_reg_dump != 0)
2267 ddr3_tip_reg_dump(dev_num);
2268 if (ret != MV_OK) {
2269 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2270 ("ddr3_tip_dynamic_read_leveling TF failure\n"));
2271 if (debug_mode == 0)
2272 return MV_FAIL;
2273 }
2274 }
2275
2276 if (mask_tune_func & DM_PBS_TX_MASK_BIT) {
2277 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("DM_PBS_TX_MASK_BIT\n"));
2278 }
2279
2280 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2281 if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) {
2282 training_stage = VREF_CALIBRATION;
2283 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("VREF\n"));
2284 ret = ddr3_tip_vref(dev_num);
2285 if (is_reg_dump != 0) {
2286 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2287 ("VREF Dump\n"));
2288 ddr3_tip_reg_dump(dev_num);
2289 }
2290 if (ret != MV_OK) {
2291 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2292 ("ddr3_tip_vref failure\n"));
2293 if (debug_mode == 0)
2294 return MV_FAIL;
2295 }
2296 }
2297 }
2298 /* Set to 0 after each loop to avoid illegal value may be used */
2299 effective_cs = 0;
2300
2301 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2302 if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) {
2303 training_stage = CENTRALIZATION_RX;
2304 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2305 ("CENTRALIZATION_RX_MASK_BIT CS #%d\n",
2306 effective_cs));
2307 ret = ddr3_tip_centralization_rx(dev_num);
2308 if (is_reg_dump != 0)
2309 ddr3_tip_reg_dump(dev_num);
2310 if (ret != MV_OK) {
2311 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2312 ("ddr3_tip_centralization_rx failure CS #%d\n",
2313 effective_cs));
2314 if (debug_mode == 0)
2315 return MV_FAIL;
2316 }
2317 }
2318 }
2319 /* Set to 0 after each loop to avoid illegal value may be used */
2320 effective_cs = 0;
2321
2322 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2323 if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {
2324 training_stage = WRITE_LEVELING_SUPP_TF;
2325 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2326 ("WRITE_LEVELING_SUPP_TF_MASK_BIT CS #%d\n",
2327 effective_cs));
2328 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
2329 if (is_reg_dump != 0)
2330 ddr3_tip_reg_dump(dev_num);
2331 if (ret != MV_OK) {
2332 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2333 ("ddr3_tip_dynamic_write_leveling_supp TF failure CS #%d\n",
2334 effective_cs));
2335 if (debug_mode == 0)
2336 return MV_FAIL;
2337 }
2338 }
2339 }
2340 /* Set to 0 after each loop to avoid illegal value may be used */
2341 effective_cs = 0;
2342
2343 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2344 if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) {
2345 training_stage = CENTRALIZATION_TX;
2346 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2347 ("CENTRALIZATION_TX_MASK_BIT CS #%d\n",
2348 effective_cs));
2349 ret = ddr3_tip_centralization_tx(dev_num);
2350 if (is_reg_dump != 0)
2351 ddr3_tip_reg_dump(dev_num);
2352 if (ret != MV_OK) {
2353 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2354 ("ddr3_tip_centralization_tx failure CS #%d\n",
2355 effective_cs));
2356 if (debug_mode == 0)
2357 return MV_FAIL;
2358 }
2359 }
2360 }
2361 /* Set to 0 after each loop to avoid illegal value may be used */
2362 effective_cs = 0;
2363
2364 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("restore registers to default\n"));
2365 /* restore register values */
2366 CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
2367
2368 if (is_reg_dump != 0)
2369 ddr3_tip_reg_dump(dev_num);
2370
2371 return MV_OK;
2372}
2373
2374/*
2375 * DDR3 Dynamic training flow
2376 */
2377static int ddr3_tip_ddr3_auto_tune(u32 dev_num)
2378{
2379 u32 if_id, stage, ret;
2380 int is_if_fail = 0, is_auto_tune_fail = 0;
2381
2382 training_stage = INIT_CONTROLLER;
2383
2384 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2385 for (stage = 0; stage < MAX_STAGE_LIMIT; stage++)
2386 training_result[stage][if_id] = NO_TEST_DONE;
2387 }
2388
2389 ret = ddr3_tip_ddr3_training_main_flow(dev_num);
2390
2391 /* activate XSB test */
2392 if (xsb_validate_type != 0) {
2393 run_xsb_test(dev_num, xsb_validation_base_address, 1, 1,
2394 0x1024);
2395 }
2396
2397 if (is_reg_dump != 0)
2398 ddr3_tip_reg_dump(dev_num);
2399
2400 /* print log */
2401 CHECK_STATUS(ddr3_tip_print_log(dev_num, window_mem_addr));
2402
2403 if (ret != MV_OK) {
2404 CHECK_STATUS(ddr3_tip_print_stability_log(dev_num));
2405 }
2406
2407 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2408 is_if_fail = 0;
2409 for (stage = 0; stage < MAX_STAGE_LIMIT; stage++) {
2410 if (training_result[stage][if_id] == TEST_FAILED)
2411 is_if_fail = 1;
2412 }
2413 if (is_if_fail == 1) {
2414 is_auto_tune_fail = 1;
2415 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2416 ("Auto Tune failed for IF %d\n",
2417 if_id));
2418 }
2419 }
2420
2421 if ((ret == MV_FAIL) || (is_auto_tune_fail == 1))
2422 return MV_FAIL;
2423 else
2424 return MV_OK;
2425}
2426
2427/*
2428 * Enable init sequence
2429 */
2430int ddr3_tip_enable_init_sequence(u32 dev_num)
2431{
2432 int is_fail = 0;
2433 u32 if_id = 0, mem_mask = 0, bus_index = 0;
2434 struct hws_topology_map *tm = ddr3_get_topology_map();
2435
2436 /* Enable init sequence */
2437 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, 0,
2438 SDRAM_INIT_CONTROL_REG, 0x1, 0x1));
2439
2440 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2441 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
2442
2443 if (ddr3_tip_if_polling
2444 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1,
2445 SDRAM_INIT_CONTROL_REG,
2446 MAX_POLLING_ITERATIONS) != MV_OK) {
2447 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2448 ("polling failed IF %d\n",
2449 if_id));
2450 is_fail = 1;
2451 continue;
2452 }
2453
2454 mem_mask = 0;
2455 for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES();
2456 bus_index++) {
2457 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
2458 mem_mask |=
2459 tm->interface_params[if_id].
2460 as_bus_params[bus_index].mirror_enable_bitmask;
2461 }
2462
2463 if (mem_mask != 0) {
2464 /* Disable Multi CS */
2465 CHECK_STATUS(ddr3_tip_if_write
2466 (dev_num, ACCESS_TYPE_MULTICAST,
2467 if_id, CS_ENABLE_REG, 1 << 3,
2468 1 << 3));
2469 }
2470 }
2471
2472 return (is_fail == 0) ? MV_OK : MV_FAIL;
2473}
2474
2475int ddr3_tip_register_dq_table(u32 dev_num, u32 *table)
2476{
2477 dq_map_table = table;
2478
2479 return MV_OK;
2480}
2481
2482/*
2483 * Check if pup search is locked
2484 */
2485int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode)
2486{
2487 u32 bit_start = 0, bit_end = 0, bit_id;
2488
2489 if (read_mode == RESULT_PER_BIT) {
2490 bit_start = 0;
2491 bit_end = BUS_WIDTH_IN_BITS - 1;
2492 } else {
2493 bit_start = 0;
2494 bit_end = 0;
2495 }
2496
2497 for (bit_id = bit_start; bit_id <= bit_end; bit_id++) {
2498 if (GET_LOCK_RESULT(pup_buf[bit_id]) == 0)
2499 return 0;
2500 }
2501
2502 return 1;
2503}
2504
2505/*
2506 * Get minimum buffer value
2507 */
2508u8 ddr3_tip_get_buf_min(u8 *buf_ptr)
2509{
2510 u8 min_val = 0xff;
2511 u8 cnt = 0;
2512
2513 for (cnt = 0; cnt < BUS_WIDTH_IN_BITS; cnt++) {
2514 if (buf_ptr[cnt] < min_val)
2515 min_val = buf_ptr[cnt];
2516 }
2517
2518 return min_val;
2519}
2520
2521/*
2522 * Get maximum buffer value
2523 */
2524u8 ddr3_tip_get_buf_max(u8 *buf_ptr)
2525{
2526 u8 max_val = 0;
2527 u8 cnt = 0;
2528
2529 for (cnt = 0; cnt < BUS_WIDTH_IN_BITS; cnt++) {
2530 if (buf_ptr[cnt] > max_val)
2531 max_val = buf_ptr[cnt];
2532 }
2533
2534 return max_val;
2535}
2536
2537/*
2538 * The following functions return memory parameters:
2539 * bus and device width, device size
2540 */
2541
2542u32 hws_ddr3_get_bus_width(void)
2543{
2544 struct hws_topology_map *tm = ddr3_get_topology_map();
2545
2546 return (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) ==
2547 1) ? 16 : 32;
2548}
2549
2550u32 hws_ddr3_get_device_width(u32 if_id)
2551{
2552 struct hws_topology_map *tm = ddr3_get_topology_map();
2553
2554 return (tm->interface_params[if_id].bus_width ==
2555 BUS_WIDTH_8) ? 8 : 16;
2556}
2557
2558u32 hws_ddr3_get_device_size(u32 if_id)
2559{
2560 struct hws_topology_map *tm = ddr3_get_topology_map();
2561
2562 if (tm->interface_params[if_id].memory_size >=
2563 MEM_SIZE_LAST) {
2564 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2565 ("Error: Wrong device size of Cs: %d",
2566 tm->interface_params[if_id].memory_size));
2567 return 0;
2568 } else {
2569 return 1 << tm->interface_params[if_id].memory_size;
2570 }
2571}
2572
2573int hws_ddr3_calc_mem_cs_size(u32 if_id, u32 cs, u32 *cs_size)
2574{
2575 u32 cs_mem_size, dev_size;
2576
2577 dev_size = hws_ddr3_get_device_size(if_id);
2578 if (dev_size != 0) {
2579 cs_mem_size = ((hws_ddr3_get_bus_width() /
2580 hws_ddr3_get_device_width(if_id)) * dev_size);
2581
2582 /* the calculated result in Gbytex16 to avoid float using */
2583
2584 if (cs_mem_size == 2) {
2585 *cs_size = _128M;
2586 } else if (cs_mem_size == 4) {
2587 *cs_size = _256M;
2588 } else if (cs_mem_size == 8) {
2589 *cs_size = _512M;
2590 } else if (cs_mem_size == 16) {
2591 *cs_size = _1G;
2592 } else if (cs_mem_size == 32) {
2593 *cs_size = _2G;
2594 } else {
2595 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2596 ("Error: Wrong Memory size of Cs: %d", cs));
2597 return MV_FAIL;
2598 }
2599 return MV_OK;
2600 } else {
2601 return MV_FAIL;
2602 }
2603}
2604
2605int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr)
2606{
2607 u32 cs_mem_size = 0;
2608#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
2609 u32 physical_mem_size;
2610 u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
2611#endif
2612
2613 if (hws_ddr3_calc_mem_cs_size(if_id, cs, &cs_mem_size) != MV_OK)
2614 return MV_FAIL;
2615
2616#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
2617 struct hws_topology_map *tm = ddr3_get_topology_map();
2618 /*
2619 * if number of address pins doesn't allow to use max mem size that
2620 * is defined in topology mem size is defined by
2621 * DEVICE_MAX_DRAM_ADDRESS_SIZE
2622 */
2623 physical_mem_size =
2624 mv_hwsmem_size[tm->interface_params[0].memory_size];
2625
2626 if (hws_ddr3_get_device_width(cs) == 16) {
2627 /*
2628 * 16bit mem device can be twice more - no need in less
2629 * significant pin
2630 */
2631 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE * 2;
2632 }
2633
2634 if (physical_mem_size > max_mem_size) {
2635 cs_mem_size = max_mem_size *
2636 (hws_ddr3_get_bus_width() /
2637 hws_ddr3_get_device_width(if_id));
2638 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2639 ("Updated Physical Mem size is from 0x%x to %x\n",
2640 physical_mem_size,
2641 DEVICE_MAX_DRAM_ADDRESS_SIZE));
2642 }
2643#endif
2644
2645 /* calculate CS base addr */
2646 *cs_base_addr = ((cs_mem_size) * cs) & 0xffff0000;
2647
2648 return MV_OK;
2649}