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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada8bbbcbd2016-05-24 21:14:01 +09002/*
3 * Copyright (C) 2016 Socionext Inc.
Masahiro Yamada8bbbcbd2016-05-24 21:14:01 +09004 */
5
6#include <common.h>
Masahiro Yamadad3a67812016-10-27 23:47:06 +09007#include <spl.h>
Masahiro Yamada8bbbcbd2016-05-24 21:14:01 +09008#include <linux/bitops.h>
9#include <linux/io.h>
10
11#include "../init.h"
Masahiro Yamada77857e22016-10-27 23:47:05 +090012#include "../sc64-regs.h"
Masahiro Yamada8bbbcbd2016-05-24 21:14:01 +090013#include "../sg-regs.h"
14
Masahiro Yamadab3b1bb72017-02-17 16:17:22 +090015#define SDCTRL_EMMC_HW_RESET 0x59810280
16
Masahiro Yamada8bbbcbd2016-05-24 21:14:01 +090017void uniphier_ld11_clk_init(void)
18{
Masahiro Yamadad3a67812016-10-27 23:47:06 +090019 /* if booted from a device other than USB, without stand-by MPU */
Masahiro Yamada76b31242019-07-10 20:07:40 +090020 if ((readl(sg_base + SG_PINMON0) & BIT(27)) &&
Masahiro Yamadafb092032017-02-14 01:24:26 +090021 uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
Masahiro Yamada76b31242019-07-10 20:07:40 +090022 writel(1, sg_base + SG_ETPHYPSHUT);
23 writel(1, sg_base + SG_ETPHYCNT);
Masahiro Yamada8bbbcbd2016-05-24 21:14:01 +090024
25 udelay(1); /* wait for regulator level 1.1V -> 2.5V */
26
Masahiro Yamada76b31242019-07-10 20:07:40 +090027 writel(3, sg_base + SG_ETPHYCNT);
28 writel(3, sg_base + SG_ETPHYPSHUT);
29 writel(7, sg_base + SG_ETPHYCNT);
Masahiro Yamada8bbbcbd2016-05-24 21:14:01 +090030 }
Masahiro Yamada77857e22016-10-27 23:47:05 +090031
Masahiro Yamadab3b1bb72017-02-17 16:17:22 +090032 /* TODO: use "mmc-pwrseq-emmc" */
33 writel(1, SDCTRL_EMMC_HW_RESET);
34
Tom Riniceed5d22017-05-12 22:33:27 -040035#ifdef CONFIG_USB_EHCI_HCD
Masahiro Yamada77857e22016-10-27 23:47:05 +090036 {
Masahiro Yamada0d3af242017-04-14 11:30:05 +090037 int ch;
38
Masahiro Yamada0d3af242017-04-14 11:30:05 +090039 for (ch = 0; ch < 3; ch++) {
Masahiro Yamada76b31242019-07-10 20:07:40 +090040 void __iomem *phyctrl = sg_base + SG_USBPHYCTRL;
Masahiro Yamada0d3af242017-04-14 11:30:05 +090041
42 writel(0x82280600, phyctrl + 8 * ch);
43 writel(0x00000106, phyctrl + 8 * ch + 4);
44 }
Masahiro Yamada77857e22016-10-27 23:47:05 +090045 }
46#endif
Masahiro Yamada8bbbcbd2016-05-24 21:14:01 +090047}