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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +00002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkaffae2b2002-08-17 09:36:01 +00005 */
6
7#include <common.h>
Stefan Roeseeff3a0a2007-10-31 17:55:58 +01008#include <asm/cache.h>
Yuri Tikhonov18db5a62008-04-29 13:32:45 +02009#include <watchdog.h>
wdenk359733b2003-03-31 17:27:09 +000010
Dave Liu06ed90b2008-12-05 15:36:14 +080011void flush_cache(ulong start_addr, ulong size)
wdenkaffae2b2002-08-17 09:36:01 +000012{
wdenk359733b2003-03-31 17:27:09 +000013#ifndef CONFIG_5xx
Dave Liu06ed90b2008-12-05 15:36:14 +080014 ulong addr, start, end;
wdenkaffae2b2002-08-17 09:36:01 +000015
Dave Liu06ed90b2008-12-05 15:36:14 +080016 start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
17 end = start_addr + size - 1;
wdenkaffae2b2002-08-17 09:36:01 +000018
Kumar Gala3b967ae2009-02-06 08:08:06 -060019 for (addr = start; (addr <= end) && (addr >= start);
20 addr += CONFIG_SYS_CACHELINE_SIZE) {
Dave Liu06ed90b2008-12-05 15:36:14 +080021 asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
22 WATCHDOG_RESET();
23 }
24 /* wait for all dcbst to complete on bus */
25 asm volatile("sync" : : : "memory");
26
Kumar Gala3b967ae2009-02-06 08:08:06 -060027 for (addr = start; (addr <= end) && (addr >= start);
28 addr += CONFIG_SYS_CACHELINE_SIZE) {
Dave Liu06ed90b2008-12-05 15:36:14 +080029 asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
30 WATCHDOG_RESET();
wdenkaffae2b2002-08-17 09:36:01 +000031 }
Dave Liu06ed90b2008-12-05 15:36:14 +080032 asm volatile("sync" : : : "memory");
33 /* flush prefetch queue */
34 asm volatile("isync" : : : "memory");
wdenk359733b2003-03-31 17:27:09 +000035#endif
wdenkaffae2b2002-08-17 09:36:01 +000036}