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git01.mediatek.com / filogic / uboot / 7675af0d666ea785f5cd361d8f859ad08a578a81 / . / include / configs / db-88f6820-amc.h
blob: 6056cb8fed082477ea0505413e54a7a4212dea8e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]2/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]4 */
5
6#ifndef _CONFIG_DB_88F6820_AMC_H
7#define _CONFIG_DB_88F6820_AMC_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
12
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]13/*
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
16 * U-Boot into it.
17 */
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]18#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
19
20/*
21 * Commands configuration
22 */
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]23
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]24/* SPI NOR flash default params, used by sf commands */
25#define CONFIG_SF_DEFAULT_BUS 1
26#define CONFIG_SF_DEFAULT_SPEED 1000000
27#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
28
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]29/* USB/EHCI configuration */
30#define CONFIG_EHCI_IS_TDI
31
32/* Environment in SPI NOR flash */
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]33#define CONFIG_ENV_SPI_BUS 1
34#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
35#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
36#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
37
38#define CONFIG_PHY_MARVELL /* there is a marvell phy */
39#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
40
41/* PCIe support */
42#ifndef CONFIG_SPL_BUILD
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]43#define CONFIG_PCI_MVEBU
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]44#define CONFIG_PCI_SCAN_SHOW
45#endif
46
Chris Packham228efd02016-09-22 12:56:15 +1200[diff] [blame]47/* NAND */
48#define CONFIG_SYS_NAND_USE_FLASH_BBT
49#define CONFIG_SYS_NAND_ONFI_DETECTION
50
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]51/* Keep device tree and initrd in lower memory so the kernel can access them */
52#define CONFIG_EXTRA_ENV_SETTINGS \
53 "fdt_high=0x10000000\0" \
54 "initrd_high=0x10000000\0"
55
56/* SPL */
57/*
58 * Select the boot device here
59 *
60 * Currently supported are:
61 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
62 *
63 * MMC is not populated on this board.
64 * NAND support may be added in the future.
65 */
66#define SPL_BOOT_SPI_NOR_FLASH 1
67#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
68
69/* Defines for SPL */
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]70#define CONFIG_SPL_SIZE (140 << 10)
71#define CONFIG_SPL_TEXT_BASE 0x40000030
72#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
73
74#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
75#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
76
77#ifdef CONFIG_SPL_BUILD
78#define CONFIG_SYS_MALLOC_SIMPLE
79#endif
80
81#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
82#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
83
84#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
85/* SPL related SPI defines */
Chris Packhama90dd4c2016-09-22 12:56:14 +1200[diff] [blame]86#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
87#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
88#endif
89
90/*
91 * mv-common.h should be defined after CMD configs since it used them
92 * to enable certain macros
93 */
94#include "mv-common.h"
95#undef CONFIG_SYS_MAXARGS
96#define CONFIG_SYS_MAXARGS 96
97
98#endif /* _CONFIG_DB_88F6820_AMC_H */