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git01.mediatek.com / filogic / uboot / 765f1edcf8d5a141cdd5a2eb421ab783d2250646 / . / arch / arm / dts / zynqmp-e-a2197-00-revA.dts
blob: f229880a70210b6ad5bf386faabe3e2e9cb1f83e [file] [log] [blame]
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]5 * (C) Copyright 2019 - 2021, Xilinx, Inc.
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/phy/phy.h>
15
16/ {
17 model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
18 compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
19 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem0;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +0200[diff] [blame]26 nvmem0 = &eeprom;
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]27 nvmem1 = &eeprom_ebm;
28 nvmem2 = &eeprom_fmc1;
29 nvmem3 = &eeprom_fmc2;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]30 rtc0 = &rtc;
31 serial0 = &uart0;
32 serial1 = &dcc;
33 };
34
35 chosen {
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]38 };
39
40 memory@0 {
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>;
43 };
44
45 ina226-vccint {
46 compatible = "iio-hwmon";
47 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
48 };
49 ina226-vcc-soc {
50 compatible = "iio-hwmon";
51 io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
52 };
53 ina226-vcc-pmc {
54 compatible = "iio-hwmon";
55 io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
56 };
57 ina226-vcc-ram {
58 compatible = "iio-hwmon";
59 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
60 };
61 ina226-vcc-pslp {
62 compatible = "iio-hwmon";
63 io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
64 };
65 ina226-vcc-psfp {
66 compatible = "iio-hwmon";
67 io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
68 };
69 ina226-vccaux {
70 compatible = "iio-hwmon";
71 io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
72 };
73 ina226-vccaux-pmc {
74 compatible = "iio-hwmon";
75 io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
76 };
77 ina226-vcco-500 {
78 compatible = "iio-hwmon";
79 io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
80 };
81 ina226-vcco-501 {
82 compatible = "iio-hwmon";
83 io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
84 };
85 ina226-vcco-502 {
86 compatible = "iio-hwmon";
87 io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
88 };
89 ina226-vcco-503 {
90 compatible = "iio-hwmon";
91 io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
92 };
93 ina226-vcc-1v8 {
94 compatible = "iio-hwmon";
95 io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
96 };
97 ina226-vcc-3v3 {
98 compatible = "iio-hwmon";
99 io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
100 };
101 ina226-vcc-1v2-ddr4 {
102 compatible = "iio-hwmon";
103 io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
104 };
105 ina226-vcc-1v1-lp4 {
106 compatible = "iio-hwmon";
107 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
108 };
109 ina226-vadj-fmc {
110 compatible = "iio-hwmon";
111 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
112 };
113 ina226-mgtyavcc {
114 compatible = "iio-hwmon";
115 io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
116 };
117 ina226-mgtyavtt {
118 compatible = "iio-hwmon";
119 io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
120 };
121 ina226-mgtyvccaux {
122 compatible = "iio-hwmon";
123 io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
124 };
125};
126
127&uart0 { /* uart0 MIO38-39 */
128 status = "okay";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]129};
130
131&sdhci1 { /* sd1 MIO45-51 cd in place */
132 status = "okay";
133 no-1-8-v;
134 disable-wp;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]135 xlnx,mio-bank = <1>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]136};
137
138&gem0 {
139 status = "okay";
140 phy-handle = <&phy0>;
141 phy-mode = "sgmii";
142 is-internal-pcspma;
143 phy0: ethernet-phy@0 { /* u131 M88E1512 */
144 reg = <0>;
145 };
146};
147
148&gpio {
149 status = "okay";
150 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
151 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
152 "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
153 "", "", "", "", "", /* 15 - 19 */
154 "", "", "", "", "", /* 20 - 24 */
155 "", "", "", "", "", /* 25 - 29 */
156 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
157 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
158 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
159 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
160 "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
161 "", "", "", "", "", /* 55 - 59 */
162 "", "", "", "", "", /* 60 - 64 */
163 "", "", "", "", "", /* 65 - 69 */
164 "", "", "", "", "", /* 70 - 74 */
165 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
Saeed Nowshadi893180e2020-03-27 08:12:20 -0700[diff] [blame]166 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]167 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
168 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
169 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
170 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]171 "", "", "", "", "", /* 100 - 104 */
172 "", "", "", "", "", /* 105 - 109 */
173 "", "", "", "", "", /* 110 - 114 */
174 "", "", "", "", "", /* 115 - 119 */
175 "", "", "", "", "", /* 120 - 124 */
176 "", "", "", "", "", /* 125 - 129 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]177 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]178 "", "", "", "", "", /* 135 - 139 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]179 "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
180 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]181 "", "", "", "", "", /* 150 - 154 */
182 "", "", "", "", "", /* 155 - 159 */
183 "", "", "", "", "", /* 160 - 164 */
184 "", "", "", "", "", /* 165 - 169 */
185 "", "", "", ""; /* 170 - 174 */
186};
187
188&i2c0 { /* MIO 34-35 - can't stay here */
189 status = "okay";
190 clock-frequency = <400000>;
191 i2c-mux@74 { /* u33 */
192 compatible = "nxp,pca9548";
193 #address-cells = <1>;
194 #size-cells = <0>;
195 reg = <0x74>;
196 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
197 i2c@0 { /* PMBUS */
198 #address-cells = <1>;
199 #size-cells = <0>;
200 reg = <0>;
201 /* u152 IR35215 0x16/0x46 vcc_soc */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]202 /* u179 ir38164 0x19/0x49 vcco_500 */
203 /* u181 ir38164 0x1a/0x4a vcco_501 */
204 /* u183 ir38164 0x1b/0x4b vcco_502 */
205 /* u185 ir38164 0x1e/0x4e vadj_fmc */
206 /* u187 ir38164 0x1F/0x4f mgtyavcc */
207 /* u189 ir38164 0x20/0x50 mgtyavtt */
208 /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
209 /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
Michal Simek3514e4e2020-03-30 11:35:38 +0200[diff] [blame]210
211 irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
212 compatible = "infineon,irps5401";
213 reg = <0x47>; /* pmbus / i2c 0x17 */
214 };
215 irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
216 compatible = "infineon,irps5401";
217 reg = <0x4c>; /* pmbus / i2c 0x1c */
218 };
219 irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
220 compatible = "infineon,irps5401";
221 reg = <0x4d>; /* pmbus / i2c 0x1d */
222 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]223 };
224 i2c@1 { /* PMBUS1_INA226 */
225 #address-cells = <1>;
226 #size-cells = <0>;
227 reg = <1>;
228 /* FIXME check alerts coming to SC */
229 vccint: ina226@40 { /* u65 */
230 compatible = "ti,ina226";
231 #io-channel-cells = <1>;
232 label = "ina226-vccint";
233 reg = <0x40>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]234 shunt-resistor = <500>; /* R440 */
235 /* 0.80V @ 32A 1 of 6 Phases*/
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]236 };
237 vcc_soc: ina226@41 { /* u161 */
238 compatible = "ti,ina226";
239 #io-channel-cells = <1>;
240 label = "ina226-vcc-soc";
241 reg = <0x41>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]242 shunt-resistor = <500>; /* R1702 */
243 /* 0.80V @ 18A */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]244 };
245 vcc_pmc: ina226@42 { /* u163 */
246 compatible = "ti,ina226";
247 #io-channel-cells = <1>;
248 label = "ina226-vcc-pmc";
249 reg = <0x42>;
250 shunt-resistor = <5000>; /* R1214 */
251 /* 0.78V @ 500mA */
252 };
253 vcc_ram: ina226@43 { /* u162 */
254 compatible = "ti,ina226";
255 #io-channel-cells = <1>;
256 label = "ina226-vcc-ram";
257 reg = <0x43>;
258 shunt-resistor = <5000>; /* r1221 */
259 /* 0.78V @ 4A */
260 };
261 vcc_pslp: ina226@44 { /* u165 */
262 compatible = "ti,ina226";
263 #io-channel-cells = <1>;
264 label = "ina226-vcc-pslp";
265 reg = <0x44>;
266 shunt-resistor = <5000>; /* R1216 */
267 /* 0.78V @ 1A */
268 };
269 vcc_psfp: ina226@45 { /* u164 */
270 compatible = "ti,ina226";
271 #io-channel-cells = <1>;
272 label = "ina226-vcc-psfp";
273 reg = <0x45>;
274 shunt-resistor = <5000>; /* R1219 */
275 /* 0.78V @ 2A */
276 };
277 };
278 i2c@2 { /* PCIE_CLK */
279 #address-cells = <1>;
280 #size-cells = <0>;
281 reg = <2>;
282 clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */
283 #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
284 compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
285 reg = <0xd8>;
286 /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
287 /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
288 };
289 };
290 i2c@3 { /* PMBUS2_INA226 */
291 #address-cells = <1>;
292 #size-cells = <0>;
293 reg = <3>;
294 /* FIXME check alerts coming to SC */
295 vccaux: ina226@40 { /* u166 */
296 compatible = "ti,ina226";
297 #io-channel-cells = <1>;
298 label = "ina226-vccaux";
299 reg = <0x40>;
300 shunt-resistor = <5000>; /* R382 */
301 /* 1.5V @ 3A */
302 };
303 vccaux_pmc: ina226@41 { /* u168 */
304 compatible = "ti,ina226";
305 #io-channel-cells = <1>;
306 label = "ina226-vccaux-pmc";
307 reg = <0x41>;
308 shunt-resistor = <5000>; /* R1246 */
309 /* 1.5V @ 500mA */
310 };
311 vcco_500: ina226@42 { /* u178 */
312 compatible = "ti,ina226";
313 #io-channel-cells = <1>;
314 label = "ina226-vcco-500";
315 reg = <0x42>;
316 shunt-resistor = <2000>; /* R1300 */
317 /* 3.3V @ 5A */
318 };
319 vcco_501: ina226@43 { /* u180 */
320 compatible = "ti,ina226";
321 #io-channel-cells = <1>;
322 label = "ina226-vcco-501";
323 reg = <0x43>;
324 shunt-resistor = <2000>; /* R1313 */
325 /* 3.3V @ 5A */
326 };
327 vcco_502: ina226@44 { /* u182 */
328 compatible = "ti,ina226";
329 #io-channel-cells = <1>;
330 label = "ina226-vcco-502";
331 reg = <0x44>;
332 shunt-resistor = <2000>; /* R1330 */
333 /* 3.3V @ 5A */
334 };
335 vcco_503: ina226@45 { /* u172 */
336 compatible = "ti,ina226";
337 #io-channel-cells = <1>;
338 label = "ina226-vcco-503";
339 reg = <0x45>;
340 shunt-resistor = <5000>; /* R1229 */
341 /* 1.8V @ 2A */
342 };
343 vcc_1v8: ina226@46 { /* u173 */
344 compatible = "ti,ina226";
345 #io-channel-cells = <1>;
346 label = "ina226-vcc-1v8";
347 reg = <0x46>;
348 shunt-resistor = <5000>; /* R400 */
349 /* 1.8V @ 6A */
350 };
351 vcc_3v3: ina226@47 { /* u174 */
352 compatible = "ti,ina226";
353 #io-channel-cells = <1>;
354 label = "ina226-vcc-3v3";
355 reg = <0x47>;
356 shunt-resistor = <5000>; /* R1232 */
357 /* 3.3V @ 500mA */
358 };
359 vcc_1v2_ddr4: ina226@48 { /* u176 */
360 compatible = "ti,ina226";
361 #io-channel-cells = <1>;
362 label = "ina226-vcc-1v2-ddr4";
363 reg = <0x48>;
364 shunt-resistor = <5000>; /* R1275 */
365 /* 1.2V @ 4A */
366 };
367 vcc1v1_lp4: ina226@49 { /* u177 */
368 compatible = "ti,ina226";
369 #io-channel-cells = <1>;
370 label = "ina226-vcc1v1-lp4";
371 reg = <0x49>;
372 shunt-resistor = <5000>; /* R1286 */
373 /* 1.1V @ 4A */
374 };
375 vadj_fmc: ina226@4a { /* u184 */
376 compatible = "ti,ina226";
377 #io-channel-cells = <1>;
378 label = "ina226-vadj-fmc";
379 reg = <0x4a>;
380 shunt-resistor = <2000>; /* R1350 */
381 /* 1.5V @ 10A */
382 };
383 mgtyavcc: ina226@4b { /* u186 */
384 compatible = "ti,ina226";
385 #io-channel-cells = <1>;
386 label = "ina226-mgtyavcc";
387 reg = <0x4b>;
388 shunt-resistor = <2000>; /* R1367 */
389 /* 0.88V @ 6A */
390 };
391 mgtyavtt: ina226@4c { /* u188 */
392 compatible = "ti,ina226";
393 #io-channel-cells = <1>;
394 label = "ina226-mgtyavtt";
395 reg = <0x4c>;
396 shunt-resistor = <2000>; /* R1384 */
397 /* 1.2V @ 10A */
398 };
399 mgtyvccaux: ina226@4d { /* u234 */
400 compatible = "ti,ina226";
401 #io-channel-cells = <1>;
402 label = "ina226-mgtyvccaux";
403 reg = <0x4d>;
404 shunt-resistor = <5000>; /* r1679 */
405 /* 1.5V @ 500mA */
406 };
407 };
408 i2c@4 { /* LP_I2C_SM */
409 #address-cells = <1>;
410 #size-cells = <0>;
411 reg = <4>;
412 /* FIXME wires ready but chip is missing */
413 };
414 i2c@5 { /* zSFP_SI570 */
415 #address-cells = <1>;
416 #size-cells = <0>;
417 reg = <5>;
418 si570_zsfp: clock-generator@5d { /* u192 */
419 #clock-cells = <0>;
420 compatible = "silabs,si570";
421 reg = <0x5d>;
422 temperature-stability = <50>;
423 factory-fout = <156250000>;
424 clock-frequency = <156250000>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]425 clock-output-names = "si570_zsfp_clk";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]426 };
427 };
428 i2c@6 { /* USER_SI570_1 */
429 #address-cells = <1>;
430 #size-cells = <0>;
431 reg = <6>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]432 si570_user1: clock-generator@5d { /* u205 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]433 #clock-cells = <0>;
434 compatible = "silabs,si570";
435 reg = <0x5f>;
436 temperature-stability = <50>;
437 factory-fout = <100000000>;
438 clock-frequency = <100000000>;
439 clock-output-names = "si570_user1";
440 };
441
442 };
443 i2c@7 { /* USER_SI570_2 */
444 #address-cells = <1>;
445 #size-cells = <0>;
446 reg = <7>;
447 /* FIXME wires ready but chip is missing */
448 };
449 };
450};
451
452&i2c1 { /* i2c1 MIO 36-37 */
453 status = "okay";
454 clock-frequency = <400000>;
455
456 i2c-mux@74 { /* u35 */
457 compatible = "nxp,pca9548";
458 #address-cells = <1>;
459 #size-cells = <0>;
460 reg = <0x74>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]461 i2c-mux-idle-disconnect;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]462 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
463 dc_i2c: i2c@0 { /* DC_I2C */
464 #address-cells = <1>;
465 #size-cells = <0>;
466 reg = <0>;
467 /* Use for storing information about SC board */
468 eeprom: eeprom@54 { /* u34 - m24128 16kB */
469 compatible = "st,24c128", "atmel,24c128";
470 reg = <0x54>; /* 0x5c too */
471 };
472 si570_ref_clk: clock-generator@5d { /* u32 */
473 #clock-cells = <0>;
474 compatible = "silabs,si570";
475 reg = <0x5d>;
476 temperature-stability = <50>;
477 factory-fout = <33333333>;
478 clock-frequency = <33333333>;
479 clock-output-names = "ref_clk";
Michal Simekf86d2b52021-03-09 12:43:42 +0100[diff] [blame]480 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]481 };
482 /* and connector J212D */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]483 eeprom_ebm: eeprom@52 { /* x-ebm module */
484 compatible = "st,24c128", "atmel,24c128";
485 reg = <0x52>;
486 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]487 };
488 fmc1: i2c@1 { /* FMCP1_IIC */
489 #address-cells = <1>;
490 #size-cells = <0>;
491 reg = <1>;
492 /* FIXME connection to Samtec J51C */
493 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]494 eeprom_fmc1: eeprom@50 {
495 compatible = "st,24c128", "atmel,24c128";
496 reg = <0x50>;
497 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]498 };
499 fmc2: i2c@2 { /* FMCP2_IIC */
500 #address-cells = <1>;
501 #size-cells = <0>;
502 reg = <2>;
503 /* FIXME connection to Samtec J53C */
504 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]505 eeprom_fmc2: eeprom@50 {
506 compatible = "st,24c128", "atmel,24c128";
507 reg = <0x50>;
508 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]509 };
510 i2c@3 { /* DDR4_DIMM1 */
511 #address-cells = <1>;
512 #size-cells = <0>;
513 reg = <3>;
514 si570_ddr_dimm1: clock-generator@60 { /* u2 */
515 #clock-cells = <0>;
516 compatible = "silabs,si570";
517 reg = <0x60>;
518 temperature-stability = <50>;
519 factory-fout = <200000000>;
520 clock-frequency = <200000000>;
521 clock-output-names = "si570_ddrdimm1_clk";
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]522 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]523 };
524 };
525 i2c@4 { /* LPDDR4_SI570_CLK2 */
526 #address-cells = <1>;
527 #size-cells = <0>;
528 reg = <4>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]529 si570_lpddr4clk2: clock-generator@60 { /* u3 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]530 #clock-cells = <0>;
531 compatible = "silabs,si570";
532 reg = <0x60>;
533 temperature-stability = <50>;
534 factory-fout = <200000000>;
535 clock-frequency = <200000000>;
536 clock-output-names = "si570_lpddr4_clk2";
537 };
538 };
539 i2c@5 { /* LPDDR4_SI570_CLK1 */
540 #address-cells = <1>;
541 #size-cells = <0>;
542 reg = <5>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]543 si570_lpddr4clk1: clock-generator@60 { /* u4 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]544 #clock-cells = <0>;
545 compatible = "silabs,si570";
546 reg = <0x60>;
547 temperature-stability = <50>;
548 factory-fout = <200000000>;
549 clock-frequency = <200000000>;
550 clock-output-names = "si570_lpddr4_clk1";
551 };
552 };
553 i2c@6 { /* HSDP_SI570 */
554 #address-cells = <1>;
555 #size-cells = <0>;
556 reg = <6>;
557 si570_hsdp: clock-generator@5d { /* u5 */
558 #clock-cells = <0>;
559 compatible = "silabs,si570";
560 reg = <0x5d>;
561 temperature-stability = <50>;
562 factory-fout = <156250000>;
563 clock-frequency = <156250000>;
564 clock-output-names = "si570_hsdp_clk";
565 };
566 };
567 i2c@7 { /* 8A34001 - U219B and J310 connector */
568 #address-cells = <1>;
569 #size-cells = <0>;
570 reg = <7>;
571 };
572 };
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]573 i2c-mux@75 { /* u214 */
574 compatible = "nxp,pca9548";
575 #address-cells = <1>;
576 #size-cells = <0>;
577 reg = <0x75>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]578 i2c-mux-idle-disconnect;
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]579 i2c@0 { /* SFP0_IIC */
580 #address-cells = <1>;
581 #size-cells = <0>;
582 reg = <0>;
583 /* SFP0 */
584 };
585 i2c@1 { /* SFP1_IIC */
586 #address-cells = <1>;
587 #size-cells = <0>;
588 reg = <1>;
589 /* SFP1 */
590 };
591 i2c@2 { /* QSFP1_I2C */
592 #address-cells = <1>;
593 #size-cells = <0>;
594 reg = <2>;
595 /* QSFP1 */
596 };
597 /* 3 - 7 unused */
598 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]599};
600
601&xilinx_ams {
602 status = "okay";
603};
604
605&ams_ps {
606 status = "okay";
607};
608
609&ams_pl {
610 status = "okay";
611};