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git01.mediatek.com / filogic / uboot / 765f1edcf8d5a141cdd5a2eb421ab783d2250646 / . / arch / arm / dts / vf.dtsi
blob: 1bdaf3de2303e5680347184956596b30ae0f1ea1 [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]4 */
5/include/ "skeleton.dtsi"
Sanchayan Maity05fb4b92016-08-09 23:45:00 +0530[diff] [blame]6#include <dt-bindings/gpio/gpio.h>
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]7
8/ {
9 aliases {
10 gpio0 = &gpio0;
11 gpio1 = &gpio1;
12 gpio2 = &gpio2;
13 gpio3 = &gpio3;
14 gpio4 = &gpio4;
Bhuvanchandra DV263d4702016-01-27 10:31:45 +0530[diff] [blame]15 serial0 = &uart0;
16 serial1 = &uart1;
17 serial2 = &uart2;
18 serial3 = &uart3;
19 serial4 = &uart4;
20 serial5 = &uart5;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]21 spi0 = &dspi0;
22 spi1 = &dspi1;
Sanchayan Maity05fb4b92016-08-09 23:45:00 +0530[diff] [blame]23 ehci0 = &ehci0;
24 ehci1 = &ehci1;
Lukasz Majewski4c2825d2019-02-13 22:46:46 +0100[diff] [blame]25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
28 i2c3 = &i2c3;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]29 };
30
31 soc {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "simple-bus";
35 ranges;
36
Oleksandr Suvorove1868a42021-09-23 23:14:37 +0300[diff] [blame]37 aips0: bus@40000000 {
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]38 compatible = "fsl,aips-bus", "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
Stefan Agner08afbfe2016-11-30 13:41:57 -0800[diff] [blame]41 reg = <0x40000000 0x00070000>;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]42 ranges;
43
Bhuvanchandra DV263d4702016-01-27 10:31:45 +0530[diff] [blame]44 uart0: serial@40027000 {
45 compatible = "fsl,vf610-lpuart";
46 reg = <0x40027000 0x1000>;
47 status = "disabled";
48 };
49
50 uart1: serial@40028000 {
51 compatible = "fsl,vf610-lpuart";
52 reg = <0x40028000 0x1000>;
53 status = "disabled";
54 };
55
56 uart2: serial@40029000 {
57 compatible = "fsl,vf610-lpuart";
58 reg = <0x40029000 0x1000>;
59 status = "disabled";
60 };
61
62 uart3: serial@4002a000 {
63 compatible = "fsl,vf610-lpuart";
64 reg = <0x4002a000 0x1000>;
65 status = "disabled";
66 };
67
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]68 dspi0: dspi0@4002c000 {
69 #address-cells = <1>;
70 #size-cells = <0>;
71 compatible = "fsl,vf610-dspi";
72 reg = <0x4002c000 0x1000>;
Michael Walle2de392c2021-10-13 18:14:18 +0200[diff] [blame]73 spi-num-chipselects = <5>;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]74 status = "disabled";
75 };
76
77 dspi1: dspi1@4002d000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 compatible = "fsl,vf610-dspi";
81 reg = <0x4002d000 0x1000>;
Michael Walle2de392c2021-10-13 18:14:18 +0200[diff] [blame]82 spi-num-chipselects = <5>;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]83 status = "disabled";
84 };
85
86 qspi0: quadspi@40044000 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "fsl,vf610-qspi";
Albert ARIBAUD \(3ADEV\)ddef3b62016-09-26 09:08:08 +0200[diff] [blame]90 reg = <0x40044000 0x1000>,
91 <0x20000000 0x10000000>;
92 reg-names = "QuadSPI", "QuadSPI-memory";
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]93 status = "disabled";
94 };
95
Lukasz Majewski4c2825d2019-02-13 22:46:46 +0100[diff] [blame]96 i2c0: i2c@40066000 {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "fsl,vf610-i2c";
100 reg = <0x40066000 0x1000>;
101 status = "disabled";
102 };
103
104 i2c1: i2c@40067000 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 compatible = "fsl,vf610-i2c";
108 reg = <0x40067000 0x1000>;
109 status = "disabled";
110 };
111
Lukasz Majewskice0cd172018-11-20 00:38:07 +0100[diff] [blame]112 iomuxc: iomuxc@40048000 {
113 compatible = "fsl,vf610-iomuxc";
114 reg = <0x40048000 0x1000>;
115 fsl,mux_mask = <0x700000>;
116 };
117
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]118 gpio0: gpio@40049000 {
119 compatible = "fsl,vf610-gpio";
120 reg = <0x400ff000 0x40>;
121 #gpio-cells = <2>;
122 };
123
124 gpio1: gpio@4004a000 {
125 compatible = "fsl,vf610-gpio";
126 reg = <0x400ff040 0x40>;
127 #gpio-cells = <2>;
128 };
129
130 gpio2: gpio@4004b000 {
131 compatible = "fsl,vf610-gpio";
132 reg = <0x400ff080 0x40>;
133 #gpio-cells = <2>;
134 };
135
136 gpio3: gpio@4004c000 {
137 compatible = "fsl,vf610-gpio";
138 reg = <0x400ff0c0 0x40>;
139 #gpio-cells = <2>;
140 };
141
142 gpio4: gpio@4004d000 {
143 compatible = "fsl,vf610-gpio";
144 reg = <0x400ff100 0x40>;
145 #gpio-cells = <2>;
146 };
Sanchayan Maity05fb4b92016-08-09 23:45:00 +0530[diff] [blame]147
Igor Opaniuk7a6310a2019-06-10 14:47:51 +0300[diff] [blame]148 dcu0: dcu@40058000 {
149 compatible = "fsl,vf610-dcu";
150 reg = <0x40058000 0x1200>;
151 status = "disabled";
152 };
153
Sanchayan Maity05fb4b92016-08-09 23:45:00 +0530[diff] [blame]154 ehci0: ehci@40034000 {
155 compatible = "fsl,vf610-usb";
156 reg = <0x40034000 0x800>;
157 status = "disabled";
158 };
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]159 };
160
Oleksandr Suvorove1868a42021-09-23 23:14:37 +0300[diff] [blame]161 aips1: bus@40080000 {
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]162 compatible = "fsl,aips-bus", "simple-bus";
163 #address-cells = <1>;
164 #size-cells = <1>;
Stefan Agner08afbfe2016-11-30 13:41:57 -0800[diff] [blame]165 reg = <0x40080000 0x0007f000>;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]166 ranges;
Bhuvanchandra DV263d4702016-01-27 10:31:45 +0530[diff] [blame]167
168 uart4: serial@400a9000 {
169 compatible = "fsl,vf610-lpuart";
170 reg = <0x400a9000 0x1000>;
171 status = "disabled";
172 };
173
174 uart5: serial@400aa000 {
175 compatible = "fsl,vf610-lpuart";
176 reg = <0x400aa000 0x1000>;
177 status = "disabled";
178 };
179
Sanchayan Maity05fb4b92016-08-09 23:45:00 +0530[diff] [blame]180 ehci1: ehci@400b4000 {
181 compatible = "fsl,vf610-usb";
182 reg = <0x400b4000 0x800>;
183 status = "disabled";
184 };
Lukasz Majewski4c2825d2019-02-13 22:46:46 +0100[diff] [blame]185
186 esdhc1: esdhc@400b2000 {
187 compatible = "fsl,esdhc";
188 reg = <0x400b2000 0x1000>;
189 status = "disabled";
190 };
191
192 fec0: fec@400d0000 {
193 compatible = "fsl,mvf600-fec";
194 reg = <0x400d0000 0x1000>;
195 status = "disabled";
196 };
197
198 fec1: fec@400d1000 {
199 compatible = "fsl,mvf600-fec";
200 reg = <0x400d1000 0x1000>;
201 status = "disabled";
202 };
203
204 nfc: nand@400e0000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,vf610-nfc";
208 reg = <0x400e0000 0x4000>;
209 status = "disabled";
210 };
211
212 i2c2: i2c@400e6000 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "fsl,vf610-i2c";
216 reg = <0x400e6000 0x1000>;
217 status = "disabled";
218 };
219
220 i2c3: i2c@400e7000 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,vf610-i2c";
224 reg = <0x400e7000 0x1000>;
225 status = "disabled";
226 };
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]227 };
228 };
229};