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Patrick Delaunay50599142018-07-09 15:17:19 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
Patrick Delaunay06020d82018-03-12 10:46:17 +01002/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
Patrick Delaunay06020d82018-03-12 10:46:17 +01006/dts-v1/;
7
Patrick Delaunay48c5e902020-03-06 17:54:41 +01008#include "stm32mp157.dtsi"
9#include "stm32mp15xc.dtsi"
10#include "stm32mp15-pinctrl.dtsi"
11#include "stm32mp15xxaa-pinctrl.dtsi"
Patrick Delaunay06020d82018-03-12 10:46:17 +010012#include <dt-bindings/gpio/gpio.h>
Patrick Delaunay91be5942019-02-04 11:26:16 +010013#include <dt-bindings/mfd/st,stpmic1.h>
Patrick Delaunay06020d82018-03-12 10:46:17 +010014
15/ {
Patrick Delaunay50599142018-07-09 15:17:19 +020016 model = "STMicroelectronics STM32MP157C eval daughter";
Patrick Delaunay06020d82018-03-12 10:46:17 +010017 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
18
19 chosen {
Patrice Chotard00442d02019-02-12 16:50:38 +010020 stdout-path = "serial0:115200n8";
Patrick Delaunay06020d82018-03-12 10:46:17 +010021 };
22
Patrick Delaunay50599142018-07-09 15:17:19 +020023 memory@c0000000 {
Patrick Delaunaya3705302019-07-11 11:15:28 +020024 device_type = "memory";
Patrick Delaunay06020d82018-03-12 10:46:17 +010025 reg = <0xC0000000 0x40000000>;
26 };
Patrice Chotardf6ef2292018-04-26 17:13:11 +020027
Patrick Delaunay708cae72019-07-30 19:16:12 +020028 reserved-memory {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 ranges;
32
Patrick Delaunay8c6e6132019-11-06 16:16:33 +010033 mcuram2: mcuram2@10000000 {
34 compatible = "shared-dma-pool";
35 reg = <0x10000000 0x40000>;
36 no-map;
37 };
38
39 vdev0vring0: vdev0vring0@10040000 {
40 compatible = "shared-dma-pool";
41 reg = <0x10040000 0x1000>;
42 no-map;
43 };
44
45 vdev0vring1: vdev0vring1@10041000 {
46 compatible = "shared-dma-pool";
47 reg = <0x10041000 0x1000>;
48 no-map;
49 };
50
51 vdev0buffer: vdev0buffer@10042000 {
52 compatible = "shared-dma-pool";
53 reg = <0x10042000 0x4000>;
54 no-map;
55 };
56
57 mcuram: mcuram@30000000 {
58 compatible = "shared-dma-pool";
59 reg = <0x30000000 0x40000>;
60 no-map;
61 };
62
63 retram: retram@38000000 {
64 compatible = "shared-dma-pool";
65 reg = <0x38000000 0x10000>;
66 no-map;
67 };
68
Patrick Delaunay708cae72019-07-30 19:16:12 +020069 gpu_reserved: gpu@e8000000 {
70 reg = <0xe8000000 0x8000000>;
71 no-map;
72 };
73 };
74
Patrice Chotard00442d02019-02-12 16:50:38 +010075 aliases {
76 serial0 = &uart4;
77 };
78
Patrice Chotardf6ef2292018-04-26 17:13:11 +020079 sd_switch: regulator-sd_switch {
80 compatible = "regulator-gpio";
81 regulator-name = "sd_switch";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <2900000>;
84 regulator-type = "voltage";
85 regulator-always-on;
86
87 gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
88 gpios-states = <0>;
Patrick Delaunayb9c16b72020-01-28 10:11:00 +010089 states = <1800000 0x1>,
90 <2900000 0x0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +020091 };
Patrick Delaunay6d397052021-01-11 12:33:36 +010092
93 vin: vin {
94 compatible = "regulator-fixed";
95 regulator-name = "vin";
96 regulator-min-microvolt = <5000000>;
97 regulator-max-microvolt = <5000000>;
98 regulator-always-on;
99 };
Patrick Delaunay06020d82018-03-12 10:46:17 +0100100};
101
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100102&adc {
103 /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
104 pinctrl-0 = <&adc1_in6_pins_a>;
105 pinctrl-names = "default";
106 vdd-supply = <&vdd>;
107 vdda-supply = <&vdda>;
108 vref-supply = <&vdda>;
109 status = "disabled";
110 adc1: adc@0 {
111 st,adc-channels = <0 1 6>;
112 /* 16.5 ck_cycles sampling time */
113 st,min-sample-time-nsecs = <400>;
114 status = "okay";
115 };
116};
117
Patrick Delaunay0e20c1f2020-05-25 12:19:42 +0200118&cpu0{
119 cpu-supply = <&vddcore>;
120};
121
122&cpu1{
123 cpu-supply = <&vddcore>;
124};
125
Patrick Delaunay6d397052021-01-11 12:33:36 +0100126&crc1 {
127 status = "okay";
128};
129
130&cryp1 {
131 status = "okay";
132};
133
Patrick Delaunayb9c16b72020-01-28 10:11:00 +0100134&dac {
135 pinctrl-names = "default";
136 pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
137 vref-supply = <&vdda>;
138 status = "disabled";
139 dac1: dac@1 {
140 status = "okay";
141 };
142 dac2: dac@2 {
143 status = "okay";
144 };
145};
146
Patrick Delaunaya3705302019-07-11 11:15:28 +0200147&dts {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100148 status = "okay";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100149};
150
Patrick Delaunay708cae72019-07-30 19:16:12 +0200151&gpu {
152 contiguous-area = <&gpu_reserved>;
Patrick Delaunay708cae72019-07-30 19:16:12 +0200153};
154
Patrick Delaunay6d397052021-01-11 12:33:36 +0100155&hash1 {
156 status = "okay";
157};
158
Patrick Delaunay06020d82018-03-12 10:46:17 +0100159&i2c4 {
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200160 pinctrl-names = "default", "sleep";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100161 pinctrl-0 = <&i2c4_pins_a>;
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200162 pinctrl-1 = <&i2c4_sleep_pins_a>;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100163 i2c-scl-rising-time-ns = <185>;
164 i2c-scl-falling-time-ns = <20>;
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200165 clock-frequency = <400000>;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100166 status = "okay";
Patrick Delaunaya3705302019-07-11 11:15:28 +0200167 /* spare dmas for other usage */
168 /delete-property/dmas;
169 /delete-property/dma-names;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100170
Patrick Delaunaya3705302019-07-11 11:15:28 +0200171 pmic: stpmic@33 {
Patrick Delaunayd79218f2019-02-04 11:26:17 +0100172 compatible = "st,stpmic1";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100173 reg = <0x33>;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200174 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100175 interrupt-controller;
176 #interrupt-cells = <2>;
177 status = "okay";
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200178
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200179 regulators {
Patrick Delaunayd79218f2019-02-04 11:26:17 +0100180 compatible = "st,stpmic1-regulators";
Patrick Delaunay6d397052021-01-11 12:33:36 +0100181 buck1-supply = <&vin>;
182 buck2-supply = <&vin>;
183 buck3-supply = <&vin>;
184 buck4-supply = <&vin>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200185 ldo1-supply = <&v3v3>;
186 ldo2-supply = <&v3v3>;
187 ldo3-supply = <&vdd_ddr>;
Patrick Delaunay6d397052021-01-11 12:33:36 +0100188 ldo4-supply = <&vin>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200189 ldo5-supply = <&v3v3>;
190 ldo6-supply = <&v3v3>;
Patrick Delaunay6d397052021-01-11 12:33:36 +0100191 vref_ddr-supply = <&vin>;
192 boost-supply = <&vin>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200193 pwr_sw1-supply = <&bst_out>;
194 pwr_sw2-supply = <&bst_out>;
195
196 vddcore: buck1 {
197 regulator-name = "vddcore";
Patrick Delaunayb9c16b72020-01-28 10:11:00 +0100198 regulator-min-microvolt = <1200000>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200199 regulator-max-microvolt = <1350000>;
200 regulator-always-on;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200201 regulator-initial-mode = <0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200202 regulator-over-current-protection;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200203 };
204
205 vdd_ddr: buck2 {
206 regulator-name = "vdd_ddr";
207 regulator-min-microvolt = <1350000>;
208 regulator-max-microvolt = <1350000>;
209 regulator-always-on;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200210 regulator-initial-mode = <0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200211 regulator-over-current-protection;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200212 };
213
214 vdd: buck3 {
215 regulator-name = "vdd";
216 regulator-min-microvolt = <3300000>;
217 regulator-max-microvolt = <3300000>;
218 regulator-always-on;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200219 st,mask-reset;
220 regulator-initial-mode = <0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200221 regulator-over-current-protection;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200222 };
223
224 v3v3: buck4 {
225 regulator-name = "v3v3";
226 regulator-min-microvolt = <3300000>;
227 regulator-max-microvolt = <3300000>;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200228 regulator-always-on;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200229 regulator-over-current-protection;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200230 regulator-initial-mode = <0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200231 };
232
233 vdda: ldo1 {
234 regulator-name = "vdda";
235 regulator-min-microvolt = <2900000>;
236 regulator-max-microvolt = <2900000>;
237 interrupts = <IT_CURLIM_LDO1 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200238 };
239
240 v2v8: ldo2 {
241 regulator-name = "v2v8";
242 regulator-min-microvolt = <2800000>;
243 regulator-max-microvolt = <2800000>;
244 interrupts = <IT_CURLIM_LDO2 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200245 };
246
247 vtt_ddr: ldo3 {
248 regulator-name = "vtt_ddr";
Patrick Delaunaya3705302019-07-11 11:15:28 +0200249 regulator-min-microvolt = <500000>;
250 regulator-max-microvolt = <750000>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200251 regulator-always-on;
252 regulator-over-current-protection;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200253 };
254
255 vdd_usb: ldo4 {
256 regulator-name = "vdd_usb";
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200257 interrupts = <IT_CURLIM_LDO4 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200258 };
259
260 vdd_sd: ldo5 {
261 regulator-name = "vdd_sd";
262 regulator-min-microvolt = <2900000>;
263 regulator-max-microvolt = <2900000>;
264 interrupts = <IT_CURLIM_LDO5 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200265 regulator-boot-on;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200266 };
267
268 v1v8: ldo6 {
269 regulator-name = "v1v8";
270 regulator-min-microvolt = <1800000>;
271 regulator-max-microvolt = <1800000>;
272 interrupts = <IT_CURLIM_LDO6 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200273 };
274
275 vref_ddr: vref_ddr {
276 regulator-name = "vref_ddr";
277 regulator-always-on;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200278 };
279
Patrick Delaunayc5c90692019-11-06 16:16:32 +0100280 bst_out: boost {
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200281 regulator-name = "bst_out";
282 interrupts = <IT_OCP_BOOST 0>;
Patrick Delaunayc5c90692019-11-06 16:16:32 +0100283 };
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200284
285 vbus_otg: pwr_sw1 {
286 regulator-name = "vbus_otg";
287 interrupts = <IT_OCP_OTG 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200288 };
289
290 vbus_sw: pwr_sw2 {
291 regulator-name = "vbus_sw";
292 interrupts = <IT_OCP_SWOUT 0>;
Patrick Delaunayb9c16b72020-01-28 10:11:00 +0100293 regulator-active-discharge = <1>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200294 };
295 };
Patrick Delaunaya3705302019-07-11 11:15:28 +0200296
297 onkey {
298 compatible = "st,stpmic1-onkey";
299 interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
300 interrupt-names = "onkey-falling", "onkey-rising";
301 power-off-time-sec = <10>;
302 status = "okay";
303 };
304
305 watchdog {
306 compatible = "st,stpmic1-wdt";
307 status = "disabled";
308 };
Patrick Delaunay06020d82018-03-12 10:46:17 +0100309 };
310};
311
Fabien Dessennec2a97d32019-05-14 11:20:37 +0200312&ipcc {
313 status = "okay";
314};
315
Patrice Chotard00442d02019-02-12 16:50:38 +0100316&iwdg2 {
317 timeout-sec = <32>;
318 status = "okay";
319};
320
Patrick Delaunay26c24b42019-08-02 15:07:18 +0200321&m4_rproc {
Patrick Delaunay8c6e6132019-11-06 16:16:33 +0100322 memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
323 <&vdev0vring1>, <&vdev0buffer>;
Patrick Delaunayc4c5c5f2021-10-21 11:54:11 +0200324 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
325 mbox-names = "vq0", "vq1", "shutdown", "detach";
Patrick Delaunay8c6e6132019-11-06 16:16:33 +0100326 interrupt-parent = <&exti>;
327 interrupts = <68 1>;
Patrick Delaunay26c24b42019-08-02 15:07:18 +0200328 status = "okay";
329};
330
Patrick Delaunay900494d2020-01-28 10:10:59 +0100331&pwr_regulators {
332 vdd-supply = <&vdd>;
333 vdd_3v3_usbfs-supply = <&vdd_usb>;
Patrick Delaunay50599142018-07-09 15:17:19 +0200334};
335
Patrice Chotard00442d02019-02-12 16:50:38 +0100336&rng1 {
337 status = "okay";
338};
339
340&rtc {
341 status = "okay";
342};
343
Patrick Delaunay06020d82018-03-12 10:46:17 +0100344&sdmmc1 {
Patrick Delaunaya3705302019-07-11 11:15:28 +0200345 pinctrl-names = "default", "opendrain", "sleep";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100346 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200347 pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
348 pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200349 cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
350 disable-wp;
Patrice Chotard882d72e2019-02-12 17:17:58 +0100351 st,sig-dir;
352 st,neg-edge;
353 st,use-ckin;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100354 bus-width = <4>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200355 vmmc-supply = <&vdd_sd>;
356 vqmmc-supply = <&sd_switch>;
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200357 sd-uhs-sdr12;
358 sd-uhs-sdr25;
359 sd-uhs-sdr50;
360 sd-uhs-ddr50;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100361 status = "okay";
362};
363
Patrick Delaunay8d050102018-03-20 10:54:52 +0100364&sdmmc2 {
Patrick Delaunay2b0bbf52019-11-06 16:16:34 +0100365 pinctrl-names = "default", "opendrain", "sleep";
Patrick Delaunay8d050102018-03-20 10:54:52 +0100366 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
Patrick Delaunay2b0bbf52019-11-06 16:16:34 +0100367 pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
368 pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
Patrick Delaunay8d050102018-03-20 10:54:52 +0100369 non-removable;
370 no-sd;
371 no-sdio;
Patrice Chotard882d72e2019-02-12 17:17:58 +0100372 st,neg-edge;
Patrick Delaunay8d050102018-03-20 10:54:52 +0100373 bus-width = <8>;
Patrick Delaunay50599142018-07-09 15:17:19 +0200374 vmmc-supply = <&v3v3>;
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200375 vqmmc-supply = <&vdd>;
Patrick Delaunay2b0bbf52019-11-06 16:16:34 +0100376 mmc-ddr-3_3v;
Patrick Delaunay8d050102018-03-20 10:54:52 +0100377 status = "okay";
378};
379
Patrice Chotard00442d02019-02-12 16:50:38 +0100380&timers6 {
381 status = "okay";
Patrick Delaunaya3705302019-07-11 11:15:28 +0200382 /* spare dmas for other usage */
383 /delete-property/dmas;
384 /delete-property/dma-names;
Patrice Chotard00442d02019-02-12 16:50:38 +0100385 timer@5 {
386 status = "okay";
387 };
388};
389
Patrick Delaunay06020d82018-03-12 10:46:17 +0100390&uart4 {
Patrick Delaunay551efca2020-09-16 10:01:32 +0200391 pinctrl-names = "default", "sleep", "idle";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100392 pinctrl-0 = <&uart4_pins_a>;
Patrick Delaunay551efca2020-09-16 10:01:32 +0200393 pinctrl-1 = <&uart4_sleep_pins_a>;
394 pinctrl-2 = <&uart4_idle_pins_a>;
Patrick Delaunay6f182192022-04-26 15:38:05 +0200395 /delete-property/dmas;
396 /delete-property/dma-names;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100397 status = "okay";
398};
Patrick Delaunay50599142018-07-09 15:17:19 +0200399
Patrick Delaunaya3705302019-07-11 11:15:28 +0200400&usbotg_hs {
401 vbus-supply = <&vbus_otg>;
402};
403
Patrick Delaunay50599142018-07-09 15:17:19 +0200404&usbphyc_port0 {
405 phy-supply = <&vdd_usb>;
Patrick Delaunay50599142018-07-09 15:17:19 +0200406};
407
408&usbphyc_port1 {
409 phy-supply = <&vdd_usb>;
Patrick Delaunay50599142018-07-09 15:17:19 +0200410};