Patrick Delaunay | c5c9069 | 2019-11-06 16:16:32 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> |
| 4 | * |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 7 | #include "armv7-m.dtsi" |
Patrice Chotard | 0dca06e | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 8 | #include <dt-bindings/clock/stm32h7-clks.h> |
Patrice Chotard | 17ed194 | 2017-10-03 15:54:56 +0200 | [diff] [blame] | 9 | #include <dt-bindings/mfd/stm32h7-rcc.h> |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 10 | #include <dt-bindings/interrupt-controller/irq.h> |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 11 | |
| 12 | / { |
Patrick Delaunay | c5c9069 | 2019-11-06 16:16:32 +0100 | [diff] [blame] | 13 | #address-cells = <1>; |
| 14 | #size-cells = <1>; |
| 15 | |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 16 | clocks { |
| 17 | clk_hse: clk-hse { |
| 18 | #clock-cells = <0>; |
| 19 | compatible = "fixed-clock"; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 20 | clock-frequency = <0>; |
Patrice Chotard | 0dca06e | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 21 | }; |
| 22 | |
| 23 | clk_lse: clk-lse { |
| 24 | #clock-cells = <0>; |
| 25 | compatible = "fixed-clock"; |
| 26 | clock-frequency = <32768>; |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 27 | }; |
| 28 | |
Patrice Chotard | 0dca06e | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 29 | clk_i2s: i2s_ckin { |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 30 | #clock-cells = <0>; |
| 31 | compatible = "fixed-clock"; |
Patrice Chotard | 0dca06e | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 32 | clock-frequency = <0>; |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 33 | }; |
| 34 | }; |
| 35 | |
| 36 | soc { |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 37 | timer5: timer@40000c00 { |
| 38 | compatible = "st,stm32-timer"; |
| 39 | reg = <0x40000c00 0x400>; |
| 40 | interrupts = <50>; |
| 41 | clocks = <&rcc TIM5_CK>; |
Patrice Chotard | 0dca06e | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 42 | }; |
| 43 | |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 44 | lptimer1: timer@40002400 { |
| 45 | #address-cells = <1>; |
| 46 | #size-cells = <0>; |
| 47 | compatible = "st,stm32-lptimer"; |
| 48 | reg = <0x40002400 0x400>; |
| 49 | clocks = <&rcc LPTIM1_CK>; |
| 50 | clock-names = "mux"; |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 51 | status = "disabled"; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 52 | |
| 53 | pwm { |
| 54 | compatible = "st,stm32-pwm-lp"; |
| 55 | #pwm-cells = <3>; |
| 56 | status = "disabled"; |
| 57 | }; |
| 58 | |
| 59 | trigger@0 { |
| 60 | compatible = "st,stm32-lptimer-trigger"; |
| 61 | reg = <0>; |
| 62 | status = "disabled"; |
| 63 | }; |
| 64 | |
| 65 | counter { |
| 66 | compatible = "st,stm32-lptimer-counter"; |
| 67 | status = "disabled"; |
| 68 | }; |
| 69 | }; |
| 70 | |
| 71 | spi2: spi@40003800 { |
| 72 | #address-cells = <1>; |
| 73 | #size-cells = <0>; |
| 74 | compatible = "st,stm32h7-spi"; |
| 75 | reg = <0x40003800 0x400>; |
| 76 | interrupts = <36>; |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 77 | resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 78 | clocks = <&rcc SPI2_CK>; |
| 79 | status = "disabled"; |
| 80 | |
| 81 | }; |
| 82 | |
| 83 | spi3: spi@40003c00 { |
| 84 | #address-cells = <1>; |
| 85 | #size-cells = <0>; |
| 86 | compatible = "st,stm32h7-spi"; |
| 87 | reg = <0x40003c00 0x400>; |
| 88 | interrupts = <51>; |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 89 | resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 90 | clocks = <&rcc SPI3_CK>; |
| 91 | status = "disabled"; |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | usart2: serial@40004400 { |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 95 | compatible = "st,stm32h7-uart"; |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 96 | reg = <0x40004400 0x400>; |
| 97 | interrupts = <38>; |
| 98 | status = "disabled"; |
Patrice Chotard | 0dca06e | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 99 | clocks = <&rcc USART2_CK>; |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 100 | }; |
| 101 | |
dillon min | 5d90198 | 2021-04-09 15:28:42 +0800 | [diff] [blame] | 102 | usart3: serial@40004800 { |
| 103 | compatible = "st,stm32h7-uart"; |
| 104 | reg = <0x40004800 0x400>; |
| 105 | interrupts = <39>; |
| 106 | status = "disabled"; |
| 107 | clocks = <&rcc USART3_CK>; |
| 108 | }; |
| 109 | |
| 110 | uart4: serial@40004c00 { |
| 111 | compatible = "st,stm32h7-uart"; |
| 112 | reg = <0x40004c00 0x400>; |
| 113 | interrupts = <52>; |
| 114 | status = "disabled"; |
| 115 | clocks = <&rcc UART4_CK>; |
| 116 | }; |
| 117 | |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 118 | i2c1: i2c@40005400 { |
| 119 | compatible = "st,stm32f7-i2c"; |
| 120 | #address-cells = <1>; |
| 121 | #size-cells = <0>; |
| 122 | reg = <0x40005400 0x400>; |
| 123 | interrupts = <31>, |
| 124 | <32>; |
| 125 | resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; |
| 126 | clocks = <&rcc I2C1_CK>; |
Patrice Chotard | 2146e9e | 2021-08-03 12:05:11 +0200 | [diff] [blame] | 127 | i2c-analog-filter; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 128 | status = "disabled"; |
| 129 | }; |
| 130 | |
| 131 | i2c2: i2c@40005800 { |
| 132 | compatible = "st,stm32f7-i2c"; |
| 133 | #address-cells = <1>; |
| 134 | #size-cells = <0>; |
| 135 | reg = <0x40005800 0x400>; |
| 136 | interrupts = <33>, |
| 137 | <34>; |
| 138 | resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; |
| 139 | clocks = <&rcc I2C2_CK>; |
Patrice Chotard | 2146e9e | 2021-08-03 12:05:11 +0200 | [diff] [blame] | 140 | i2c-analog-filter; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 141 | status = "disabled"; |
| 142 | }; |
| 143 | |
dillon min | a5dc7a1 | 2021-04-09 15:28:43 +0800 | [diff] [blame] | 144 | i2c3: i2c@40005c00 { |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 145 | compatible = "st,stm32f7-i2c"; |
| 146 | #address-cells = <1>; |
| 147 | #size-cells = <0>; |
| 148 | reg = <0x40005C00 0x400>; |
| 149 | interrupts = <72>, |
| 150 | <73>; |
| 151 | resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; |
| 152 | clocks = <&rcc I2C3_CK>; |
Patrice Chotard | 2146e9e | 2021-08-03 12:05:11 +0200 | [diff] [blame] | 153 | i2c-analog-filter; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 154 | status = "disabled"; |
| 155 | }; |
| 156 | |
| 157 | dac: dac@40007400 { |
| 158 | compatible = "st,stm32h7-dac-core"; |
| 159 | reg = <0x40007400 0x400>; |
| 160 | clocks = <&rcc DAC12_CK>; |
| 161 | clock-names = "pclk"; |
| 162 | #address-cells = <1>; |
| 163 | #size-cells = <0>; |
| 164 | status = "disabled"; |
| 165 | |
| 166 | dac1: dac@1 { |
| 167 | compatible = "st,stm32-dac"; |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 168 | #io-channel-cells = <1>; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 169 | reg = <1>; |
| 170 | status = "disabled"; |
| 171 | }; |
| 172 | |
| 173 | dac2: dac@2 { |
| 174 | compatible = "st,stm32-dac"; |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 175 | #io-channel-cells = <1>; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 176 | reg = <2>; |
| 177 | status = "disabled"; |
| 178 | }; |
| 179 | }; |
| 180 | |
| 181 | usart1: serial@40011000 { |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 182 | compatible = "st,stm32h7-uart"; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 183 | reg = <0x40011000 0x400>; |
| 184 | interrupts = <37>; |
| 185 | status = "disabled"; |
| 186 | clocks = <&rcc USART1_CK>; |
| 187 | }; |
| 188 | |
| 189 | spi1: spi@40013000 { |
| 190 | #address-cells = <1>; |
| 191 | #size-cells = <0>; |
| 192 | compatible = "st,stm32h7-spi"; |
| 193 | reg = <0x40013000 0x400>; |
| 194 | interrupts = <35>; |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 195 | resets = <&rcc STM32H7_APB2_RESET(SPI1)>; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 196 | clocks = <&rcc SPI1_CK>; |
| 197 | status = "disabled"; |
| 198 | }; |
| 199 | |
| 200 | spi4: spi@40013400 { |
| 201 | #address-cells = <1>; |
| 202 | #size-cells = <0>; |
| 203 | compatible = "st,stm32h7-spi"; |
| 204 | reg = <0x40013400 0x400>; |
| 205 | interrupts = <84>; |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 206 | resets = <&rcc STM32H7_APB2_RESET(SPI4)>; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 207 | clocks = <&rcc SPI4_CK>; |
| 208 | status = "disabled"; |
| 209 | }; |
| 210 | |
| 211 | spi5: spi@40015000 { |
| 212 | #address-cells = <1>; |
| 213 | #size-cells = <0>; |
| 214 | compatible = "st,stm32h7-spi"; |
| 215 | reg = <0x40015000 0x400>; |
| 216 | interrupts = <85>; |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 217 | resets = <&rcc STM32H7_APB2_RESET(SPI5)>; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 218 | clocks = <&rcc SPI5_CK>; |
| 219 | status = "disabled"; |
| 220 | }; |
| 221 | |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 222 | dma1: dma-controller@40020000 { |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 223 | compatible = "st,stm32-dma"; |
| 224 | reg = <0x40020000 0x400>; |
| 225 | interrupts = <11>, |
| 226 | <12>, |
| 227 | <13>, |
| 228 | <14>, |
| 229 | <15>, |
| 230 | <16>, |
| 231 | <17>, |
| 232 | <47>; |
| 233 | clocks = <&rcc DMA1_CK>; |
| 234 | #dma-cells = <4>; |
| 235 | st,mem2mem; |
| 236 | dma-requests = <8>; |
| 237 | status = "disabled"; |
| 238 | }; |
| 239 | |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 240 | dma2: dma-controller@40020400 { |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 241 | compatible = "st,stm32-dma"; |
| 242 | reg = <0x40020400 0x400>; |
| 243 | interrupts = <56>, |
| 244 | <57>, |
| 245 | <58>, |
| 246 | <59>, |
| 247 | <60>, |
| 248 | <68>, |
| 249 | <69>, |
| 250 | <70>; |
| 251 | clocks = <&rcc DMA2_CK>; |
| 252 | #dma-cells = <4>; |
| 253 | st,mem2mem; |
| 254 | dma-requests = <8>; |
| 255 | status = "disabled"; |
Patrice Chotard | 0dca06e | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 256 | }; |
| 257 | |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 258 | dmamux1: dma-router@40020800 { |
| 259 | compatible = "st,stm32h7-dmamux"; |
dillon min | a5dc7a1 | 2021-04-09 15:28:43 +0800 | [diff] [blame] | 260 | reg = <0x40020800 0x40>; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 261 | #dma-cells = <3>; |
| 262 | dma-channels = <16>; |
| 263 | dma-requests = <128>; |
| 264 | dma-masters = <&dma1 &dma2>; |
| 265 | clocks = <&rcc DMA1_CK>; |
| 266 | }; |
| 267 | |
| 268 | adc_12: adc@40022000 { |
| 269 | compatible = "st,stm32h7-adc-core"; |
| 270 | reg = <0x40022000 0x400>; |
| 271 | interrupts = <18>; |
| 272 | clocks = <&rcc ADC12_CK>; |
| 273 | clock-names = "bus"; |
| 274 | interrupt-controller; |
| 275 | #interrupt-cells = <1>; |
| 276 | #address-cells = <1>; |
| 277 | #size-cells = <0>; |
| 278 | status = "disabled"; |
| 279 | |
| 280 | adc1: adc@0 { |
| 281 | compatible = "st,stm32h7-adc"; |
| 282 | #io-channel-cells = <1>; |
| 283 | reg = <0x0>; |
| 284 | interrupt-parent = <&adc_12>; |
| 285 | interrupts = <0>; |
| 286 | status = "disabled"; |
| 287 | }; |
| 288 | |
| 289 | adc2: adc@100 { |
| 290 | compatible = "st,stm32h7-adc"; |
| 291 | #io-channel-cells = <1>; |
| 292 | reg = <0x100>; |
| 293 | interrupt-parent = <&adc_12>; |
| 294 | interrupts = <1>; |
| 295 | status = "disabled"; |
| 296 | }; |
| 297 | }; |
| 298 | |
| 299 | usbotg_hs: usb@40040000 { |
| 300 | compatible = "st,stm32f7-hsotg"; |
| 301 | reg = <0x40040000 0x40000>; |
| 302 | interrupts = <77>; |
| 303 | clocks = <&rcc USB1OTG_CK>; |
| 304 | clock-names = "otg"; |
| 305 | g-rx-fifo-size = <256>; |
| 306 | g-np-tx-fifo-size = <32>; |
| 307 | g-tx-fifo-size = <128 128 64 64 64 64 32 32>; |
| 308 | status = "disabled"; |
| 309 | }; |
| 310 | |
| 311 | usbotg_fs: usb@40080000 { |
| 312 | compatible = "st,stm32f4x9-fsotg"; |
| 313 | reg = <0x40080000 0x40000>; |
| 314 | interrupts = <101>; |
| 315 | clocks = <&rcc USB2OTG_CK>; |
| 316 | clock-names = "otg"; |
| 317 | status = "disabled"; |
| 318 | }; |
| 319 | |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 320 | ltdc: display-controller@50001000 { |
| 321 | compatible = "st,stm32-ltdc"; |
| 322 | reg = <0x50001000 0x200>; |
| 323 | interrupts = <88>, <89>; |
| 324 | resets = <&rcc STM32H7_APB3_RESET(LTDC)>; |
| 325 | clocks = <&rcc LTDC_CK>; |
| 326 | clock-names = "lcd"; |
| 327 | status = "disabled"; |
| 328 | }; |
| 329 | |
| 330 | mdma1: dma-controller@52000000 { |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 331 | compatible = "st,stm32h7-mdma"; |
| 332 | reg = <0x52000000 0x1000>; |
| 333 | interrupts = <122>; |
| 334 | clocks = <&rcc MDMA_CK>; |
| 335 | #dma-cells = <5>; |
| 336 | dma-channels = <16>; |
| 337 | dma-requests = <32>; |
| 338 | }; |
| 339 | |
Patrick Delaunay | c5c9069 | 2019-11-06 16:16:32 +0100 | [diff] [blame] | 340 | sdmmc1: sdmmc@52007000 { |
| 341 | compatible = "arm,pl18x", "arm,primecell"; |
| 342 | arm,primecell-periphid = <0x10153180>; |
| 343 | reg = <0x52007000 0x1000>; |
| 344 | interrupts = <49>; |
| 345 | interrupt-names = "cmd_irq"; |
| 346 | clocks = <&rcc SDMMC1_CK>; |
| 347 | clock-names = "apb_pclk"; |
| 348 | resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; |
| 349 | cap-sd-highspeed; |
| 350 | cap-mmc-highspeed; |
| 351 | max-frequency = <120000000>; |
| 352 | }; |
| 353 | |
dillon min | 5d90198 | 2021-04-09 15:28:42 +0800 | [diff] [blame] | 354 | sdmmc2: sdmmc@48022400 { |
| 355 | compatible = "arm,pl18x", "arm,primecell"; |
| 356 | arm,primecell-periphid = <0x10153180>; |
| 357 | reg = <0x48022400 0x400>; |
| 358 | interrupts = <124>; |
| 359 | interrupt-names = "cmd_irq"; |
| 360 | clocks = <&rcc SDMMC2_CK>; |
| 361 | clock-names = "apb_pclk"; |
| 362 | resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; |
| 363 | cap-sd-highspeed; |
| 364 | cap-mmc-highspeed; |
| 365 | max-frequency = <120000000>; |
| 366 | }; |
| 367 | |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 368 | exti: interrupt-controller@58000000 { |
| 369 | compatible = "st,stm32h7-exti"; |
| 370 | interrupt-controller; |
| 371 | #interrupt-cells = <2>; |
| 372 | reg = <0x58000000 0x400>; |
| 373 | interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; |
| 374 | }; |
| 375 | |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 376 | syscfg: syscon@58000400 { |
| 377 | compatible = "st,stm32-syscfg", "syscon"; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 378 | reg = <0x58000400 0x400>; |
| 379 | }; |
| 380 | |
| 381 | spi6: spi@58001400 { |
| 382 | #address-cells = <1>; |
| 383 | #size-cells = <0>; |
| 384 | compatible = "st,stm32h7-spi"; |
| 385 | reg = <0x58001400 0x400>; |
| 386 | interrupts = <86>; |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 387 | resets = <&rcc STM32H7_APB4_RESET(SPI6)>; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 388 | clocks = <&rcc SPI6_CK>; |
| 389 | status = "disabled"; |
| 390 | }; |
| 391 | |
dillon min | a5dc7a1 | 2021-04-09 15:28:43 +0800 | [diff] [blame] | 392 | i2c4: i2c@58001c00 { |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 393 | compatible = "st,stm32f7-i2c"; |
| 394 | #address-cells = <1>; |
| 395 | #size-cells = <0>; |
| 396 | reg = <0x58001C00 0x400>; |
| 397 | interrupts = <95>, |
| 398 | <96>; |
| 399 | resets = <&rcc STM32H7_APB4_RESET(I2C4)>; |
| 400 | clocks = <&rcc I2C4_CK>; |
Patrice Chotard | 2146e9e | 2021-08-03 12:05:11 +0200 | [diff] [blame] | 401 | i2c-analog-filter; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 402 | status = "disabled"; |
| 403 | }; |
| 404 | |
| 405 | lptimer2: timer@58002400 { |
| 406 | #address-cells = <1>; |
| 407 | #size-cells = <0>; |
| 408 | compatible = "st,stm32-lptimer"; |
| 409 | reg = <0x58002400 0x400>; |
| 410 | clocks = <&rcc LPTIM2_CK>; |
| 411 | clock-names = "mux"; |
| 412 | status = "disabled"; |
| 413 | |
| 414 | pwm { |
| 415 | compatible = "st,stm32-pwm-lp"; |
| 416 | #pwm-cells = <3>; |
| 417 | status = "disabled"; |
| 418 | }; |
| 419 | |
| 420 | trigger@1 { |
| 421 | compatible = "st,stm32-lptimer-trigger"; |
| 422 | reg = <1>; |
| 423 | status = "disabled"; |
| 424 | }; |
| 425 | |
| 426 | counter { |
| 427 | compatible = "st,stm32-lptimer-counter"; |
| 428 | status = "disabled"; |
| 429 | }; |
| 430 | }; |
| 431 | |
| 432 | lptimer3: timer@58002800 { |
| 433 | #address-cells = <1>; |
| 434 | #size-cells = <0>; |
| 435 | compatible = "st,stm32-lptimer"; |
| 436 | reg = <0x58002800 0x400>; |
| 437 | clocks = <&rcc LPTIM3_CK>; |
| 438 | clock-names = "mux"; |
| 439 | status = "disabled"; |
| 440 | |
| 441 | pwm { |
| 442 | compatible = "st,stm32-pwm-lp"; |
| 443 | #pwm-cells = <3>; |
| 444 | status = "disabled"; |
| 445 | }; |
| 446 | |
| 447 | trigger@2 { |
| 448 | compatible = "st,stm32-lptimer-trigger"; |
| 449 | reg = <2>; |
| 450 | status = "disabled"; |
| 451 | }; |
| 452 | }; |
| 453 | |
| 454 | lptimer4: timer@58002c00 { |
| 455 | #address-cells = <1>; |
| 456 | #size-cells = <0>; |
| 457 | compatible = "st,stm32-lptimer"; |
| 458 | reg = <0x58002c00 0x400>; |
| 459 | clocks = <&rcc LPTIM4_CK>; |
| 460 | clock-names = "mux"; |
| 461 | status = "disabled"; |
| 462 | |
| 463 | pwm { |
| 464 | compatible = "st,stm32-pwm-lp"; |
| 465 | #pwm-cells = <3>; |
| 466 | status = "disabled"; |
| 467 | }; |
| 468 | }; |
| 469 | |
| 470 | lptimer5: timer@58003000 { |
| 471 | #address-cells = <1>; |
| 472 | #size-cells = <0>; |
| 473 | compatible = "st,stm32-lptimer"; |
| 474 | reg = <0x58003000 0x400>; |
| 475 | clocks = <&rcc LPTIM5_CK>; |
| 476 | clock-names = "mux"; |
| 477 | status = "disabled"; |
| 478 | |
| 479 | pwm { |
| 480 | compatible = "st,stm32-pwm-lp"; |
| 481 | #pwm-cells = <3>; |
| 482 | status = "disabled"; |
| 483 | }; |
| 484 | }; |
| 485 | |
| 486 | vrefbuf: regulator@58003c00 { |
| 487 | compatible = "st,stm32-vrefbuf"; |
| 488 | reg = <0x58003C00 0x8>; |
| 489 | clocks = <&rcc VREF_CK>; |
| 490 | regulator-min-microvolt = <1500000>; |
| 491 | regulator-max-microvolt = <2500000>; |
| 492 | status = "disabled"; |
| 493 | }; |
| 494 | |
| 495 | rtc: rtc@58004000 { |
| 496 | compatible = "st,stm32h7-rtc"; |
| 497 | reg = <0x58004000 0x400>; |
| 498 | clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; |
| 499 | clock-names = "pclk", "rtc_ck"; |
| 500 | assigned-clocks = <&rcc RTC_CK>; |
| 501 | assigned-clock-parents = <&rcc LSE_CK>; |
| 502 | interrupt-parent = <&exti>; |
| 503 | interrupts = <17 IRQ_TYPE_EDGE_RISING>; |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 504 | st,syscfg = <&pwrcfg 0x00 0x100>; |
| 505 | status = "disabled"; |
| 506 | }; |
| 507 | |
| 508 | rcc: reset-clock-controller@58024400 { |
| 509 | compatible = "st,stm32h743-rcc", "st,stm32-rcc"; |
| 510 | reg = <0x58024400 0x400>; |
| 511 | #clock-cells = <1>; |
| 512 | #reset-cells = <1>; |
| 513 | clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; |
| 514 | st,syscfg = <&pwrcfg>; |
| 515 | }; |
| 516 | |
Patrice Chotard | 0dca06e | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 517 | pwrcfg: power-config@58024800 { |
Patrice Chotard | 62f5616 | 2020-11-06 08:11:58 +0100 | [diff] [blame] | 518 | compatible = "st,stm32-power-config", "syscon"; |
Patrice Chotard | 0dca06e | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 519 | reg = <0x58024800 0x400>; |
| 520 | }; |
| 521 | |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 522 | adc_3: adc@58026000 { |
| 523 | compatible = "st,stm32h7-adc-core"; |
| 524 | reg = <0x58026000 0x400>; |
| 525 | interrupts = <127>; |
| 526 | clocks = <&rcc ADC3_CK>; |
| 527 | clock-names = "bus"; |
| 528 | interrupt-controller; |
| 529 | #interrupt-cells = <1>; |
| 530 | #address-cells = <1>; |
| 531 | #size-cells = <0>; |
| 532 | status = "disabled"; |
Patrice Chotard | 0dca06e | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 533 | |
Patrice Chotard | 044d7af | 2018-12-06 11:53:39 +0100 | [diff] [blame] | 534 | adc3: adc@0 { |
| 535 | compatible = "st,stm32h7-adc"; |
| 536 | #io-channel-cells = <1>; |
| 537 | reg = <0x0>; |
| 538 | interrupt-parent = <&adc_3>; |
| 539 | interrupts = <0>; |
| 540 | status = "disabled"; |
| 541 | }; |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 542 | }; |
Patrick Delaunay | c5c9069 | 2019-11-06 16:16:32 +0100 | [diff] [blame] | 543 | |
| 544 | mac: ethernet@40028000 { |
| 545 | compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; |
| 546 | reg = <0x40028000 0x8000>; |
| 547 | reg-names = "stmmaceth"; |
| 548 | interrupts = <61>; |
| 549 | interrupt-names = "macirq"; |
| 550 | clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; |
| 551 | clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>; |
| 552 | st,syscon = <&syscfg 0x4>; |
| 553 | snps,pbl = <8>; |
| 554 | status = "disabled"; |
| 555 | }; |
dillon min | 75a81de | 2021-04-09 15:28:41 +0800 | [diff] [blame] | 556 | |
| 557 | pinctrl: pin-controller@58020000 { |
| 558 | #address-cells = <1>; |
| 559 | #size-cells = <1>; |
| 560 | compatible = "st,stm32h743-pinctrl"; |
| 561 | ranges = <0 0x58020000 0x3000>; |
| 562 | interrupt-parent = <&exti>; |
| 563 | st,syscfg = <&syscfg 0x8>; |
| 564 | pins-are-numbered; |
| 565 | |
| 566 | gpioa: gpio@58020000 { |
| 567 | gpio-controller; |
| 568 | #gpio-cells = <2>; |
| 569 | reg = <0x0 0x400>; |
| 570 | clocks = <&rcc GPIOA_CK>; |
| 571 | st,bank-name = "GPIOA"; |
| 572 | interrupt-controller; |
| 573 | #interrupt-cells = <2>; |
| 574 | ngpios = <16>; |
| 575 | gpio-ranges = <&pinctrl 0 0 16>; |
| 576 | }; |
| 577 | |
| 578 | gpiob: gpio@58020400 { |
| 579 | gpio-controller; |
| 580 | #gpio-cells = <2>; |
| 581 | reg = <0x400 0x400>; |
| 582 | clocks = <&rcc GPIOB_CK>; |
| 583 | st,bank-name = "GPIOB"; |
| 584 | interrupt-controller; |
| 585 | #interrupt-cells = <2>; |
| 586 | ngpios = <16>; |
| 587 | gpio-ranges = <&pinctrl 0 16 16>; |
| 588 | }; |
| 589 | |
| 590 | gpioc: gpio@58020800 { |
| 591 | gpio-controller; |
| 592 | #gpio-cells = <2>; |
| 593 | reg = <0x800 0x400>; |
| 594 | clocks = <&rcc GPIOC_CK>; |
| 595 | st,bank-name = "GPIOC"; |
| 596 | interrupt-controller; |
| 597 | #interrupt-cells = <2>; |
| 598 | ngpios = <16>; |
| 599 | gpio-ranges = <&pinctrl 0 32 16>; |
| 600 | }; |
| 601 | |
| 602 | gpiod: gpio@58020c00 { |
| 603 | gpio-controller; |
| 604 | #gpio-cells = <2>; |
| 605 | reg = <0xc00 0x400>; |
| 606 | clocks = <&rcc GPIOD_CK>; |
| 607 | st,bank-name = "GPIOD"; |
| 608 | interrupt-controller; |
| 609 | #interrupt-cells = <2>; |
| 610 | ngpios = <16>; |
| 611 | gpio-ranges = <&pinctrl 0 48 16>; |
| 612 | }; |
| 613 | |
| 614 | gpioe: gpio@58021000 { |
| 615 | gpio-controller; |
| 616 | #gpio-cells = <2>; |
| 617 | reg = <0x1000 0x400>; |
| 618 | clocks = <&rcc GPIOE_CK>; |
| 619 | st,bank-name = "GPIOE"; |
| 620 | interrupt-controller; |
| 621 | #interrupt-cells = <2>; |
| 622 | ngpios = <16>; |
| 623 | gpio-ranges = <&pinctrl 0 64 16>; |
| 624 | }; |
| 625 | |
| 626 | gpiof: gpio@58021400 { |
| 627 | gpio-controller; |
| 628 | #gpio-cells = <2>; |
| 629 | reg = <0x1400 0x400>; |
| 630 | clocks = <&rcc GPIOF_CK>; |
| 631 | st,bank-name = "GPIOF"; |
| 632 | interrupt-controller; |
| 633 | #interrupt-cells = <2>; |
| 634 | ngpios = <16>; |
| 635 | gpio-ranges = <&pinctrl 0 80 16>; |
| 636 | }; |
| 637 | |
| 638 | gpiog: gpio@58021800 { |
| 639 | gpio-controller; |
| 640 | #gpio-cells = <2>; |
| 641 | reg = <0x1800 0x400>; |
| 642 | clocks = <&rcc GPIOG_CK>; |
| 643 | st,bank-name = "GPIOG"; |
| 644 | interrupt-controller; |
| 645 | #interrupt-cells = <2>; |
| 646 | ngpios = <16>; |
| 647 | gpio-ranges = <&pinctrl 0 96 16>; |
| 648 | }; |
| 649 | |
| 650 | gpioh: gpio@58021c00 { |
| 651 | gpio-controller; |
| 652 | #gpio-cells = <2>; |
| 653 | reg = <0x1c00 0x400>; |
| 654 | clocks = <&rcc GPIOH_CK>; |
| 655 | st,bank-name = "GPIOH"; |
| 656 | interrupt-controller; |
| 657 | #interrupt-cells = <2>; |
| 658 | ngpios = <16>; |
| 659 | gpio-ranges = <&pinctrl 0 112 16>; |
| 660 | }; |
| 661 | |
| 662 | gpioi: gpio@58022000 { |
| 663 | gpio-controller; |
| 664 | #gpio-cells = <2>; |
| 665 | reg = <0x2000 0x400>; |
| 666 | clocks = <&rcc GPIOI_CK>; |
| 667 | st,bank-name = "GPIOI"; |
| 668 | interrupt-controller; |
| 669 | #interrupt-cells = <2>; |
| 670 | ngpios = <16>; |
| 671 | gpio-ranges = <&pinctrl 0 128 16>; |
| 672 | }; |
| 673 | |
| 674 | gpioj: gpio@58022400 { |
| 675 | gpio-controller; |
| 676 | #gpio-cells = <2>; |
| 677 | reg = <0x2400 0x400>; |
| 678 | clocks = <&rcc GPIOJ_CK>; |
| 679 | st,bank-name = "GPIOJ"; |
| 680 | interrupt-controller; |
| 681 | #interrupt-cells = <2>; |
| 682 | ngpios = <16>; |
| 683 | gpio-ranges = <&pinctrl 0 144 16>; |
| 684 | }; |
| 685 | |
| 686 | gpiok: gpio@58022800 { |
| 687 | gpio-controller; |
| 688 | #gpio-cells = <2>; |
| 689 | reg = <0x2800 0x400>; |
| 690 | clocks = <&rcc GPIOK_CK>; |
| 691 | st,bank-name = "GPIOK"; |
| 692 | interrupt-controller; |
| 693 | #interrupt-cells = <2>; |
| 694 | ngpios = <8>; |
| 695 | gpio-ranges = <&pinctrl 0 160 8>; |
| 696 | }; |
| 697 | }; |
Patrice Chotard | e4c6b78 | 2017-09-13 18:00:09 +0200 | [diff] [blame] | 698 | }; |
| 699 | }; |
| 700 | |
| 701 | &systick { |
| 702 | clock-frequency = <250000000>; |
| 703 | status = "okay"; |
| 704 | }; |