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git01.mediatek.com / filogic / uboot / 765f1edcf8d5a141cdd5a2eb421ab783d2250646 / . / arch / arm / dts / imxrt1020-evk.dts
blob: 22ae5ed73597ebc331c3c66bbe8b3c2d5792c370 [file] [log] [blame]
Giulio Benettid1203ca2020-02-18 20:02:55 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2020
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
7/dts-v1/;
8#include "imxrt1020.dtsi"
9#include "imxrt1020-evk-u-boot.dtsi"
Jesse Taube62394a72022-03-17 14:33:20 -0400[diff] [blame]10#include "imxrt1020-pinfunc.h"
Giulio Benettid1203ca2020-02-18 20:02:55 +0100[diff] [blame]11
12/ {
13 model = "NXP IMXRT1020-evk board";
14 compatible = "fsl,imxrt1020-evk", "fsl,imxrt1020";
15
16 chosen {
17 bootargs = "root=/dev/ram";
18 stdout-path = "serial0:115200n8";
Giulio Benetti0fe94c02021-05-13 12:18:35 +0200[diff] [blame]19 tick-timer = &gpt1;
Giulio Benettid1203ca2020-02-18 20:02:55 +0100[diff] [blame]20 };
21
22 memory {
Giulio Benetticd90a192021-05-13 12:18:37 +0200[diff] [blame]23 device_type = "memory";
Giulio Benettid1203ca2020-02-18 20:02:55 +0100[diff] [blame]24 reg = <0x80000000 0x2000000>;
25 };
26};
27
28&lpuart1 { /* console */
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_lpuart1>;
31 status = "okay";
32};
33
34&semc {
35 /*
36 * Memory configuration from sdram datasheet IS42S16160J-6TLI
37 */
38 fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
39 MUX_CSX0_SDRAM_CS1
40 0
41 0
42 0
43 0>;
44 fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
45 BL_8
46 COL_9BITS
47 CL_3>;
48 fsl,sdram-timing = /bits/ 8 <0x2
49 0x2
50 0x9
51 0x1
52 0x5
53 0x6
54
55 0x20
56 0x09
57 0x01
58 0x00
59
60 0x04
61 0x0A
62 0x21
63 0x50>;
64
65 bank1: bank@0 {
66 fsl,base-address = <0x80000000>;
67 fsl,memory-size = <MEM_SIZE_32M>;
68 };
69};
70
71&iomuxc {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_lpuart1>;
74
75 imxrt1020-evk {
76 pinctrl_lpuart1: lpuart1grp {
77 fsl,pins = <
78 MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX
79 0xf1
80 MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX
81 0xf1
82 >;
83 };
84
85 pinctrl_semc: semcgrp {
86 fsl,pins = <
87 MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
88 0xf1 /* SEMC_D0 */
89 MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
90 0xf1 /* SEMC_D1 */
91 MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
92 0xf1 /* SEMC_D2 */
93 MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
94 0xf1 /* SEMC_D3 */
95 MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
96 0xf1 /* SEMC_D4 */
97 MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
98 0xf1 /* SEMC_D5 */
99 MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
100 0xf1 /* SEMC_D6 */
101 MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
102 0xf1 /* SEMC_D7 */
103 MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00
104 0xf1 /* SEMC_DM0 */
105 MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
106 0xf1 /* SEMC_A0 */
107 MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS
108 0xf1 /* SEMC_CAS */
109 MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS
110 0xf1 /* SEMC_RAS */
111 MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0
112 0xf1 /* SEMC_CS0 */
113 MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0
114 0xf1 /* SEMC_BA0 */
115 MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1
116 0xf1 /* SEMC_BA1 */
117 MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10
118 0xf1 /* SEMC_A10 */
119 MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00
120 0xf1 /* SEMC_A0 */
121 MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01
122 0xf1 /* SEMC_A1 */
123 MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02
124 0xf1 /* SEMC_A2 */
125 MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03
126 0xf1 /* SEMC_A3 */
127 MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04
128 0xf1 /* SEMC_A4 */
129 MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05
130 0xf1 /* SEMC_A5 */
131 MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06
132 0xf1 /* SEMC_A6 */
133 MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07
134 0xf1 /* SEMC_A7 */
135 MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08
136 0xf1 /* SEMC_A8 */
137 MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09
138 0xf1 /* SEMC_A9 */
139 MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11
140 0xf1 /* SEMC_A11 */
141 MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12
142 0xf1 /* SEMC_A12 */
143 MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS
144 (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
145 MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE
146 0xf1 /* SEMC_CKE */
147 MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK
148 0xf1 /* SEMC_CLK */
149 MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01
150 0xf1 /* SEMC_DM01 */
151 MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08
152 0xf1 /* SEMC_D8 */
153 MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09
154 0xf1 /* SEMC_D9 */
155 MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10
156 0xf1 /* SEMC_D10 */
157 MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11
158 0xf1 /* SEMC_D11 */
159 MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12
160 0xf1 /* SEMC_D12 */
161 MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13
162 0xf1 /* SEMC_D13 */
163 MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14
164 0xf1 /* SEMC_D14 */
165 MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15
166 0xf1 /* SEMC_D15 */
167 >;
168 };
169
170 pinctrl_usdhc0: usdhc0grp {
171 fsl,pins = <
172 MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B
173 0x1B000
174 MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD
175 0x17061
176 MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK
177 0x17061
178 MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3
179 0x17061
180 MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2
181 0x17061
182 MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1
183 0x17061
184 MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0
185 0x17061
186 >;
187 };
188 };
189};
190
Giulio Benetti857330e2021-05-13 12:18:34 +0200[diff] [blame]191&gpt1 {
192 status = "okay";
193};
194
Giulio Benettid1203ca2020-02-18 20:02:55 +0100[diff] [blame]195&usdhc1 {
196 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
197 pinctrl-0 = <&pinctrl_usdhc0>;
198 pinctrl-1 = <&pinctrl_usdhc0>;
199 pinctrl-2 = <&pinctrl_usdhc0>;
200 pinctrl-3 = <&pinctrl_usdhc0>;
201 status = "okay";
202
203 cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
204};