| Anup Patel | 42fdf08 | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | config CLK_ANALOGBITS_WRPLL_CLN28HPC |
| 4 | bool |
| 5 | |
| 6 | config CLK_SIFIVE |
| 7 | bool "SiFive SoC driver support" |
| 8 | depends on CLK |
| 9 | help |
| 10 | SoC drivers for SiFive Linux-capable SoCs. |
| 11 | |
| 12 | config CLK_SIFIVE_FU540_PRCI |
| 13 | bool "PRCI driver for SiFive FU540 SoCs" |
| 14 | depends on CLK_SIFIVE |
| 15 | select CLK_ANALOGBITS_WRPLL_CLN28HPC |
| 16 | help |
| 17 | Supports the Power Reset Clock interface (PRCI) IP block found in |
| 18 | FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, |
| 19 | enable this driver. |
| Bin Meng | eb195bd | 2019-05-22 00:09:44 -0700 | [diff] [blame] | 20 | |
| 21 | config CLK_SIFIVE_GEMGXL_MGMT |
| 22 | bool "GEMGXL management for SiFive FU540 SoCs" |
| 23 | depends on CLK_SIFIVE |
| 24 | help |
| 25 | Supports the GEMGXL management IP block found in FU540 SoCs to |
| 26 | control GEM TX clock operation mode for 10/100/1000 Mbps. |