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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / ti / k3-am62-wakeup.dtsi
blob: 66ddf2dc51afa7870a27ebabac19799726a834aa [file] [log] [blame]
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only OR MIT
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2/*
3 * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
4 *
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]6 */
7
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]8#include <dt-bindings/bus/ti-sysc.h>
9
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]10&cbass_wakeup {
11 wkup_conf: syscon@43000000 {
12 bootph-all;
13 compatible = "syscon", "simple-mfd";
14 reg = <0x00 0x43000000 0x00 0x20000>;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges = <0x0 0x00 0x43000000 0x20000>;
18
19 chipid: chipid@14 {
20 bootph-all;
21 compatible = "ti,am654-chipid";
22 reg = <0x14 0x4>;
23 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame^]24
25 usb0_phy_ctrl: syscon@4008 {
26 compatible = "ti,am62-usb-phy-ctrl", "syscon";
27 reg = <0x4008 0x4>;
28 };
29
30 usb1_phy_ctrl: syscon@4018 {
31 compatible = "ti,am62-usb-phy-ctrl", "syscon";
32 reg = <0x4018 0x4>;
33 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]34 };
35
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]36 target-module@2b300050 {
37 compatible = "ti,sysc-omap2", "ti,sysc";
38 reg = <0x00 0x2b300050 0x00 0x4>,
39 <0x00 0x2b300054 0x00 0x4>,
40 <0x00 0x2b300058 0x00 0x4>;
41 reg-names = "rev", "sysc", "syss";
42 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
43 SYSC_OMAP2_SOFTRESET |
44 SYSC_OMAP2_AUTOIDLE)>;
45 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
46 <SYSC_IDLE_NO>,
47 <SYSC_IDLE_SMART>,
48 <SYSC_IDLE_SMART_WKUP>;
49 ti,syss-mask = <1>;
50 ti,no-reset-on-init;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]51 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
52 clocks = <&k3_clks 114 0>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]53 clock-names = "fck";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges = <0x0 0x00 0x2b300000 0x100000>;
57
58 wkup_uart0: serial@0 {
59 compatible = "ti,am64-uart", "ti,am654-uart";
60 reg = <0x0 0x100>;
61 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
62 status = "disabled";
63 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]64 };
65
66 wkup_i2c0: i2c@2b200000 {
67 compatible = "ti,am64-i2c", "ti,omap4-i2c";
68 reg = <0x00 0x2b200000 0x00 0x100>;
69 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
70 #address-cells = <1>;
71 #size-cells = <0>;
72 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
73 clocks = <&k3_clks 107 4>;
74 clock-names = "fck";
75 status = "disabled";
76 };
77
78 wkup_rtc0: rtc@2b1f0000 {
79 compatible = "ti,am62-rtc";
80 reg = <0x00 0x2b1f0000 0x00 0x100>;
81 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
82 clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
83 clock-names = "vbus", "osc32k";
84 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
85 wakeup-source;
86 };
87
88 wkup_rti0: watchdog@2b000000 {
89 compatible = "ti,j7-rti-wdt";
90 reg = <0x00 0x2b000000 0x00 0x100>;
91 clocks = <&k3_clks 132 0>;
92 power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
93 assigned-clocks = <&k3_clks 132 0>;
94 assigned-clock-parents = <&k3_clks 132 2>;
95 /* Used by DM firmware */
96 status = "reserved";
97 };
98
99 wkup_vtm0: temperature-sensor@b00000 {
100 compatible = "ti,j7200-vtm";
101 reg = <0x00 0xb00000 0x00 0x400>,
102 <0x00 0xb01000 0x00 0x400>;
103 power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
104 #thermal-sensor-cells = <1>;
105 };
106};