blob: 029f8898196167d2300e06c4a4750d1e5e0b0c65 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include "stm32mp251.dtsi"
7
8/ {
9 cpus {
10 cpu1: cpu@1 {
11 compatible = "arm,cortex-a35";
12 device_type = "cpu";
13 reg = <1>;
14 enable-method = "psci";
15 };
16 };
17
18 arm-pmu {
19 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
20 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
21 interrupt-affinity = <&cpu0>, <&cpu1>;
22 };
Tom Rini762f85b2024-07-20 11:15:10 -060023
24 timer {
25 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
26 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
27 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
28 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
29 };
Tom Rini53633a82024-02-29 12:33:36 -050030};