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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / renesas / r9a09g011.dtsi
blob: 50ed66d42a24532a6a0c77e2564eacb34d843a0b [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2M SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/r9a09g011-cpg.h>
10
11/ {
12 compatible = "renesas,r9a09g011";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
17 extal_clk: extal {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 /* This value must be overridden by the board */
21 clock-frequency = <0>;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu-map {
29 cluster0 {
30 core0 {
31 cpu = <&cpu0>;
32 };
33 };
34 };
35
36 cpu0: cpu@0 {
37 compatible = "arm,cortex-a53";
38 reg = <0>;
39 device_type = "cpu";
40 next-level-cache = <&L2_CA53>;
41 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
42 };
43
44 L2_CA53: cache-controller-0 {
45 compatible = "cache";
46 cache-unified;
47 cache-level = <2>;
48 };
49 };
50
51 soc: soc {
52 compatible = "simple-bus";
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
55 #size-cells = <2>;
56 ranges;
57
58 gic: interrupt-controller@82010000 {
59 compatible = "arm,gic-400";
60 #interrupt-cells = <3>;
61 #address-cells = <0>;
62 interrupt-controller;
63 reg = <0x0 0x82010000 0 0x1000>,
64 <0x0 0x82020000 0 0x20000>,
65 <0x0 0x82040000 0 0x20000>,
66 <0x0 0x82060000 0 0x20000>;
67 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
69 clock-names = "clk";
70 };
71
72 sdhi0: mmc@85000000 {
73 compatible = "renesas,sdhi-r9a09g011",
74 "renesas,rcar-gen3-sdhi";
75 reg = <0x0 0x85000000 0 0x2000>;
76 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
82 clock-names = "core", "clkh", "cd", "aclk";
83 resets = <&cpg R9A09G011_SDI0_IXRST>;
84 power-domains = <&cpg>;
85 status = "disabled";
86 };
87
88 sdhi1: mmc@85010000 {
89 compatible = "renesas,sdhi-r9a09g011",
90 "renesas,rcar-gen3-sdhi";
91 reg = <0x0 0x85010000 0 0x2000>;
92 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
95 <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>,
96 <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>,
97 <&cpg CPG_MOD R9A09G011_SDI1_ACLK>;
98 clock-names = "core", "clkh", "cd", "aclk";
99 resets = <&cpg R9A09G011_SDI1_IXRST>;
100 power-domains = <&cpg>;
101 status = "disabled";
102 };
103
104 emmc: mmc@85020000 {
105 compatible = "renesas,sdhi-r9a09g011",
106 "renesas,rcar-gen3-sdhi";
107 reg = <0x0 0x85020000 0 0x2000>;
108 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>,
111 <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>,
112 <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>,
113 <&cpg CPG_MOD R9A09G011_EMM_ACLK>;
114 clock-names = "core", "clkh", "cd", "aclk";
115 resets = <&cpg R9A09G011_EMM_IXRST>;
116 power-domains = <&cpg>;
117 status = "disabled";
118 };
119
120 usb3drd: usb3drd@85070400 {
121 compatible = "renesas,r9a09g011-usb3drd",
122 "renesas,rzv2m-usb3drd";
123 reg = <0x0 0x85070400 0x0 0x100>;
124 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-names = "drd", "bc", "gpi";
128 clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
129 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
130 clock-names = "axi", "reg";
131 resets = <&cpg R9A09G011_USB_DRD_RESET>;
132 power-domains = <&cpg>;
133 ranges;
134 #address-cells = <2>;
135 #size-cells = <2>;
136 status = "disabled";
137
138 usb3host: usb@85060000 {
139 compatible = "renesas,r9a09g011-xhci",
140 "renesas,rzv2m-xhci";
141 reg = <0 0x85060000 0 0x2000>;
142 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
144 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
145 clock-names = "axi", "reg";
146 resets = <&cpg R9A09G011_USB_ARESETN_H>;
147 power-domains = <&cpg>;
148 status = "disabled";
149 };
150
151 usb3peri: usb3peri@85070000 {
152 compatible = "renesas,r9a09g011-usb3-peri",
153 "renesas,rzv2m-usb3-peri";
154 reg = <0x0 0x85070000 0x0 0x400>;
155 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
157 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
158 clock-names = "axi", "reg";
159 resets = <&cpg R9A09G011_USB_ARESETN_P>;
160 power-domains = <&cpg>;
161 status = "disabled";
162 };
163 };
164
165 avb: ethernet@a3300000 {
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]166 compatible = "renesas,etheravb-r9a09g011", "renesas,etheravb-rzv2m";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]167 reg = <0 0xa3300000 0 0x800>;
168 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */
169 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */
170 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */
187 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */
188 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */
191 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */
192 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */
193 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */
194 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */
195 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */
196 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */
197 interrupt-names = "ch0", "ch1", "ch2", "ch3",
198 "ch4", "ch5", "ch6", "ch7",
199 "ch8", "ch9", "ch10", "ch11",
200 "ch12", "ch13", "ch14", "ch15",
201 "ch16", "ch17", "ch18", "ch19",
202 "ch20", "ch21", "dia", "dib",
203 "err_a", "err_b", "mgmt_a", "mgmt_b",
204 "line3";
205 clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>,
206 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>,
207 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
208 clock-names = "axi", "chi", "gptp";
209 resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
210 power-domains = <&cpg>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 status = "disabled";
214 };
215
216 cpg: clock-controller@a3500000 {
217 compatible = "renesas,r9a09g011-cpg";
218 reg = <0 0xa3500000 0 0x1000>;
219 clocks = <&extal_clk>;
220 clock-names = "extal";
221 #clock-cells = <2>;
222 #reset-cells = <1>;
223 #power-domain-cells = <0>;
224 };
225
226 pwc: pwc@a3700000 {
227 compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc";
228 reg = <0 0xa3700000 0 0x800>;
229 gpio-controller;
230 #gpio-cells = <2>;
231 status = "disabled";
232 };
233
234 sys: system-controller@a3f03000 {
235 compatible = "renesas,r9a09g011-sys";
236 reg = <0 0xa3f03000 0 0x400>;
237 };
238
239 csi0: spi@a4020000 {
240 compatible = "renesas,rzv2m-csi";
241 reg = <0 0xa4020000 0 0x80>;
242 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>,
244 <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>;
245 clock-names = "csiclk", "pclk";
246 resets = <&cpg R9A09G011_CSI_GPG_PRESETN>;
247 power-domains = <&cpg>;
248 #address-cells = <1>;
249 #size-cells = <0>;
250 status = "disabled";
251 };
252
253 csi4: spi@a4020200 {
254 compatible = "renesas,rzv2m-csi";
255 reg = <0 0xa4020200 0 0x80>;
256 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
258 <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
259 clock-names = "csiclk", "pclk";
260 resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
261 power-domains = <&cpg>;
262 #address-cells = <1>;
263 #size-cells = <0>;
264 status = "disabled";
265 };
266
267 i2c0: i2c@a4030000 {
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
271 reg = <0 0xa4030000 0 0x80>;
272 interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
274 interrupt-names = "tia", "tis";
275 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
276 resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
277 power-domains = <&cpg>;
278 status = "disabled";
279 };
280
281 i2c2: i2c@a4030100 {
282 #address-cells = <1>;
283 #size-cells = <0>;
284 compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
285 reg = <0 0xa4030100 0 0x80>;
286 interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
287 <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>;
288 interrupt-names = "tia", "tis";
289 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>;
290 resets = <&cpg R9A09G011_IIC_GPB_PRESETN>;
291 power-domains = <&cpg>;
292 status = "disabled";
293 };
294
295 uart0: serial@a4040000 {
296 compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
297 reg = <0 0xa4040000 0 0x80>;
298 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
300 <&cpg CPG_MOD R9A09G011_URT_PCLK>;
301 clock-names = "sclk", "pclk";
302 status = "disabled";
303 };
304
305 wdt0: watchdog@a4050000 {
306 compatible = "renesas,r9a09g011-wdt",
307 "renesas,rzv2m-wdt";
308 reg = <0 0xa4050000 0 0x80>;
309 clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>,
310 <&cpg CPG_MOD R9A09G011_WDT0_CLK>;
311 clock-names = "pclk", "oscclk";
312 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
313 resets = <&cpg R9A09G011_WDT0_PRESETN>;
314 power-domains = <&cpg>;
315 status = "disabled";
316 };
317
318 pinctrl: pinctrl@b6250000 {
319 compatible = "renesas,r9a09g011-pinctrl";
320 reg = <0 0xb6250000 0 0x800>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 gpio-ranges = <&pinctrl 0 0 352>;
324 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
364 power-domains = <&cpg>;
365 resets = <&cpg R9A09G011_PFC_PRESETN>;
366 };
367 };
368
369 timer {
370 compatible = "arm,armv8-timer";
371 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
372 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
373 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
374 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
375 };
376};