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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / qcom / sdm845.dtsi
blob: 10de2bd46ffcc659198ad3e70badd82a3a89ad3d [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SDM845 SoC device tree source
4 *
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,camcc-sdm845.h>
9#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10#include <dt-bindings/clock/qcom,gcc-sdm845.h>
11#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12#include <dt-bindings/clock/qcom,lpass-sdm845.h>
13#include <dt-bindings/clock/qcom,rpmh.h>
14#include <dt-bindings/clock/qcom,videocc-sdm845.h>
15#include <dt-bindings/dma/qcom-gpi.h>
16#include <dt-bindings/firmware/qcom,scm.h>
17#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/interconnect/qcom,osm-l3.h>
19#include <dt-bindings/interconnect/qcom,sdm845.h>
20#include <dt-bindings/interrupt-controller/arm-gic.h>
21#include <dt-bindings/phy/phy-qcom-qmp.h>
22#include <dt-bindings/phy/phy-qcom-qusb2.h>
23#include <dt-bindings/power/qcom-rpmpd.h>
24#include <dt-bindings/reset/qcom,sdm845-aoss.h>
25#include <dt-bindings/reset/qcom,sdm845-pdc.h>
26#include <dt-bindings/soc/qcom,apr.h>
27#include <dt-bindings/soc/qcom,rpmh-rsc.h>
28#include <dt-bindings/clock/qcom,gcc-sdm845.h>
29#include <dt-bindings/thermal/thermal.h>
30
31/ {
32 interrupt-parent = <&intc>;
33
34 #address-cells = <2>;
35 #size-cells = <2>;
36
37 aliases {
38 i2c0 = &i2c0;
39 i2c1 = &i2c1;
40 i2c2 = &i2c2;
41 i2c3 = &i2c3;
42 i2c4 = &i2c4;
43 i2c5 = &i2c5;
44 i2c6 = &i2c6;
45 i2c7 = &i2c7;
46 i2c8 = &i2c8;
47 i2c9 = &i2c9;
48 i2c10 = &i2c10;
49 i2c11 = &i2c11;
50 i2c12 = &i2c12;
51 i2c13 = &i2c13;
52 i2c14 = &i2c14;
53 i2c15 = &i2c15;
54 spi0 = &spi0;
55 spi1 = &spi1;
56 spi2 = &spi2;
57 spi3 = &spi3;
58 spi4 = &spi4;
59 spi5 = &spi5;
60 spi6 = &spi6;
61 spi7 = &spi7;
62 spi8 = &spi8;
63 spi9 = &spi9;
64 spi10 = &spi10;
65 spi11 = &spi11;
66 spi12 = &spi12;
67 spi13 = &spi13;
68 spi14 = &spi14;
69 spi15 = &spi15;
70 };
71
72 chosen { };
73
74 clocks {
75 xo_board: xo-board {
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <38400000>;
79 clock-output-names = "xo_board";
80 };
81
82 sleep_clk: sleep-clk {
83 compatible = "fixed-clock";
84 #clock-cells = <0>;
85 clock-frequency = <32764>;
86 };
87 };
88
89 cpus: cpus {
90 #address-cells = <2>;
91 #size-cells = <0>;
92
93 CPU0: cpu@0 {
94 device_type = "cpu";
95 compatible = "qcom,kryo385";
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
98 enable-method = "psci";
99 capacity-dmips-mhz = <611>;
100 dynamic-power-coefficient = <154>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 operating-points-v2 = <&cpu0_opp_table>;
103 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
104 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
105 power-domains = <&CPU_PD0>;
106 power-domain-names = "psci";
107 #cooling-cells = <2>;
108 next-level-cache = <&L2_0>;
109 L2_0: l2-cache {
110 compatible = "cache";
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&L3_0>;
114 L3_0: l3-cache {
115 compatible = "cache";
116 cache-level = <3>;
117 cache-unified;
118 };
119 };
120 };
121
122 CPU1: cpu@100 {
123 device_type = "cpu";
124 compatible = "qcom,kryo385";
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
127 enable-method = "psci";
128 capacity-dmips-mhz = <611>;
129 dynamic-power-coefficient = <154>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
131 operating-points-v2 = <&cpu0_opp_table>;
132 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
133 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
134 power-domains = <&CPU_PD1>;
135 power-domain-names = "psci";
136 #cooling-cells = <2>;
137 next-level-cache = <&L2_100>;
138 L2_100: l2-cache {
139 compatible = "cache";
140 cache-level = <2>;
141 cache-unified;
142 next-level-cache = <&L3_0>;
143 };
144 };
145
146 CPU2: cpu@200 {
147 device_type = "cpu";
148 compatible = "qcom,kryo385";
149 reg = <0x0 0x200>;
150 clocks = <&cpufreq_hw 0>;
151 enable-method = "psci";
152 capacity-dmips-mhz = <611>;
153 dynamic-power-coefficient = <154>;
154 qcom,freq-domain = <&cpufreq_hw 0>;
155 operating-points-v2 = <&cpu0_opp_table>;
156 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
157 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
158 power-domains = <&CPU_PD2>;
159 power-domain-names = "psci";
160 #cooling-cells = <2>;
161 next-level-cache = <&L2_200>;
162 L2_200: l2-cache {
163 compatible = "cache";
164 cache-level = <2>;
165 cache-unified;
166 next-level-cache = <&L3_0>;
167 };
168 };
169
170 CPU3: cpu@300 {
171 device_type = "cpu";
172 compatible = "qcom,kryo385";
173 reg = <0x0 0x300>;
174 clocks = <&cpufreq_hw 0>;
175 enable-method = "psci";
176 capacity-dmips-mhz = <611>;
177 dynamic-power-coefficient = <154>;
178 qcom,freq-domain = <&cpufreq_hw 0>;
179 operating-points-v2 = <&cpu0_opp_table>;
180 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
181 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
182 #cooling-cells = <2>;
183 power-domains = <&CPU_PD3>;
184 power-domain-names = "psci";
185 next-level-cache = <&L2_300>;
186 L2_300: l2-cache {
187 compatible = "cache";
188 cache-level = <2>;
189 cache-unified;
190 next-level-cache = <&L3_0>;
191 };
192 };
193
194 CPU4: cpu@400 {
195 device_type = "cpu";
196 compatible = "qcom,kryo385";
197 reg = <0x0 0x400>;
198 clocks = <&cpufreq_hw 1>;
199 enable-method = "psci";
200 capacity-dmips-mhz = <1024>;
201 dynamic-power-coefficient = <442>;
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 operating-points-v2 = <&cpu4_opp_table>;
204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
206 power-domains = <&CPU_PD4>;
207 power-domain-names = "psci";
208 #cooling-cells = <2>;
209 next-level-cache = <&L2_400>;
210 L2_400: l2-cache {
211 compatible = "cache";
212 cache-level = <2>;
213 cache-unified;
214 next-level-cache = <&L3_0>;
215 };
216 };
217
218 CPU5: cpu@500 {
219 device_type = "cpu";
220 compatible = "qcom,kryo385";
221 reg = <0x0 0x500>;
222 clocks = <&cpufreq_hw 1>;
223 enable-method = "psci";
224 capacity-dmips-mhz = <1024>;
225 dynamic-power-coefficient = <442>;
226 qcom,freq-domain = <&cpufreq_hw 1>;
227 operating-points-v2 = <&cpu4_opp_table>;
228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
230 power-domains = <&CPU_PD5>;
231 power-domain-names = "psci";
232 #cooling-cells = <2>;
233 next-level-cache = <&L2_500>;
234 L2_500: l2-cache {
235 compatible = "cache";
236 cache-level = <2>;
237 cache-unified;
238 next-level-cache = <&L3_0>;
239 };
240 };
241
242 CPU6: cpu@600 {
243 device_type = "cpu";
244 compatible = "qcom,kryo385";
245 reg = <0x0 0x600>;
246 clocks = <&cpufreq_hw 1>;
247 enable-method = "psci";
248 capacity-dmips-mhz = <1024>;
249 dynamic-power-coefficient = <442>;
250 qcom,freq-domain = <&cpufreq_hw 1>;
251 operating-points-v2 = <&cpu4_opp_table>;
252 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
254 power-domains = <&CPU_PD6>;
255 power-domain-names = "psci";
256 #cooling-cells = <2>;
257 next-level-cache = <&L2_600>;
258 L2_600: l2-cache {
259 compatible = "cache";
260 cache-level = <2>;
261 cache-unified;
262 next-level-cache = <&L3_0>;
263 };
264 };
265
266 CPU7: cpu@700 {
267 device_type = "cpu";
268 compatible = "qcom,kryo385";
269 reg = <0x0 0x700>;
270 clocks = <&cpufreq_hw 1>;
271 enable-method = "psci";
272 capacity-dmips-mhz = <1024>;
273 dynamic-power-coefficient = <442>;
274 qcom,freq-domain = <&cpufreq_hw 1>;
275 operating-points-v2 = <&cpu4_opp_table>;
276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
277 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
278 power-domains = <&CPU_PD7>;
279 power-domain-names = "psci";
280 #cooling-cells = <2>;
281 next-level-cache = <&L2_700>;
282 L2_700: l2-cache {
283 compatible = "cache";
284 cache-level = <2>;
285 cache-unified;
286 next-level-cache = <&L3_0>;
287 };
288 };
289
290 cpu-map {
291 cluster0 {
292 core0 {
293 cpu = <&CPU0>;
294 };
295
296 core1 {
297 cpu = <&CPU1>;
298 };
299
300 core2 {
301 cpu = <&CPU2>;
302 };
303
304 core3 {
305 cpu = <&CPU3>;
306 };
307
308 core4 {
309 cpu = <&CPU4>;
310 };
311
312 core5 {
313 cpu = <&CPU5>;
314 };
315
316 core6 {
317 cpu = <&CPU6>;
318 };
319
320 core7 {
321 cpu = <&CPU7>;
322 };
323 };
324 };
325
326 cpu_idle_states: idle-states {
327 entry-method = "psci";
328
329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
330 compatible = "arm,idle-state";
331 idle-state-name = "little-rail-power-collapse";
332 arm,psci-suspend-param = <0x40000004>;
333 entry-latency-us = <350>;
334 exit-latency-us = <461>;
335 min-residency-us = <1890>;
336 local-timer-stop;
337 };
338
339 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
340 compatible = "arm,idle-state";
341 idle-state-name = "big-rail-power-collapse";
342 arm,psci-suspend-param = <0x40000004>;
343 entry-latency-us = <264>;
344 exit-latency-us = <621>;
345 min-residency-us = <952>;
346 local-timer-stop;
347 };
348 };
349
350 domain-idle-states {
351 CLUSTER_SLEEP_0: cluster-sleep-0 {
352 compatible = "domain-idle-state";
353 arm,psci-suspend-param = <0x4100c244>;
354 entry-latency-us = <3263>;
355 exit-latency-us = <6562>;
356 min-residency-us = <9987>;
357 };
358 };
359 };
360
361 firmware {
362 scm {
363 compatible = "qcom,scm-sdm845", "qcom,scm";
364 };
365 };
366
367 memory@80000000 {
368 device_type = "memory";
369 /* We expect the bootloader to fill in the size */
370 reg = <0 0x80000000 0 0>;
371 };
372
373 cpu0_opp_table: opp-table-cpu0 {
374 compatible = "operating-points-v2";
375 opp-shared;
376
377 cpu0_opp1: opp-300000000 {
378 opp-hz = /bits/ 64 <300000000>;
379 opp-peak-kBps = <800000 4800000>;
380 };
381
382 cpu0_opp2: opp-403200000 {
383 opp-hz = /bits/ 64 <403200000>;
384 opp-peak-kBps = <800000 4800000>;
385 };
386
387 cpu0_opp3: opp-480000000 {
388 opp-hz = /bits/ 64 <480000000>;
389 opp-peak-kBps = <800000 6451200>;
390 };
391
392 cpu0_opp4: opp-576000000 {
393 opp-hz = /bits/ 64 <576000000>;
394 opp-peak-kBps = <800000 6451200>;
395 };
396
397 cpu0_opp5: opp-652800000 {
398 opp-hz = /bits/ 64 <652800000>;
399 opp-peak-kBps = <800000 7680000>;
400 };
401
402 cpu0_opp6: opp-748800000 {
403 opp-hz = /bits/ 64 <748800000>;
404 opp-peak-kBps = <1804000 9216000>;
405 };
406
407 cpu0_opp7: opp-825600000 {
408 opp-hz = /bits/ 64 <825600000>;
409 opp-peak-kBps = <1804000 9216000>;
410 };
411
412 cpu0_opp8: opp-902400000 {
413 opp-hz = /bits/ 64 <902400000>;
414 opp-peak-kBps = <1804000 10444800>;
415 };
416
417 cpu0_opp9: opp-979200000 {
418 opp-hz = /bits/ 64 <979200000>;
419 opp-peak-kBps = <1804000 11980800>;
420 };
421
422 cpu0_opp10: opp-1056000000 {
423 opp-hz = /bits/ 64 <1056000000>;
424 opp-peak-kBps = <1804000 11980800>;
425 };
426
427 cpu0_opp11: opp-1132800000 {
428 opp-hz = /bits/ 64 <1132800000>;
429 opp-peak-kBps = <2188000 13516800>;
430 };
431
432 cpu0_opp12: opp-1228800000 {
433 opp-hz = /bits/ 64 <1228800000>;
434 opp-peak-kBps = <2188000 15052800>;
435 };
436
437 cpu0_opp13: opp-1324800000 {
438 opp-hz = /bits/ 64 <1324800000>;
439 opp-peak-kBps = <2188000 16588800>;
440 };
441
442 cpu0_opp14: opp-1420800000 {
443 opp-hz = /bits/ 64 <1420800000>;
444 opp-peak-kBps = <3072000 18124800>;
445 };
446
447 cpu0_opp15: opp-1516800000 {
448 opp-hz = /bits/ 64 <1516800000>;
449 opp-peak-kBps = <3072000 19353600>;
450 };
451
452 cpu0_opp16: opp-1612800000 {
453 opp-hz = /bits/ 64 <1612800000>;
454 opp-peak-kBps = <4068000 19353600>;
455 };
456
457 cpu0_opp17: opp-1689600000 {
458 opp-hz = /bits/ 64 <1689600000>;
459 opp-peak-kBps = <4068000 20889600>;
460 };
461
462 cpu0_opp18: opp-1766400000 {
463 opp-hz = /bits/ 64 <1766400000>;
464 opp-peak-kBps = <4068000 22425600>;
465 };
466 };
467
468 cpu4_opp_table: opp-table-cpu4 {
469 compatible = "operating-points-v2";
470 opp-shared;
471
472 cpu4_opp1: opp-300000000 {
473 opp-hz = /bits/ 64 <300000000>;
474 opp-peak-kBps = <800000 4800000>;
475 };
476
477 cpu4_opp2: opp-403200000 {
478 opp-hz = /bits/ 64 <403200000>;
479 opp-peak-kBps = <800000 4800000>;
480 };
481
482 cpu4_opp3: opp-480000000 {
483 opp-hz = /bits/ 64 <480000000>;
484 opp-peak-kBps = <1804000 4800000>;
485 };
486
487 cpu4_opp4: opp-576000000 {
488 opp-hz = /bits/ 64 <576000000>;
489 opp-peak-kBps = <1804000 4800000>;
490 };
491
492 cpu4_opp5: opp-652800000 {
493 opp-hz = /bits/ 64 <652800000>;
494 opp-peak-kBps = <1804000 4800000>;
495 };
496
497 cpu4_opp6: opp-748800000 {
498 opp-hz = /bits/ 64 <748800000>;
499 opp-peak-kBps = <1804000 4800000>;
500 };
501
502 cpu4_opp7: opp-825600000 {
503 opp-hz = /bits/ 64 <825600000>;
504 opp-peak-kBps = <2188000 9216000>;
505 };
506
507 cpu4_opp8: opp-902400000 {
508 opp-hz = /bits/ 64 <902400000>;
509 opp-peak-kBps = <2188000 9216000>;
510 };
511
512 cpu4_opp9: opp-979200000 {
513 opp-hz = /bits/ 64 <979200000>;
514 opp-peak-kBps = <2188000 9216000>;
515 };
516
517 cpu4_opp10: opp-1056000000 {
518 opp-hz = /bits/ 64 <1056000000>;
519 opp-peak-kBps = <3072000 9216000>;
520 };
521
522 cpu4_opp11: opp-1132800000 {
523 opp-hz = /bits/ 64 <1132800000>;
524 opp-peak-kBps = <3072000 11980800>;
525 };
526
527 cpu4_opp12: opp-1209600000 {
528 opp-hz = /bits/ 64 <1209600000>;
529 opp-peak-kBps = <4068000 11980800>;
530 };
531
532 cpu4_opp13: opp-1286400000 {
533 opp-hz = /bits/ 64 <1286400000>;
534 opp-peak-kBps = <4068000 11980800>;
535 };
536
537 cpu4_opp14: opp-1363200000 {
538 opp-hz = /bits/ 64 <1363200000>;
539 opp-peak-kBps = <4068000 15052800>;
540 };
541
542 cpu4_opp15: opp-1459200000 {
543 opp-hz = /bits/ 64 <1459200000>;
544 opp-peak-kBps = <4068000 15052800>;
545 };
546
547 cpu4_opp16: opp-1536000000 {
548 opp-hz = /bits/ 64 <1536000000>;
549 opp-peak-kBps = <5412000 15052800>;
550 };
551
552 cpu4_opp17: opp-1612800000 {
553 opp-hz = /bits/ 64 <1612800000>;
554 opp-peak-kBps = <5412000 15052800>;
555 };
556
557 cpu4_opp18: opp-1689600000 {
558 opp-hz = /bits/ 64 <1689600000>;
559 opp-peak-kBps = <5412000 19353600>;
560 };
561
562 cpu4_opp19: opp-1766400000 {
563 opp-hz = /bits/ 64 <1766400000>;
564 opp-peak-kBps = <6220000 19353600>;
565 };
566
567 cpu4_opp20: opp-1843200000 {
568 opp-hz = /bits/ 64 <1843200000>;
569 opp-peak-kBps = <6220000 19353600>;
570 };
571
572 cpu4_opp21: opp-1920000000 {
573 opp-hz = /bits/ 64 <1920000000>;
574 opp-peak-kBps = <7216000 19353600>;
575 };
576
577 cpu4_opp22: opp-1996800000 {
578 opp-hz = /bits/ 64 <1996800000>;
579 opp-peak-kBps = <7216000 20889600>;
580 };
581
582 cpu4_opp23: opp-2092800000 {
583 opp-hz = /bits/ 64 <2092800000>;
584 opp-peak-kBps = <7216000 20889600>;
585 };
586
587 cpu4_opp24: opp-2169600000 {
588 opp-hz = /bits/ 64 <2169600000>;
589 opp-peak-kBps = <7216000 20889600>;
590 };
591
592 cpu4_opp25: opp-2246400000 {
593 opp-hz = /bits/ 64 <2246400000>;
594 opp-peak-kBps = <7216000 20889600>;
595 };
596
597 cpu4_opp26: opp-2323200000 {
598 opp-hz = /bits/ 64 <2323200000>;
599 opp-peak-kBps = <7216000 20889600>;
600 };
601
602 cpu4_opp27: opp-2400000000 {
603 opp-hz = /bits/ 64 <2400000000>;
604 opp-peak-kBps = <7216000 22425600>;
605 };
606
607 cpu4_opp28: opp-2476800000 {
608 opp-hz = /bits/ 64 <2476800000>;
609 opp-peak-kBps = <7216000 22425600>;
610 };
611
612 cpu4_opp29: opp-2553600000 {
613 opp-hz = /bits/ 64 <2553600000>;
614 opp-peak-kBps = <7216000 22425600>;
615 };
616
617 cpu4_opp30: opp-2649600000 {
618 opp-hz = /bits/ 64 <2649600000>;
619 opp-peak-kBps = <7216000 22425600>;
620 };
621
622 cpu4_opp31: opp-2745600000 {
623 opp-hz = /bits/ 64 <2745600000>;
624 opp-peak-kBps = <7216000 25497600>;
625 };
626
627 cpu4_opp32: opp-2803200000 {
628 opp-hz = /bits/ 64 <2803200000>;
629 opp-peak-kBps = <7216000 25497600>;
630 };
631 };
632
633 dsi_opp_table: opp-table-dsi {
634 compatible = "operating-points-v2";
635
636 opp-19200000 {
637 opp-hz = /bits/ 64 <19200000>;
638 required-opps = <&rpmhpd_opp_min_svs>;
639 };
640
641 opp-180000000 {
642 opp-hz = /bits/ 64 <180000000>;
643 required-opps = <&rpmhpd_opp_low_svs>;
644 };
645
646 opp-275000000 {
647 opp-hz = /bits/ 64 <275000000>;
648 required-opps = <&rpmhpd_opp_svs>;
649 };
650
651 opp-328580000 {
652 opp-hz = /bits/ 64 <328580000>;
653 required-opps = <&rpmhpd_opp_svs_l1>;
654 };
655
656 opp-358000000 {
657 opp-hz = /bits/ 64 <358000000>;
658 required-opps = <&rpmhpd_opp_nom>;
659 };
660 };
661
662 qspi_opp_table: opp-table-qspi {
663 compatible = "operating-points-v2";
664
665 opp-19200000 {
666 opp-hz = /bits/ 64 <19200000>;
667 required-opps = <&rpmhpd_opp_min_svs>;
668 };
669
670 opp-100000000 {
671 opp-hz = /bits/ 64 <100000000>;
672 required-opps = <&rpmhpd_opp_low_svs>;
673 };
674
675 opp-150000000 {
676 opp-hz = /bits/ 64 <150000000>;
677 required-opps = <&rpmhpd_opp_svs>;
678 };
679
680 opp-300000000 {
681 opp-hz = /bits/ 64 <300000000>;
682 required-opps = <&rpmhpd_opp_nom>;
683 };
684 };
685
686 qup_opp_table: opp-table-qup {
687 compatible = "operating-points-v2";
688
689 opp-50000000 {
690 opp-hz = /bits/ 64 <50000000>;
691 required-opps = <&rpmhpd_opp_min_svs>;
692 };
693
694 opp-75000000 {
695 opp-hz = /bits/ 64 <75000000>;
696 required-opps = <&rpmhpd_opp_low_svs>;
697 };
698
699 opp-100000000 {
700 opp-hz = /bits/ 64 <100000000>;
701 required-opps = <&rpmhpd_opp_svs>;
702 };
703
704 opp-128000000 {
705 opp-hz = /bits/ 64 <128000000>;
706 required-opps = <&rpmhpd_opp_nom>;
707 };
708 };
709
710 pmu {
711 compatible = "arm,armv8-pmuv3";
712 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
713 };
714
715 psci: psci {
716 compatible = "arm,psci-1.0";
717 method = "smc";
718
719 CPU_PD0: power-domain-cpu0 {
720 #power-domain-cells = <0>;
721 power-domains = <&CLUSTER_PD>;
722 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
723 };
724
725 CPU_PD1: power-domain-cpu1 {
726 #power-domain-cells = <0>;
727 power-domains = <&CLUSTER_PD>;
728 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
729 };
730
731 CPU_PD2: power-domain-cpu2 {
732 #power-domain-cells = <0>;
733 power-domains = <&CLUSTER_PD>;
734 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
735 };
736
737 CPU_PD3: power-domain-cpu3 {
738 #power-domain-cells = <0>;
739 power-domains = <&CLUSTER_PD>;
740 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
741 };
742
743 CPU_PD4: power-domain-cpu4 {
744 #power-domain-cells = <0>;
745 power-domains = <&CLUSTER_PD>;
746 domain-idle-states = <&BIG_CPU_SLEEP_0>;
747 };
748
749 CPU_PD5: power-domain-cpu5 {
750 #power-domain-cells = <0>;
751 power-domains = <&CLUSTER_PD>;
752 domain-idle-states = <&BIG_CPU_SLEEP_0>;
753 };
754
755 CPU_PD6: power-domain-cpu6 {
756 #power-domain-cells = <0>;
757 power-domains = <&CLUSTER_PD>;
758 domain-idle-states = <&BIG_CPU_SLEEP_0>;
759 };
760
761 CPU_PD7: power-domain-cpu7 {
762 #power-domain-cells = <0>;
763 power-domains = <&CLUSTER_PD>;
764 domain-idle-states = <&BIG_CPU_SLEEP_0>;
765 };
766
767 CLUSTER_PD: power-domain-cluster {
768 #power-domain-cells = <0>;
769 domain-idle-states = <&CLUSTER_SLEEP_0>;
770 };
771 };
772
773 reserved-memory {
774 #address-cells = <2>;
775 #size-cells = <2>;
776 ranges;
777
778 hyp_mem: hyp-mem@85700000 {
779 reg = <0 0x85700000 0 0x600000>;
780 no-map;
781 };
782
783 xbl_mem: xbl-mem@85e00000 {
784 reg = <0 0x85e00000 0 0x100000>;
785 no-map;
786 };
787
788 aop_mem: aop-mem@85fc0000 {
789 reg = <0 0x85fc0000 0 0x20000>;
790 no-map;
791 };
792
793 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
794 compatible = "qcom,cmd-db";
795 reg = <0x0 0x85fe0000 0 0x20000>;
796 no-map;
797 };
798
799 smem@86000000 {
800 compatible = "qcom,smem";
801 reg = <0x0 0x86000000 0 0x200000>;
802 no-map;
803 hwlocks = <&tcsr_mutex 3>;
804 };
805
806 tz_mem: tz@86200000 {
807 reg = <0 0x86200000 0 0x2d00000>;
808 no-map;
809 };
810
811 rmtfs_mem: rmtfs@88f00000 {
812 compatible = "qcom,rmtfs-mem";
813 reg = <0 0x88f00000 0 0x200000>;
814 no-map;
815
816 qcom,client-id = <1>;
817 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
818 };
819
820 qseecom_mem: qseecom@8ab00000 {
821 reg = <0 0x8ab00000 0 0x1400000>;
822 no-map;
823 };
824
825 camera_mem: camera-mem@8bf00000 {
826 reg = <0 0x8bf00000 0 0x500000>;
827 no-map;
828 };
829
830 ipa_fw_mem: ipa-fw@8c400000 {
831 reg = <0 0x8c400000 0 0x10000>;
832 no-map;
833 };
834
835 ipa_gsi_mem: ipa-gsi@8c410000 {
836 reg = <0 0x8c410000 0 0x5000>;
837 no-map;
838 };
839
840 gpu_mem: gpu@8c415000 {
841 reg = <0 0x8c415000 0 0x2000>;
842 no-map;
843 };
844
845 adsp_mem: adsp@8c500000 {
846 reg = <0 0x8c500000 0 0x1a00000>;
847 no-map;
848 };
849
850 wlan_msa_mem: wlan-msa@8df00000 {
851 reg = <0 0x8df00000 0 0x100000>;
852 no-map;
853 };
854
855 mpss_region: mpss@8e000000 {
856 reg = <0 0x8e000000 0 0x7800000>;
857 no-map;
858 };
859
860 venus_mem: venus@95800000 {
861 reg = <0 0x95800000 0 0x500000>;
862 no-map;
863 };
864
865 cdsp_mem: cdsp@95d00000 {
866 reg = <0 0x95d00000 0 0x800000>;
867 no-map;
868 };
869
870 mba_region: mba@96500000 {
871 reg = <0 0x96500000 0 0x200000>;
872 no-map;
873 };
874
875 slpi_mem: slpi@96700000 {
876 reg = <0 0x96700000 0 0x1400000>;
877 no-map;
878 };
879
880 spss_mem: spss@97b00000 {
881 reg = <0 0x97b00000 0 0x100000>;
882 no-map;
883 };
884
885 mdata_mem: mpss-metadata {
886 alloc-ranges = <0 0xa0000000 0 0x20000000>;
887 size = <0 0x4000>;
888 no-map;
889 };
890
891 fastrpc_mem: fastrpc {
892 compatible = "shared-dma-pool";
893 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
894 alignment = <0x0 0x400000>;
895 size = <0x0 0x1000000>;
896 reusable;
897 };
898 };
899
900 adsp_pas: remoteproc-adsp {
901 compatible = "qcom,sdm845-adsp-pas";
902
903 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
904 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
908 interrupt-names = "wdog", "fatal", "ready",
909 "handover", "stop-ack";
910
911 clocks = <&rpmhcc RPMH_CXO_CLK>;
912 clock-names = "xo";
913
914 memory-region = <&adsp_mem>;
915
916 qcom,qmp = <&aoss_qmp>;
917
918 qcom,smem-states = <&adsp_smp2p_out 0>;
919 qcom,smem-state-names = "stop";
920
921 status = "disabled";
922
923 glink-edge {
924 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
925 label = "lpass";
926 qcom,remote-pid = <2>;
927 mboxes = <&apss_shared 8>;
928
929 apr {
930 compatible = "qcom,apr-v2";
931 qcom,glink-channels = "apr_audio_svc";
932 qcom,domain = <APR_DOMAIN_ADSP>;
933 #address-cells = <1>;
934 #size-cells = <0>;
935 qcom,intents = <512 20>;
936
937 service@3 {
938 reg = <APR_SVC_ADSP_CORE>;
939 compatible = "qcom,q6core";
940 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
941 };
942
943 q6afe: service@4 {
944 compatible = "qcom,q6afe";
945 reg = <APR_SVC_AFE>;
946 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
947 q6afedai: dais {
948 compatible = "qcom,q6afe-dais";
949 #address-cells = <1>;
950 #size-cells = <0>;
951 #sound-dai-cells = <1>;
952 };
953 };
954
955 q6asm: service@7 {
956 compatible = "qcom,q6asm";
957 reg = <APR_SVC_ASM>;
958 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
959 q6asmdai: dais {
960 compatible = "qcom,q6asm-dais";
961 #address-cells = <1>;
962 #size-cells = <0>;
963 #sound-dai-cells = <1>;
964 iommus = <&apps_smmu 0x1821 0x0>;
965 };
966 };
967
968 q6adm: service@8 {
969 compatible = "qcom,q6adm";
970 reg = <APR_SVC_ADM>;
971 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
972 q6routing: routing {
973 compatible = "qcom,q6adm-routing";
974 #sound-dai-cells = <0>;
975 };
976 };
977 };
978
979 fastrpc {
980 compatible = "qcom,fastrpc";
981 qcom,glink-channels = "fastrpcglink-apps-dsp";
982 label = "adsp";
983 qcom,non-secure-domain;
984 #address-cells = <1>;
985 #size-cells = <0>;
986
987 compute-cb@3 {
988 compatible = "qcom,fastrpc-compute-cb";
989 reg = <3>;
990 iommus = <&apps_smmu 0x1823 0x0>;
991 };
992
993 compute-cb@4 {
994 compatible = "qcom,fastrpc-compute-cb";
995 reg = <4>;
996 iommus = <&apps_smmu 0x1824 0x0>;
997 };
998 };
999 };
1000 };
1001
1002 cdsp_pas: remoteproc-cdsp {
1003 compatible = "qcom,sdm845-cdsp-pas";
1004
1005 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1006 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1010 interrupt-names = "wdog", "fatal", "ready",
1011 "handover", "stop-ack";
1012
1013 clocks = <&rpmhcc RPMH_CXO_CLK>;
1014 clock-names = "xo";
1015
1016 memory-region = <&cdsp_mem>;
1017
1018 qcom,qmp = <&aoss_qmp>;
1019
1020 qcom,smem-states = <&cdsp_smp2p_out 0>;
1021 qcom,smem-state-names = "stop";
1022
1023 status = "disabled";
1024
1025 glink-edge {
1026 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1027 label = "turing";
1028 qcom,remote-pid = <5>;
1029 mboxes = <&apss_shared 4>;
1030 fastrpc {
1031 compatible = "qcom,fastrpc";
1032 qcom,glink-channels = "fastrpcglink-apps-dsp";
1033 label = "cdsp";
1034 qcom,non-secure-domain;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037
1038 compute-cb@1 {
1039 compatible = "qcom,fastrpc-compute-cb";
1040 reg = <1>;
1041 iommus = <&apps_smmu 0x1401 0x30>;
1042 };
1043
1044 compute-cb@2 {
1045 compatible = "qcom,fastrpc-compute-cb";
1046 reg = <2>;
1047 iommus = <&apps_smmu 0x1402 0x30>;
1048 };
1049
1050 compute-cb@3 {
1051 compatible = "qcom,fastrpc-compute-cb";
1052 reg = <3>;
1053 iommus = <&apps_smmu 0x1403 0x30>;
1054 };
1055
1056 compute-cb@4 {
1057 compatible = "qcom,fastrpc-compute-cb";
1058 reg = <4>;
1059 iommus = <&apps_smmu 0x1404 0x30>;
1060 };
1061
1062 compute-cb@5 {
1063 compatible = "qcom,fastrpc-compute-cb";
1064 reg = <5>;
1065 iommus = <&apps_smmu 0x1405 0x30>;
1066 };
1067
1068 compute-cb@6 {
1069 compatible = "qcom,fastrpc-compute-cb";
1070 reg = <6>;
1071 iommus = <&apps_smmu 0x1406 0x30>;
1072 };
1073
1074 compute-cb@7 {
1075 compatible = "qcom,fastrpc-compute-cb";
1076 reg = <7>;
1077 iommus = <&apps_smmu 0x1407 0x30>;
1078 };
1079
1080 compute-cb@8 {
1081 compatible = "qcom,fastrpc-compute-cb";
1082 reg = <8>;
1083 iommus = <&apps_smmu 0x1408 0x30>;
1084 };
1085 };
1086 };
1087 };
1088
1089 smp2p-cdsp {
1090 compatible = "qcom,smp2p";
1091 qcom,smem = <94>, <432>;
1092
1093 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1094
1095 mboxes = <&apss_shared 6>;
1096
1097 qcom,local-pid = <0>;
1098 qcom,remote-pid = <5>;
1099
1100 cdsp_smp2p_out: master-kernel {
1101 qcom,entry-name = "master-kernel";
1102 #qcom,smem-state-cells = <1>;
1103 };
1104
1105 cdsp_smp2p_in: slave-kernel {
1106 qcom,entry-name = "slave-kernel";
1107
1108 interrupt-controller;
1109 #interrupt-cells = <2>;
1110 };
1111 };
1112
1113 smp2p-lpass {
1114 compatible = "qcom,smp2p";
1115 qcom,smem = <443>, <429>;
1116
1117 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1118
1119 mboxes = <&apss_shared 10>;
1120
1121 qcom,local-pid = <0>;
1122 qcom,remote-pid = <2>;
1123
1124 adsp_smp2p_out: master-kernel {
1125 qcom,entry-name = "master-kernel";
1126 #qcom,smem-state-cells = <1>;
1127 };
1128
1129 adsp_smp2p_in: slave-kernel {
1130 qcom,entry-name = "slave-kernel";
1131
1132 interrupt-controller;
1133 #interrupt-cells = <2>;
1134 };
1135 };
1136
1137 smp2p-mpss {
1138 compatible = "qcom,smp2p";
1139 qcom,smem = <435>, <428>;
1140 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1141 mboxes = <&apss_shared 14>;
1142 qcom,local-pid = <0>;
1143 qcom,remote-pid = <1>;
1144
1145 modem_smp2p_out: master-kernel {
1146 qcom,entry-name = "master-kernel";
1147 #qcom,smem-state-cells = <1>;
1148 };
1149
1150 modem_smp2p_in: slave-kernel {
1151 qcom,entry-name = "slave-kernel";
1152 interrupt-controller;
1153 #interrupt-cells = <2>;
1154 };
1155
1156 ipa_smp2p_out: ipa-ap-to-modem {
1157 qcom,entry-name = "ipa";
1158 #qcom,smem-state-cells = <1>;
1159 };
1160
1161 ipa_smp2p_in: ipa-modem-to-ap {
1162 qcom,entry-name = "ipa";
1163 interrupt-controller;
1164 #interrupt-cells = <2>;
1165 };
1166 };
1167
1168 smp2p-slpi {
1169 compatible = "qcom,smp2p";
1170 qcom,smem = <481>, <430>;
1171 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1172 mboxes = <&apss_shared 26>;
1173 qcom,local-pid = <0>;
1174 qcom,remote-pid = <3>;
1175
1176 slpi_smp2p_out: master-kernel {
1177 qcom,entry-name = "master-kernel";
1178 #qcom,smem-state-cells = <1>;
1179 };
1180
1181 slpi_smp2p_in: slave-kernel {
1182 qcom,entry-name = "slave-kernel";
1183 interrupt-controller;
1184 #interrupt-cells = <2>;
1185 };
1186 };
1187
1188 soc: soc@0 {
1189 #address-cells = <2>;
1190 #size-cells = <2>;
1191 ranges = <0 0 0 0 0x10 0>;
1192 dma-ranges = <0 0 0 0 0x10 0>;
1193 compatible = "simple-bus";
1194
1195 gcc: clock-controller@100000 {
1196 compatible = "qcom,gcc-sdm845";
1197 reg = <0 0x00100000 0 0x1f0000>;
1198 clocks = <&rpmhcc RPMH_CXO_CLK>,
1199 <&rpmhcc RPMH_CXO_CLK_A>,
1200 <&sleep_clk>,
1201 <&pcie0_phy>,
1202 <&pcie1_phy>;
1203 clock-names = "bi_tcxo",
1204 "bi_tcxo_ao",
1205 "sleep_clk",
1206 "pcie_0_pipe_clk",
1207 "pcie_1_pipe_clk";
1208 #clock-cells = <1>;
1209 #reset-cells = <1>;
1210 #power-domain-cells = <1>;
1211 power-domains = <&rpmhpd SDM845_CX>;
1212 };
1213
1214 qfprom@784000 {
1215 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1216 reg = <0 0x00784000 0 0x8ff>;
1217 #address-cells = <1>;
1218 #size-cells = <1>;
1219
1220 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1221 reg = <0x1eb 0x1>;
1222 bits = <1 4>;
1223 };
1224
1225 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1226 reg = <0x1eb 0x2>;
1227 bits = <6 4>;
1228 };
1229 };
1230
1231 rng: rng@793000 {
1232 compatible = "qcom,prng-ee";
1233 reg = <0 0x00793000 0 0x1000>;
1234 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1235 clock-names = "core";
1236 };
1237
1238 gpi_dma0: dma-controller@800000 {
1239 #dma-cells = <3>;
1240 compatible = "qcom,sdm845-gpi-dma";
1241 reg = <0 0x00800000 0 0x60000>;
1242 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1255 dma-channels = <13>;
1256 dma-channel-mask = <0xfa>;
1257 iommus = <&apps_smmu 0x0016 0x0>;
1258 status = "disabled";
1259 };
1260
1261 qupv3_id_0: geniqup@8c0000 {
1262 compatible = "qcom,geni-se-qup";
1263 reg = <0 0x008c0000 0 0x6000>;
1264 clock-names = "m-ahb", "s-ahb";
1265 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1266 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1267 iommus = <&apps_smmu 0x3 0x0>;
1268 #address-cells = <2>;
1269 #size-cells = <2>;
1270 ranges;
1271 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1272 interconnect-names = "qup-core";
1273 status = "disabled";
1274
1275 i2c0: i2c@880000 {
1276 compatible = "qcom,geni-i2c";
1277 reg = <0 0x00880000 0 0x4000>;
1278 clock-names = "se";
1279 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1280 pinctrl-names = "default";
1281 pinctrl-0 = <&qup_i2c0_default>;
1282 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1285 power-domains = <&rpmhpd SDM845_CX>;
1286 operating-points-v2 = <&qup_opp_table>;
1287 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1288 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1289 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1290 interconnect-names = "qup-core", "qup-config", "qup-memory";
1291 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1292 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1293 dma-names = "tx", "rx";
1294 status = "disabled";
1295 };
1296
1297 spi0: spi@880000 {
1298 compatible = "qcom,geni-spi";
1299 reg = <0 0x00880000 0 0x4000>;
1300 clock-names = "se";
1301 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1302 pinctrl-names = "default";
1303 pinctrl-0 = <&qup_spi0_default>;
1304 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1307 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1308 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1309 interconnect-names = "qup-core", "qup-config";
1310 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1311 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1312 dma-names = "tx", "rx";
1313 status = "disabled";
1314 };
1315
1316 uart0: serial@880000 {
1317 compatible = "qcom,geni-uart";
1318 reg = <0 0x00880000 0 0x4000>;
1319 clock-names = "se";
1320 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&qup_uart0_default>;
1323 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1324 power-domains = <&rpmhpd SDM845_CX>;
1325 operating-points-v2 = <&qup_opp_table>;
1326 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1327 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1328 interconnect-names = "qup-core", "qup-config";
1329 status = "disabled";
1330 };
1331
1332 i2c1: i2c@884000 {
1333 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00884000 0 0x4000>;
1335 clock-names = "se";
1336 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1337 pinctrl-names = "default";
1338 pinctrl-0 = <&qup_i2c1_default>;
1339 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1342 power-domains = <&rpmhpd SDM845_CX>;
1343 operating-points-v2 = <&qup_opp_table>;
1344 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1345 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1346 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1347 interconnect-names = "qup-core", "qup-config", "qup-memory";
1348 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1349 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1350 dma-names = "tx", "rx";
1351 status = "disabled";
1352 };
1353
1354 spi1: spi@884000 {
1355 compatible = "qcom,geni-spi";
1356 reg = <0 0x00884000 0 0x4000>;
1357 clock-names = "se";
1358 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_spi1_default>;
1361 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1365 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1366 interconnect-names = "qup-core", "qup-config";
1367 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1368 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1369 dma-names = "tx", "rx";
1370 status = "disabled";
1371 };
1372
1373 uart1: serial@884000 {
1374 compatible = "qcom,geni-uart";
1375 reg = <0 0x00884000 0 0x4000>;
1376 clock-names = "se";
1377 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1378 pinctrl-names = "default";
1379 pinctrl-0 = <&qup_uart1_default>;
1380 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1381 power-domains = <&rpmhpd SDM845_CX>;
1382 operating-points-v2 = <&qup_opp_table>;
1383 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1384 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1385 interconnect-names = "qup-core", "qup-config";
1386 status = "disabled";
1387 };
1388
1389 i2c2: i2c@888000 {
1390 compatible = "qcom,geni-i2c";
1391 reg = <0 0x00888000 0 0x4000>;
1392 clock-names = "se";
1393 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1394 pinctrl-names = "default";
1395 pinctrl-0 = <&qup_i2c2_default>;
1396 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1399 power-domains = <&rpmhpd SDM845_CX>;
1400 operating-points-v2 = <&qup_opp_table>;
1401 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1402 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1403 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1404 interconnect-names = "qup-core", "qup-config", "qup-memory";
1405 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1406 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1407 dma-names = "tx", "rx";
1408 status = "disabled";
1409 };
1410
1411 spi2: spi@888000 {
1412 compatible = "qcom,geni-spi";
1413 reg = <0 0x00888000 0 0x4000>;
1414 clock-names = "se";
1415 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1416 pinctrl-names = "default";
1417 pinctrl-0 = <&qup_spi2_default>;
1418 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1419 #address-cells = <1>;
1420 #size-cells = <0>;
1421 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1422 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1423 interconnect-names = "qup-core", "qup-config";
1424 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1425 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1426 dma-names = "tx", "rx";
1427 status = "disabled";
1428 };
1429
1430 uart2: serial@888000 {
1431 compatible = "qcom,geni-uart";
1432 reg = <0 0x00888000 0 0x4000>;
1433 clock-names = "se";
1434 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1435 pinctrl-names = "default";
1436 pinctrl-0 = <&qup_uart2_default>;
1437 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1438 power-domains = <&rpmhpd SDM845_CX>;
1439 operating-points-v2 = <&qup_opp_table>;
1440 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1441 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1442 interconnect-names = "qup-core", "qup-config";
1443 status = "disabled";
1444 };
1445
1446 i2c3: i2c@88c000 {
1447 compatible = "qcom,geni-i2c";
1448 reg = <0 0x0088c000 0 0x4000>;
1449 clock-names = "se";
1450 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1451 pinctrl-names = "default";
1452 pinctrl-0 = <&qup_i2c3_default>;
1453 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1456 power-domains = <&rpmhpd SDM845_CX>;
1457 operating-points-v2 = <&qup_opp_table>;
1458 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1459 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1460 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1461 interconnect-names = "qup-core", "qup-config", "qup-memory";
1462 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1463 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1464 dma-names = "tx", "rx";
1465 status = "disabled";
1466 };
1467
1468 spi3: spi@88c000 {
1469 compatible = "qcom,geni-spi";
1470 reg = <0 0x0088c000 0 0x4000>;
1471 clock-names = "se";
1472 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1473 pinctrl-names = "default";
1474 pinctrl-0 = <&qup_spi3_default>;
1475 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1478 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1479 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1480 interconnect-names = "qup-core", "qup-config";
1481 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1482 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1483 dma-names = "tx", "rx";
1484 status = "disabled";
1485 };
1486
1487 uart3: serial@88c000 {
1488 compatible = "qcom,geni-uart";
1489 reg = <0 0x0088c000 0 0x4000>;
1490 clock-names = "se";
1491 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1492 pinctrl-names = "default";
1493 pinctrl-0 = <&qup_uart3_default>;
1494 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1495 power-domains = <&rpmhpd SDM845_CX>;
1496 operating-points-v2 = <&qup_opp_table>;
1497 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1498 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1499 interconnect-names = "qup-core", "qup-config";
1500 status = "disabled";
1501 };
1502
1503 i2c4: i2c@890000 {
1504 compatible = "qcom,geni-i2c";
1505 reg = <0 0x00890000 0 0x4000>;
1506 clock-names = "se";
1507 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1508 pinctrl-names = "default";
1509 pinctrl-0 = <&qup_i2c4_default>;
1510 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1511 #address-cells = <1>;
1512 #size-cells = <0>;
1513 power-domains = <&rpmhpd SDM845_CX>;
1514 operating-points-v2 = <&qup_opp_table>;
1515 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1516 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1517 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1518 interconnect-names = "qup-core", "qup-config", "qup-memory";
1519 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1520 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1521 dma-names = "tx", "rx";
1522 status = "disabled";
1523 };
1524
1525 spi4: spi@890000 {
1526 compatible = "qcom,geni-spi";
1527 reg = <0 0x00890000 0 0x4000>;
1528 clock-names = "se";
1529 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1530 pinctrl-names = "default";
1531 pinctrl-0 = <&qup_spi4_default>;
1532 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1533 #address-cells = <1>;
1534 #size-cells = <0>;
1535 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1536 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1537 interconnect-names = "qup-core", "qup-config";
1538 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1539 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1540 dma-names = "tx", "rx";
1541 status = "disabled";
1542 };
1543
1544 uart4: serial@890000 {
1545 compatible = "qcom,geni-uart";
1546 reg = <0 0x00890000 0 0x4000>;
1547 clock-names = "se";
1548 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1549 pinctrl-names = "default";
1550 pinctrl-0 = <&qup_uart4_default>;
1551 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1552 power-domains = <&rpmhpd SDM845_CX>;
1553 operating-points-v2 = <&qup_opp_table>;
1554 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1555 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1556 interconnect-names = "qup-core", "qup-config";
1557 status = "disabled";
1558 };
1559
1560 i2c5: i2c@894000 {
1561 compatible = "qcom,geni-i2c";
1562 reg = <0 0x00894000 0 0x4000>;
1563 clock-names = "se";
1564 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&qup_i2c5_default>;
1567 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1568 #address-cells = <1>;
1569 #size-cells = <0>;
1570 power-domains = <&rpmhpd SDM845_CX>;
1571 operating-points-v2 = <&qup_opp_table>;
1572 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1573 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1574 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1575 interconnect-names = "qup-core", "qup-config", "qup-memory";
1576 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1577 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1578 dma-names = "tx", "rx";
1579 status = "disabled";
1580 };
1581
1582 spi5: spi@894000 {
1583 compatible = "qcom,geni-spi";
1584 reg = <0 0x00894000 0 0x4000>;
1585 clock-names = "se";
1586 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1587 pinctrl-names = "default";
1588 pinctrl-0 = <&qup_spi5_default>;
1589 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1592 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1593 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1594 interconnect-names = "qup-core", "qup-config";
1595 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1596 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1597 dma-names = "tx", "rx";
1598 status = "disabled";
1599 };
1600
1601 uart5: serial@894000 {
1602 compatible = "qcom,geni-uart";
1603 reg = <0 0x00894000 0 0x4000>;
1604 clock-names = "se";
1605 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1606 pinctrl-names = "default";
1607 pinctrl-0 = <&qup_uart5_default>;
1608 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1609 power-domains = <&rpmhpd SDM845_CX>;
1610 operating-points-v2 = <&qup_opp_table>;
1611 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1612 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1613 interconnect-names = "qup-core", "qup-config";
1614 status = "disabled";
1615 };
1616
1617 i2c6: i2c@898000 {
1618 compatible = "qcom,geni-i2c";
1619 reg = <0 0x00898000 0 0x4000>;
1620 clock-names = "se";
1621 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1622 pinctrl-names = "default";
1623 pinctrl-0 = <&qup_i2c6_default>;
1624 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1627 power-domains = <&rpmhpd SDM845_CX>;
1628 operating-points-v2 = <&qup_opp_table>;
1629 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1630 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1631 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1632 interconnect-names = "qup-core", "qup-config", "qup-memory";
1633 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1634 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1635 dma-names = "tx", "rx";
1636 status = "disabled";
1637 };
1638
1639 spi6: spi@898000 {
1640 compatible = "qcom,geni-spi";
1641 reg = <0 0x00898000 0 0x4000>;
1642 clock-names = "se";
1643 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1644 pinctrl-names = "default";
1645 pinctrl-0 = <&qup_spi6_default>;
1646 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1649 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1650 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1651 interconnect-names = "qup-core", "qup-config";
1652 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1653 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1654 dma-names = "tx", "rx";
1655 status = "disabled";
1656 };
1657
1658 uart6: serial@898000 {
1659 compatible = "qcom,geni-uart";
1660 reg = <0 0x00898000 0 0x4000>;
1661 clock-names = "se";
1662 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1663 pinctrl-names = "default";
1664 pinctrl-0 = <&qup_uart6_default>;
1665 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1666 power-domains = <&rpmhpd SDM845_CX>;
1667 operating-points-v2 = <&qup_opp_table>;
1668 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1669 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1670 interconnect-names = "qup-core", "qup-config";
1671 status = "disabled";
1672 };
1673
1674 i2c7: i2c@89c000 {
1675 compatible = "qcom,geni-i2c";
1676 reg = <0 0x0089c000 0 0x4000>;
1677 clock-names = "se";
1678 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1679 pinctrl-names = "default";
1680 pinctrl-0 = <&qup_i2c7_default>;
1681 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1682 #address-cells = <1>;
1683 #size-cells = <0>;
1684 power-domains = <&rpmhpd SDM845_CX>;
1685 operating-points-v2 = <&qup_opp_table>;
1686 status = "disabled";
1687 };
1688
1689 spi7: spi@89c000 {
1690 compatible = "qcom,geni-spi";
1691 reg = <0 0x0089c000 0 0x4000>;
1692 clock-names = "se";
1693 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1694 pinctrl-names = "default";
1695 pinctrl-0 = <&qup_spi7_default>;
1696 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1699 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1700 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1701 interconnect-names = "qup-core", "qup-config";
1702 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1703 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1704 dma-names = "tx", "rx";
1705 status = "disabled";
1706 };
1707
1708 uart7: serial@89c000 {
1709 compatible = "qcom,geni-uart";
1710 reg = <0 0x0089c000 0 0x4000>;
1711 clock-names = "se";
1712 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1713 pinctrl-names = "default";
1714 pinctrl-0 = <&qup_uart7_default>;
1715 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1716 power-domains = <&rpmhpd SDM845_CX>;
1717 operating-points-v2 = <&qup_opp_table>;
1718 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1719 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1720 interconnect-names = "qup-core", "qup-config";
1721 status = "disabled";
1722 };
1723 };
1724
1725 gpi_dma1: dma-controller@a00000 {
1726 #dma-cells = <3>;
1727 compatible = "qcom,sdm845-gpi-dma";
1728 reg = <0 0x00a00000 0 0x60000>;
1729 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1730 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1742 dma-channels = <13>;
1743 dma-channel-mask = <0xfa>;
1744 iommus = <&apps_smmu 0x06d6 0x0>;
1745 status = "disabled";
1746 };
1747
1748 qupv3_id_1: geniqup@ac0000 {
1749 compatible = "qcom,geni-se-qup";
1750 reg = <0 0x00ac0000 0 0x6000>;
1751 clock-names = "m-ahb", "s-ahb";
1752 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1753 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1754 iommus = <&apps_smmu 0x6c3 0x0>;
1755 #address-cells = <2>;
1756 #size-cells = <2>;
1757 ranges;
1758 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1759 interconnect-names = "qup-core";
1760 status = "disabled";
1761
1762 i2c8: i2c@a80000 {
1763 compatible = "qcom,geni-i2c";
1764 reg = <0 0x00a80000 0 0x4000>;
1765 clock-names = "se";
1766 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1767 pinctrl-names = "default";
1768 pinctrl-0 = <&qup_i2c8_default>;
1769 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1770 #address-cells = <1>;
1771 #size-cells = <0>;
1772 power-domains = <&rpmhpd SDM845_CX>;
1773 operating-points-v2 = <&qup_opp_table>;
1774 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1775 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1776 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1777 interconnect-names = "qup-core", "qup-config", "qup-memory";
1778 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1779 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1780 dma-names = "tx", "rx";
1781 status = "disabled";
1782 };
1783
1784 spi8: spi@a80000 {
1785 compatible = "qcom,geni-spi";
1786 reg = <0 0x00a80000 0 0x4000>;
1787 clock-names = "se";
1788 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1789 pinctrl-names = "default";
1790 pinctrl-0 = <&qup_spi8_default>;
1791 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1792 #address-cells = <1>;
1793 #size-cells = <0>;
1794 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1795 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1796 interconnect-names = "qup-core", "qup-config";
1797 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1798 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1799 dma-names = "tx", "rx";
1800 status = "disabled";
1801 };
1802
1803 uart8: serial@a80000 {
1804 compatible = "qcom,geni-uart";
1805 reg = <0 0x00a80000 0 0x4000>;
1806 clock-names = "se";
1807 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1808 pinctrl-names = "default";
1809 pinctrl-0 = <&qup_uart8_default>;
1810 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1811 power-domains = <&rpmhpd SDM845_CX>;
1812 operating-points-v2 = <&qup_opp_table>;
1813 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1814 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1815 interconnect-names = "qup-core", "qup-config";
1816 status = "disabled";
1817 };
1818
1819 i2c9: i2c@a84000 {
1820 compatible = "qcom,geni-i2c";
1821 reg = <0 0x00a84000 0 0x4000>;
1822 clock-names = "se";
1823 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1824 pinctrl-names = "default";
1825 pinctrl-0 = <&qup_i2c9_default>;
1826 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1827 #address-cells = <1>;
1828 #size-cells = <0>;
1829 power-domains = <&rpmhpd SDM845_CX>;
1830 operating-points-v2 = <&qup_opp_table>;
1831 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1832 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1833 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1834 interconnect-names = "qup-core", "qup-config", "qup-memory";
1835 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1836 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1837 dma-names = "tx", "rx";
1838 status = "disabled";
1839 };
1840
1841 spi9: spi@a84000 {
1842 compatible = "qcom,geni-spi";
1843 reg = <0 0x00a84000 0 0x4000>;
1844 clock-names = "se";
1845 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1846 pinctrl-names = "default";
1847 pinctrl-0 = <&qup_spi9_default>;
1848 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1849 #address-cells = <1>;
1850 #size-cells = <0>;
1851 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1852 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1853 interconnect-names = "qup-core", "qup-config";
1854 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1855 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1856 dma-names = "tx", "rx";
1857 status = "disabled";
1858 };
1859
1860 uart9: serial@a84000 {
1861 compatible = "qcom,geni-debug-uart";
1862 reg = <0 0x00a84000 0 0x4000>;
1863 clock-names = "se";
1864 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1865 pinctrl-names = "default";
1866 pinctrl-0 = <&qup_uart9_default>;
1867 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1868 power-domains = <&rpmhpd SDM845_CX>;
1869 operating-points-v2 = <&qup_opp_table>;
1870 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1871 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1872 interconnect-names = "qup-core", "qup-config";
1873 status = "disabled";
1874 };
1875
1876 i2c10: i2c@a88000 {
1877 compatible = "qcom,geni-i2c";
1878 reg = <0 0x00a88000 0 0x4000>;
1879 clock-names = "se";
1880 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1881 pinctrl-names = "default";
1882 pinctrl-0 = <&qup_i2c10_default>;
1883 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1884 #address-cells = <1>;
1885 #size-cells = <0>;
1886 power-domains = <&rpmhpd SDM845_CX>;
1887 operating-points-v2 = <&qup_opp_table>;
1888 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1889 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1890 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1891 interconnect-names = "qup-core", "qup-config", "qup-memory";
1892 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1893 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1894 dma-names = "tx", "rx";
1895 status = "disabled";
1896 };
1897
1898 spi10: spi@a88000 {
1899 compatible = "qcom,geni-spi";
1900 reg = <0 0x00a88000 0 0x4000>;
1901 clock-names = "se";
1902 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1903 pinctrl-names = "default";
1904 pinctrl-0 = <&qup_spi10_default>;
1905 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1906 #address-cells = <1>;
1907 #size-cells = <0>;
1908 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1909 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1910 interconnect-names = "qup-core", "qup-config";
1911 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1912 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1913 dma-names = "tx", "rx";
1914 status = "disabled";
1915 };
1916
1917 uart10: serial@a88000 {
1918 compatible = "qcom,geni-uart";
1919 reg = <0 0x00a88000 0 0x4000>;
1920 clock-names = "se";
1921 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1922 pinctrl-names = "default";
1923 pinctrl-0 = <&qup_uart10_default>;
1924 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1925 power-domains = <&rpmhpd SDM845_CX>;
1926 operating-points-v2 = <&qup_opp_table>;
1927 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1928 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1929 interconnect-names = "qup-core", "qup-config";
1930 status = "disabled";
1931 };
1932
1933 i2c11: i2c@a8c000 {
1934 compatible = "qcom,geni-i2c";
1935 reg = <0 0x00a8c000 0 0x4000>;
1936 clock-names = "se";
1937 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1938 pinctrl-names = "default";
1939 pinctrl-0 = <&qup_i2c11_default>;
1940 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1941 #address-cells = <1>;
1942 #size-cells = <0>;
1943 power-domains = <&rpmhpd SDM845_CX>;
1944 operating-points-v2 = <&qup_opp_table>;
1945 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1946 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1947 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1948 interconnect-names = "qup-core", "qup-config", "qup-memory";
1949 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1950 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1951 dma-names = "tx", "rx";
1952 status = "disabled";
1953 };
1954
1955 spi11: spi@a8c000 {
1956 compatible = "qcom,geni-spi";
1957 reg = <0 0x00a8c000 0 0x4000>;
1958 clock-names = "se";
1959 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1960 pinctrl-names = "default";
1961 pinctrl-0 = <&qup_spi11_default>;
1962 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1963 #address-cells = <1>;
1964 #size-cells = <0>;
1965 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1966 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1967 interconnect-names = "qup-core", "qup-config";
1968 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1969 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1970 dma-names = "tx", "rx";
1971 status = "disabled";
1972 };
1973
1974 uart11: serial@a8c000 {
1975 compatible = "qcom,geni-uart";
1976 reg = <0 0x00a8c000 0 0x4000>;
1977 clock-names = "se";
1978 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1979 pinctrl-names = "default";
1980 pinctrl-0 = <&qup_uart11_default>;
1981 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1982 power-domains = <&rpmhpd SDM845_CX>;
1983 operating-points-v2 = <&qup_opp_table>;
1984 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1985 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1986 interconnect-names = "qup-core", "qup-config";
1987 status = "disabled";
1988 };
1989
1990 i2c12: i2c@a90000 {
1991 compatible = "qcom,geni-i2c";
1992 reg = <0 0x00a90000 0 0x4000>;
1993 clock-names = "se";
1994 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1995 pinctrl-names = "default";
1996 pinctrl-0 = <&qup_i2c12_default>;
1997 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1998 #address-cells = <1>;
1999 #size-cells = <0>;
2000 power-domains = <&rpmhpd SDM845_CX>;
2001 operating-points-v2 = <&qup_opp_table>;
2002 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2003 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2004 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2005 interconnect-names = "qup-core", "qup-config", "qup-memory";
2006 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2007 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2008 dma-names = "tx", "rx";
2009 status = "disabled";
2010 };
2011
2012 spi12: spi@a90000 {
2013 compatible = "qcom,geni-spi";
2014 reg = <0 0x00a90000 0 0x4000>;
2015 clock-names = "se";
2016 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2017 pinctrl-names = "default";
2018 pinctrl-0 = <&qup_spi12_default>;
2019 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2020 #address-cells = <1>;
2021 #size-cells = <0>;
2022 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2023 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2024 interconnect-names = "qup-core", "qup-config";
2025 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2026 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2027 dma-names = "tx", "rx";
2028 status = "disabled";
2029 };
2030
2031 uart12: serial@a90000 {
2032 compatible = "qcom,geni-uart";
2033 reg = <0 0x00a90000 0 0x4000>;
2034 clock-names = "se";
2035 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2036 pinctrl-names = "default";
2037 pinctrl-0 = <&qup_uart12_default>;
2038 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2039 power-domains = <&rpmhpd SDM845_CX>;
2040 operating-points-v2 = <&qup_opp_table>;
2041 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2042 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2043 interconnect-names = "qup-core", "qup-config";
2044 status = "disabled";
2045 };
2046
2047 i2c13: i2c@a94000 {
2048 compatible = "qcom,geni-i2c";
2049 reg = <0 0x00a94000 0 0x4000>;
2050 clock-names = "se";
2051 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2052 pinctrl-names = "default";
2053 pinctrl-0 = <&qup_i2c13_default>;
2054 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2055 #address-cells = <1>;
2056 #size-cells = <0>;
2057 power-domains = <&rpmhpd SDM845_CX>;
2058 operating-points-v2 = <&qup_opp_table>;
2059 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2060 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2061 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2062 interconnect-names = "qup-core", "qup-config", "qup-memory";
2063 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2064 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2065 dma-names = "tx", "rx";
2066 status = "disabled";
2067 };
2068
2069 spi13: spi@a94000 {
2070 compatible = "qcom,geni-spi";
2071 reg = <0 0x00a94000 0 0x4000>;
2072 clock-names = "se";
2073 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2074 pinctrl-names = "default";
2075 pinctrl-0 = <&qup_spi13_default>;
2076 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2077 #address-cells = <1>;
2078 #size-cells = <0>;
2079 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2080 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2081 interconnect-names = "qup-core", "qup-config";
2082 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2083 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2084 dma-names = "tx", "rx";
2085 status = "disabled";
2086 };
2087
2088 uart13: serial@a94000 {
2089 compatible = "qcom,geni-uart";
2090 reg = <0 0x00a94000 0 0x4000>;
2091 clock-names = "se";
2092 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2093 pinctrl-names = "default";
2094 pinctrl-0 = <&qup_uart13_default>;
2095 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2096 power-domains = <&rpmhpd SDM845_CX>;
2097 operating-points-v2 = <&qup_opp_table>;
2098 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2099 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2100 interconnect-names = "qup-core", "qup-config";
2101 status = "disabled";
2102 };
2103
2104 i2c14: i2c@a98000 {
2105 compatible = "qcom,geni-i2c";
2106 reg = <0 0x00a98000 0 0x4000>;
2107 clock-names = "se";
2108 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2109 pinctrl-names = "default";
2110 pinctrl-0 = <&qup_i2c14_default>;
2111 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2112 #address-cells = <1>;
2113 #size-cells = <0>;
2114 power-domains = <&rpmhpd SDM845_CX>;
2115 operating-points-v2 = <&qup_opp_table>;
2116 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2117 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2118 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2119 interconnect-names = "qup-core", "qup-config", "qup-memory";
2120 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2121 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2122 dma-names = "tx", "rx";
2123 status = "disabled";
2124 };
2125
2126 spi14: spi@a98000 {
2127 compatible = "qcom,geni-spi";
2128 reg = <0 0x00a98000 0 0x4000>;
2129 clock-names = "se";
2130 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2131 pinctrl-names = "default";
2132 pinctrl-0 = <&qup_spi14_default>;
2133 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2134 #address-cells = <1>;
2135 #size-cells = <0>;
2136 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2137 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2138 interconnect-names = "qup-core", "qup-config";
2139 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2140 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2141 dma-names = "tx", "rx";
2142 status = "disabled";
2143 };
2144
2145 uart14: serial@a98000 {
2146 compatible = "qcom,geni-uart";
2147 reg = <0 0x00a98000 0 0x4000>;
2148 clock-names = "se";
2149 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2150 pinctrl-names = "default";
2151 pinctrl-0 = <&qup_uart14_default>;
2152 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2153 power-domains = <&rpmhpd SDM845_CX>;
2154 operating-points-v2 = <&qup_opp_table>;
2155 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2156 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2157 interconnect-names = "qup-core", "qup-config";
2158 status = "disabled";
2159 };
2160
2161 i2c15: i2c@a9c000 {
2162 compatible = "qcom,geni-i2c";
2163 reg = <0 0x00a9c000 0 0x4000>;
2164 clock-names = "se";
2165 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2166 pinctrl-names = "default";
2167 pinctrl-0 = <&qup_i2c15_default>;
2168 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2169 #address-cells = <1>;
2170 #size-cells = <0>;
2171 power-domains = <&rpmhpd SDM845_CX>;
2172 operating-points-v2 = <&qup_opp_table>;
2173 status = "disabled";
2174 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2175 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2176 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2177 interconnect-names = "qup-core", "qup-config", "qup-memory";
2178 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2179 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2180 dma-names = "tx", "rx";
2181 };
2182
2183 spi15: spi@a9c000 {
2184 compatible = "qcom,geni-spi";
2185 reg = <0 0x00a9c000 0 0x4000>;
2186 clock-names = "se";
2187 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2188 pinctrl-names = "default";
2189 pinctrl-0 = <&qup_spi15_default>;
2190 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2191 #address-cells = <1>;
2192 #size-cells = <0>;
2193 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2194 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2195 interconnect-names = "qup-core", "qup-config";
2196 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2197 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2198 dma-names = "tx", "rx";
2199 status = "disabled";
2200 };
2201
2202 uart15: serial@a9c000 {
2203 compatible = "qcom,geni-uart";
2204 reg = <0 0x00a9c000 0 0x4000>;
2205 clock-names = "se";
2206 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2207 pinctrl-names = "default";
2208 pinctrl-0 = <&qup_uart15_default>;
2209 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2210 power-domains = <&rpmhpd SDM845_CX>;
2211 operating-points-v2 = <&qup_opp_table>;
2212 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2213 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2214 interconnect-names = "qup-core", "qup-config";
2215 status = "disabled";
2216 };
2217 };
2218
2219 llcc: system-cache-controller@1100000 {
2220 compatible = "qcom,sdm845-llcc";
2221 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2222 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2223 <0 0x01300000 0 0x50000>;
2224 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2225 "llcc3_base", "llcc_broadcast_base";
2226 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2227 };
2228
2229 dma@10a2000 {
2230 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2231 reg = <0x0 0x010a2000 0x0 0x1000>,
2232 <0x0 0x010ae000 0x0 0x2000>;
2233 };
2234
2235 pmu@114a000 {
2236 compatible = "qcom,sdm845-llcc-bwmon";
2237 reg = <0 0x0114a000 0 0x1000>;
2238 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2239 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2240
2241 operating-points-v2 = <&llcc_bwmon_opp_table>;
2242
2243 llcc_bwmon_opp_table: opp-table {
2244 compatible = "operating-points-v2";
2245
2246 /*
2247 * The interconnect path bandwidth taken from
2248 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2249 * interconnect. This also matches the
2250 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2251 * bus width: 4 bytes) from msm-4.9 downstream
2252 * kernel.
2253 */
2254 opp-0 {
2255 opp-peak-kBps = <800000>;
2256 };
2257 opp-1 {
2258 opp-peak-kBps = <1804000>;
2259 };
2260 opp-2 {
2261 opp-peak-kBps = <3072000>;
2262 };
2263 opp-3 {
2264 opp-peak-kBps = <5412000>;
2265 };
2266 opp-4 {
2267 opp-peak-kBps = <7216000>;
2268 };
2269 };
2270 };
2271
2272 pmu@1436400 {
2273 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2274 reg = <0 0x01436400 0 0x600>;
2275 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2277
2278 operating-points-v2 = <&cpu_bwmon_opp_table>;
2279
2280 cpu_bwmon_opp_table: opp-table {
2281 compatible = "operating-points-v2";
2282
2283 /*
2284 * The interconnect path bandwidth taken from
2285 * cpu4_opp_table bandwidth for OSM L3
2286 * interconnect. This also matches the OSM L3
2287 * from bandwidth table of qcom,cpu4-l3lat-mon
2288 * (qcom,core-dev-table, bus width: 16 bytes)
2289 * from msm-4.9 downstream kernel.
2290 */
2291 opp-0 {
2292 opp-peak-kBps = <4800000>;
2293 };
2294 opp-1 {
2295 opp-peak-kBps = <9216000>;
2296 };
2297 opp-2 {
2298 opp-peak-kBps = <15052800>;
2299 };
2300 opp-3 {
2301 opp-peak-kBps = <20889600>;
2302 };
2303 opp-4 {
2304 opp-peak-kBps = <25497600>;
2305 };
2306 };
2307 };
2308
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2309 pcie0: pcie@1c00000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2310 compatible = "qcom,pcie-sdm845";
2311 reg = <0 0x01c00000 0 0x2000>,
2312 <0 0x60000000 0 0xf1d>,
2313 <0 0x60000f20 0 0xa8>,
2314 <0 0x60100000 0 0x100000>,
2315 <0 0x01c07000 0 0x1000>;
2316 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2317 device_type = "pci";
2318 linux,pci-domain = <0>;
2319 bus-range = <0x00 0xff>;
2320 num-lanes = <1>;
2321
2322 #address-cells = <3>;
2323 #size-cells = <2>;
2324
2325 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2326 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2327
2328 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2329 interrupt-names = "msi";
2330 #interrupt-cells = <1>;
2331 interrupt-map-mask = <0 0 0 0x7>;
2332 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2333 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2334 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2335 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2336
2337 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2338 <&gcc GCC_PCIE_0_AUX_CLK>,
2339 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2340 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2341 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2342 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2343 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2344 clock-names = "pipe",
2345 "aux",
2346 "cfg",
2347 "bus_master",
2348 "bus_slave",
2349 "slave_q2a",
2350 "tbu";
2351
2352 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2353 <0x100 &apps_smmu 0x1c11 0x1>,
2354 <0x200 &apps_smmu 0x1c12 0x1>,
2355 <0x300 &apps_smmu 0x1c13 0x1>,
2356 <0x400 &apps_smmu 0x1c14 0x1>,
2357 <0x500 &apps_smmu 0x1c15 0x1>,
2358 <0x600 &apps_smmu 0x1c16 0x1>,
2359 <0x700 &apps_smmu 0x1c17 0x1>,
2360 <0x800 &apps_smmu 0x1c18 0x1>,
2361 <0x900 &apps_smmu 0x1c19 0x1>,
2362 <0xa00 &apps_smmu 0x1c1a 0x1>,
2363 <0xb00 &apps_smmu 0x1c1b 0x1>,
2364 <0xc00 &apps_smmu 0x1c1c 0x1>,
2365 <0xd00 &apps_smmu 0x1c1d 0x1>,
2366 <0xe00 &apps_smmu 0x1c1e 0x1>,
2367 <0xf00 &apps_smmu 0x1c1f 0x1>;
2368
2369 resets = <&gcc GCC_PCIE_0_BCR>;
2370 reset-names = "pci";
2371
2372 power-domains = <&gcc PCIE_0_GDSC>;
2373
2374 phys = <&pcie0_phy>;
2375 phy-names = "pciephy";
2376
2377 status = "disabled";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame^]2378
2379 pcie@0 {
2380 device_type = "pci";
2381 reg = <0x0 0x0 0x0 0x0 0x0>;
2382 bus-range = <0x01 0xff>;
2383
2384 #address-cells = <3>;
2385 #size-cells = <2>;
2386 ranges;
2387 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2388 };
2389
2390 pcie0_phy: phy@1c06000 {
2391 compatible = "qcom,sdm845-qmp-pcie-phy";
2392 reg = <0 0x01c06000 0 0x1000>;
2393 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2394 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2395 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2396 <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
2397 <&gcc GCC_PCIE_0_PIPE_CLK>;
2398 clock-names = "aux",
2399 "cfg_ahb",
2400 "ref",
2401 "refgen",
2402 "pipe";
2403
2404 clock-output-names = "pcie_0_pipe_clk";
2405 #clock-cells = <0>;
2406
2407 #phy-cells = <0>;
2408
2409 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2410 reset-names = "phy";
2411
2412 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2413 assigned-clock-rates = <100000000>;
2414
2415 status = "disabled";
2416 };
2417
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2418 pcie1: pcie@1c08000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2419 compatible = "qcom,pcie-sdm845";
2420 reg = <0 0x01c08000 0 0x2000>,
2421 <0 0x40000000 0 0xf1d>,
2422 <0 0x40000f20 0 0xa8>,
2423 <0 0x40100000 0 0x100000>,
2424 <0 0x01c0c000 0 0x1000>;
2425 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2426 device_type = "pci";
2427 linux,pci-domain = <1>;
2428 bus-range = <0x00 0xff>;
2429 num-lanes = <1>;
2430
2431 #address-cells = <3>;
2432 #size-cells = <2>;
2433
2434 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2435 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2436
2437 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2438 interrupt-names = "msi";
2439 #interrupt-cells = <1>;
2440 interrupt-map-mask = <0 0 0 0x7>;
2441 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2442 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2443 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2444 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2445
2446 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2447 <&gcc GCC_PCIE_1_AUX_CLK>,
2448 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2449 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2450 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2451 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2452 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2453 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2454 clock-names = "pipe",
2455 "aux",
2456 "cfg",
2457 "bus_master",
2458 "bus_slave",
2459 "slave_q2a",
2460 "ref",
2461 "tbu";
2462
2463 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2464 assigned-clock-rates = <19200000>;
2465
2466 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2467 <0x100 &apps_smmu 0x1c01 0x1>,
2468 <0x200 &apps_smmu 0x1c02 0x1>,
2469 <0x300 &apps_smmu 0x1c03 0x1>,
2470 <0x400 &apps_smmu 0x1c04 0x1>,
2471 <0x500 &apps_smmu 0x1c05 0x1>,
2472 <0x600 &apps_smmu 0x1c06 0x1>,
2473 <0x700 &apps_smmu 0x1c07 0x1>,
2474 <0x800 &apps_smmu 0x1c08 0x1>,
2475 <0x900 &apps_smmu 0x1c09 0x1>,
2476 <0xa00 &apps_smmu 0x1c0a 0x1>,
2477 <0xb00 &apps_smmu 0x1c0b 0x1>,
2478 <0xc00 &apps_smmu 0x1c0c 0x1>,
2479 <0xd00 &apps_smmu 0x1c0d 0x1>,
2480 <0xe00 &apps_smmu 0x1c0e 0x1>,
2481 <0xf00 &apps_smmu 0x1c0f 0x1>;
2482
2483 resets = <&gcc GCC_PCIE_1_BCR>;
2484 reset-names = "pci";
2485
2486 power-domains = <&gcc PCIE_1_GDSC>;
2487
2488 phys = <&pcie1_phy>;
2489 phy-names = "pciephy";
2490
2491 status = "disabled";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame^]2492
2493 pcie@0 {
2494 device_type = "pci";
2495 reg = <0x0 0x0 0x0 0x0 0x0>;
2496 bus-range = <0x01 0xff>;
2497
2498 #address-cells = <3>;
2499 #size-cells = <2>;
2500 ranges;
2501 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2502 };
2503
2504 pcie1_phy: phy@1c0a000 {
2505 compatible = "qcom,sdm845-qhp-pcie-phy";
2506 reg = <0 0x01c0a000 0 0x2000>;
2507 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2508 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2509 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2510 <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
2511 <&gcc GCC_PCIE_1_PIPE_CLK>;
2512 clock-names = "aux",
2513 "cfg_ahb",
2514 "ref",
2515 "refgen",
2516 "pipe";
2517
2518 clock-output-names = "pcie_1_pipe_clk";
2519 #clock-cells = <0>;
2520
2521 #phy-cells = <0>;
2522
2523 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2524 reset-names = "phy";
2525
2526 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2527 assigned-clock-rates = <100000000>;
2528
2529 status = "disabled";
2530 };
2531
2532 mem_noc: interconnect@1380000 {
2533 compatible = "qcom,sdm845-mem-noc";
2534 reg = <0 0x01380000 0 0x27200>;
2535 #interconnect-cells = <2>;
2536 qcom,bcm-voters = <&apps_bcm_voter>;
2537 };
2538
2539 dc_noc: interconnect@14e0000 {
2540 compatible = "qcom,sdm845-dc-noc";
2541 reg = <0 0x014e0000 0 0x400>;
2542 #interconnect-cells = <2>;
2543 qcom,bcm-voters = <&apps_bcm_voter>;
2544 };
2545
2546 config_noc: interconnect@1500000 {
2547 compatible = "qcom,sdm845-config-noc";
2548 reg = <0 0x01500000 0 0x5080>;
2549 #interconnect-cells = <2>;
2550 qcom,bcm-voters = <&apps_bcm_voter>;
2551 };
2552
2553 system_noc: interconnect@1620000 {
2554 compatible = "qcom,sdm845-system-noc";
2555 reg = <0 0x01620000 0 0x18080>;
2556 #interconnect-cells = <2>;
2557 qcom,bcm-voters = <&apps_bcm_voter>;
2558 };
2559
2560 aggre1_noc: interconnect@16e0000 {
2561 compatible = "qcom,sdm845-aggre1-noc";
2562 reg = <0 0x016e0000 0 0x15080>;
2563 #interconnect-cells = <2>;
2564 qcom,bcm-voters = <&apps_bcm_voter>;
2565 };
2566
2567 aggre2_noc: interconnect@1700000 {
2568 compatible = "qcom,sdm845-aggre2-noc";
2569 reg = <0 0x01700000 0 0x1f300>;
2570 #interconnect-cells = <2>;
2571 qcom,bcm-voters = <&apps_bcm_voter>;
2572 };
2573
2574 mmss_noc: interconnect@1740000 {
2575 compatible = "qcom,sdm845-mmss-noc";
2576 reg = <0 0x01740000 0 0x1c100>;
2577 #interconnect-cells = <2>;
2578 qcom,bcm-voters = <&apps_bcm_voter>;
2579 };
2580
2581 ufs_mem_hc: ufshc@1d84000 {
2582 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2583 "jedec,ufs-2.0";
2584 reg = <0 0x01d84000 0 0x2500>,
2585 <0 0x01d90000 0 0x8000>;
2586 reg-names = "std", "ice";
2587 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2588 phys = <&ufs_mem_phy>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2589 phy-names = "ufsphy";
2590 lanes-per-direction = <2>;
2591 power-domains = <&gcc UFS_PHY_GDSC>;
2592 #reset-cells = <1>;
2593 resets = <&gcc GCC_UFS_PHY_BCR>;
2594 reset-names = "rst";
2595
2596 iommus = <&apps_smmu 0x100 0xf>;
2597
2598 clock-names =
2599 "core_clk",
2600 "bus_aggr_clk",
2601 "iface_clk",
2602 "core_clk_unipro",
2603 "ref_clk",
2604 "tx_lane0_sync_clk",
2605 "rx_lane0_sync_clk",
2606 "rx_lane1_sync_clk",
2607 "ice_core_clk";
2608 clocks =
2609 <&gcc GCC_UFS_PHY_AXI_CLK>,
2610 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_UFS_PHY_AHB_CLK>,
2612 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2613 <&rpmhcc RPMH_CXO_CLK>,
2614 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2615 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2617 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2618
2619 operating-points-v2 = <&ufs_opp_table>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2620
2621 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
2622 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2623 interconnect-names = "ufs-ddr", "cpu-ufs";
2624
2625 status = "disabled";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2626
2627 ufs_opp_table: opp-table {
2628 compatible = "operating-points-v2";
2629
2630 opp-50000000 {
2631 opp-hz = /bits/ 64 <50000000>,
2632 /bits/ 64 <0>,
2633 /bits/ 64 <0>,
2634 /bits/ 64 <37500000>,
2635 /bits/ 64 <0>,
2636 /bits/ 64 <0>,
2637 /bits/ 64 <0>,
2638 /bits/ 64 <0>,
2639 /bits/ 64 <75000000>;
2640 required-opps = <&rpmhpd_opp_low_svs>;
2641 };
2642
2643 opp-200000000 {
2644 opp-hz = /bits/ 64 <200000000>,
2645 /bits/ 64 <0>,
2646 /bits/ 64 <0>,
2647 /bits/ 64 <150000000>,
2648 /bits/ 64 <0>,
2649 /bits/ 64 <0>,
2650 /bits/ 64 <0>,
2651 /bits/ 64 <0>,
2652 /bits/ 64 <300000000>;
2653 required-opps = <&rpmhpd_opp_nom>;
2654 };
2655 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2656 };
2657
2658 ufs_mem_phy: phy@1d87000 {
2659 compatible = "qcom,sdm845-qmp-ufs-phy";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2660 reg = <0 0x01d87000 0 0x1000>;
2661
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]2662 clocks = <&rpmhcc RPMH_CXO_CLK>,
2663 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2664 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2665 clock-names = "ref",
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]2666 "ref_aux",
2667 "qref";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2668
2669 resets = <&ufs_mem_hc 0>;
2670 reset-names = "ufsphy";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2671
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2672 #phy-cells = <0>;
2673 status = "disabled";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2674 };
2675
2676 cryptobam: dma-controller@1dc4000 {
2677 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2678 reg = <0 0x01dc4000 0 0x24000>;
2679 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2680 clocks = <&rpmhcc RPMH_CE_CLK>;
2681 clock-names = "bam_clk";
2682 #dma-cells = <1>;
2683 qcom,ee = <0>;
2684 qcom,controlled-remotely;
2685 iommus = <&apps_smmu 0x704 0x1>,
2686 <&apps_smmu 0x706 0x1>,
2687 <&apps_smmu 0x714 0x1>,
2688 <&apps_smmu 0x716 0x1>;
2689 };
2690
2691 crypto: crypto@1dfa000 {
2692 compatible = "qcom,crypto-v5.4";
2693 reg = <0 0x01dfa000 0 0x6000>;
2694 clocks = <&gcc GCC_CE1_AHB_CLK>,
2695 <&gcc GCC_CE1_AXI_CLK>,
2696 <&rpmhcc RPMH_CE_CLK>;
2697 clock-names = "iface", "bus", "core";
2698 dmas = <&cryptobam 6>, <&cryptobam 7>;
2699 dma-names = "rx", "tx";
2700 iommus = <&apps_smmu 0x704 0x1>,
2701 <&apps_smmu 0x706 0x1>,
2702 <&apps_smmu 0x714 0x1>,
2703 <&apps_smmu 0x716 0x1>;
2704 };
2705
2706 ipa: ipa@1e40000 {
2707 compatible = "qcom,sdm845-ipa";
2708
2709 iommus = <&apps_smmu 0x720 0x0>,
2710 <&apps_smmu 0x722 0x0>;
2711 reg = <0 0x01e40000 0 0x7000>,
2712 <0 0x01e47000 0 0x2000>,
2713 <0 0x01e04000 0 0x2c000>;
2714 reg-names = "ipa-reg",
2715 "ipa-shared",
2716 "gsi";
2717
2718 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2719 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2720 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2721 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2722 interrupt-names = "ipa",
2723 "gsi",
2724 "ipa-clock-query",
2725 "ipa-setup-ready";
2726
2727 clocks = <&rpmhcc RPMH_IPA_CLK>;
2728 clock-names = "core";
2729
2730 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2731 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2732 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2733 interconnect-names = "memory",
2734 "imem",
2735 "config";
2736
2737 qcom,smem-states = <&ipa_smp2p_out 0>,
2738 <&ipa_smp2p_out 1>;
2739 qcom,smem-state-names = "ipa-clock-enabled-valid",
2740 "ipa-clock-enabled";
2741
2742 status = "disabled";
2743 };
2744
2745 tcsr_mutex: hwlock@1f40000 {
2746 compatible = "qcom,tcsr-mutex";
2747 reg = <0 0x01f40000 0 0x20000>;
2748 #hwlock-cells = <1>;
2749 };
2750
2751 tcsr_regs_1: syscon@1f60000 {
2752 compatible = "qcom,sdm845-tcsr", "syscon";
2753 reg = <0 0x01f60000 0 0x20000>;
2754 };
2755
2756 tlmm: pinctrl@3400000 {
2757 compatible = "qcom,sdm845-pinctrl";
2758 reg = <0 0x03400000 0 0xc00000>;
2759 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2760 gpio-controller;
2761 #gpio-cells = <2>;
2762 interrupt-controller;
2763 #interrupt-cells = <2>;
2764 gpio-ranges = <&tlmm 0 0 151>;
2765 wakeup-parent = <&pdc_intc>;
2766
2767 cci0_default: cci0-default-state {
2768 /* SDA, SCL */
2769 pins = "gpio17", "gpio18";
2770 function = "cci_i2c";
2771
2772 bias-pull-up;
2773 drive-strength = <2>; /* 2 mA */
2774 };
2775
2776 cci0_sleep: cci0-sleep-state {
2777 /* SDA, SCL */
2778 pins = "gpio17", "gpio18";
2779 function = "cci_i2c";
2780
2781 drive-strength = <2>; /* 2 mA */
2782 bias-pull-down;
2783 };
2784
2785 cci1_default: cci1-default-state {
2786 /* SDA, SCL */
2787 pins = "gpio19", "gpio20";
2788 function = "cci_i2c";
2789
2790 bias-pull-up;
2791 drive-strength = <2>; /* 2 mA */
2792 };
2793
2794 cci1_sleep: cci1-sleep-state {
2795 /* SDA, SCL */
2796 pins = "gpio19", "gpio20";
2797 function = "cci_i2c";
2798
2799 drive-strength = <2>; /* 2 mA */
2800 bias-pull-down;
2801 };
2802
2803 qspi_clk: qspi-clk-state {
2804 pins = "gpio95";
2805 function = "qspi_clk";
2806 };
2807
2808 qspi_cs0: qspi-cs0-state {
2809 pins = "gpio90";
2810 function = "qspi_cs";
2811 };
2812
2813 qspi_cs1: qspi-cs1-state {
2814 pins = "gpio89";
2815 function = "qspi_cs";
2816 };
2817
2818 qspi_data0: qspi-data0-state {
2819 pins = "gpio91";
2820 function = "qspi_data";
2821 };
2822
2823 qspi_data1: qspi-data1-state {
2824 pins = "gpio92";
2825 function = "qspi_data";
2826 };
2827
2828 qspi_data23: qspi-data23-state {
2829 pins = "gpio93", "gpio94";
2830 function = "qspi_data";
2831 };
2832
2833 qup_i2c0_default: qup-i2c0-default-state {
2834 pins = "gpio0", "gpio1";
2835 function = "qup0";
2836 };
2837
2838 qup_i2c1_default: qup-i2c1-default-state {
2839 pins = "gpio17", "gpio18";
2840 function = "qup1";
2841 };
2842
2843 qup_i2c2_default: qup-i2c2-default-state {
2844 pins = "gpio27", "gpio28";
2845 function = "qup2";
2846 };
2847
2848 qup_i2c3_default: qup-i2c3-default-state {
2849 pins = "gpio41", "gpio42";
2850 function = "qup3";
2851 };
2852
2853 qup_i2c4_default: qup-i2c4-default-state {
2854 pins = "gpio89", "gpio90";
2855 function = "qup4";
2856 };
2857
2858 qup_i2c5_default: qup-i2c5-default-state {
2859 pins = "gpio85", "gpio86";
2860 function = "qup5";
2861 };
2862
2863 qup_i2c6_default: qup-i2c6-default-state {
2864 pins = "gpio45", "gpio46";
2865 function = "qup6";
2866 };
2867
2868 qup_i2c7_default: qup-i2c7-default-state {
2869 pins = "gpio93", "gpio94";
2870 function = "qup7";
2871 };
2872
2873 qup_i2c8_default: qup-i2c8-default-state {
2874 pins = "gpio65", "gpio66";
2875 function = "qup8";
2876 };
2877
2878 qup_i2c9_default: qup-i2c9-default-state {
2879 pins = "gpio6", "gpio7";
2880 function = "qup9";
2881 };
2882
2883 qup_i2c10_default: qup-i2c10-default-state {
2884 pins = "gpio55", "gpio56";
2885 function = "qup10";
2886 };
2887
2888 qup_i2c11_default: qup-i2c11-default-state {
2889 pins = "gpio31", "gpio32";
2890 function = "qup11";
2891 };
2892
2893 qup_i2c12_default: qup-i2c12-default-state {
2894 pins = "gpio49", "gpio50";
2895 function = "qup12";
2896 };
2897
2898 qup_i2c13_default: qup-i2c13-default-state {
2899 pins = "gpio105", "gpio106";
2900 function = "qup13";
2901 };
2902
2903 qup_i2c14_default: qup-i2c14-default-state {
2904 pins = "gpio33", "gpio34";
2905 function = "qup14";
2906 };
2907
2908 qup_i2c15_default: qup-i2c15-default-state {
2909 pins = "gpio81", "gpio82";
2910 function = "qup15";
2911 };
2912
2913 qup_spi0_default: qup-spi0-default-state {
2914 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2915 function = "qup0";
2916 };
2917
2918 qup_spi1_default: qup-spi1-default-state {
2919 pins = "gpio17", "gpio18", "gpio19", "gpio20";
2920 function = "qup1";
2921 };
2922
2923 qup_spi2_default: qup-spi2-default-state {
2924 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2925 function = "qup2";
2926 };
2927
2928 qup_spi3_default: qup-spi3-default-state {
2929 pins = "gpio41", "gpio42", "gpio43", "gpio44";
2930 function = "qup3";
2931 };
2932
2933 qup_spi4_default: qup-spi4-default-state {
2934 pins = "gpio89", "gpio90", "gpio91", "gpio92";
2935 function = "qup4";
2936 };
2937
2938 qup_spi5_default: qup-spi5-default-state {
2939 pins = "gpio85", "gpio86", "gpio87", "gpio88";
2940 function = "qup5";
2941 };
2942
2943 qup_spi6_default: qup-spi6-default-state {
2944 pins = "gpio45", "gpio46", "gpio47", "gpio48";
2945 function = "qup6";
2946 };
2947
2948 qup_spi7_default: qup-spi7-default-state {
2949 pins = "gpio93", "gpio94", "gpio95", "gpio96";
2950 function = "qup7";
2951 };
2952
2953 qup_spi8_default: qup-spi8-default-state {
2954 pins = "gpio65", "gpio66", "gpio67", "gpio68";
2955 function = "qup8";
2956 };
2957
2958 qup_spi9_default: qup-spi9-default-state {
2959 pins = "gpio6", "gpio7", "gpio4", "gpio5";
2960 function = "qup9";
2961 };
2962
2963 qup_spi10_default: qup-spi10-default-state {
2964 pins = "gpio55", "gpio56", "gpio53", "gpio54";
2965 function = "qup10";
2966 };
2967
2968 qup_spi11_default: qup-spi11-default-state {
2969 pins = "gpio31", "gpio32", "gpio33", "gpio34";
2970 function = "qup11";
2971 };
2972
2973 qup_spi12_default: qup-spi12-default-state {
2974 pins = "gpio49", "gpio50", "gpio51", "gpio52";
2975 function = "qup12";
2976 };
2977
2978 qup_spi13_default: qup-spi13-default-state {
2979 pins = "gpio105", "gpio106", "gpio107", "gpio108";
2980 function = "qup13";
2981 };
2982
2983 qup_spi14_default: qup-spi14-default-state {
2984 pins = "gpio33", "gpio34", "gpio31", "gpio32";
2985 function = "qup14";
2986 };
2987
2988 qup_spi15_default: qup-spi15-default-state {
2989 pins = "gpio81", "gpio82", "gpio83", "gpio84";
2990 function = "qup15";
2991 };
2992
2993 qup_uart0_default: qup-uart0-default-state {
2994 qup_uart0_tx: tx-pins {
2995 pins = "gpio2";
2996 function = "qup0";
2997 };
2998
2999 qup_uart0_rx: rx-pins {
3000 pins = "gpio3";
3001 function = "qup0";
3002 };
3003 };
3004
3005 qup_uart1_default: qup-uart1-default-state {
3006 qup_uart1_tx: tx-pins {
3007 pins = "gpio19";
3008 function = "qup1";
3009 };
3010
3011 qup_uart1_rx: rx-pins {
3012 pins = "gpio20";
3013 function = "qup1";
3014 };
3015 };
3016
3017 qup_uart2_default: qup-uart2-default-state {
3018 qup_uart2_tx: tx-pins {
3019 pins = "gpio29";
3020 function = "qup2";
3021 };
3022
3023 qup_uart2_rx: rx-pins {
3024 pins = "gpio30";
3025 function = "qup2";
3026 };
3027 };
3028
3029 qup_uart3_default: qup-uart3-default-state {
3030 qup_uart3_tx: tx-pins {
3031 pins = "gpio43";
3032 function = "qup3";
3033 };
3034
3035 qup_uart3_rx: rx-pins {
3036 pins = "gpio44";
3037 function = "qup3";
3038 };
3039 };
3040
3041 qup_uart3_4pin: qup-uart3-4pin-state {
3042 qup_uart3_4pin_cts: cts-pins {
3043 pins = "gpio41";
3044 function = "qup3";
3045 };
3046
3047 qup_uart3_4pin_rts_tx: rts-tx-pins {
3048 pins = "gpio42", "gpio43";
3049 function = "qup3";
3050 };
3051
3052 qup_uart3_4pin_rx: rx-pins {
3053 pins = "gpio44";
3054 function = "qup3";
3055 };
3056 };
3057
3058 qup_uart4_default: qup-uart4-default-state {
3059 qup_uart4_tx: tx-pins {
3060 pins = "gpio91";
3061 function = "qup4";
3062 };
3063
3064 qup_uart4_rx: rx-pins {
3065 pins = "gpio92";
3066 function = "qup4";
3067 };
3068 };
3069
3070 qup_uart5_default: qup-uart5-default-state {
3071 qup_uart5_tx: tx-pins {
3072 pins = "gpio87";
3073 function = "qup5";
3074 };
3075
3076 qup_uart5_rx: rx-pins {
3077 pins = "gpio88";
3078 function = "qup5";
3079 };
3080 };
3081
3082 qup_uart6_default: qup-uart6-default-state {
3083 qup_uart6_tx: tx-pins {
3084 pins = "gpio47";
3085 function = "qup6";
3086 };
3087
3088 qup_uart6_rx: rx-pins {
3089 pins = "gpio48";
3090 function = "qup6";
3091 };
3092 };
3093
3094 qup_uart6_4pin: qup-uart6-4pin-state {
3095 qup_uart6_4pin_cts: cts-pins {
3096 pins = "gpio45";
3097 function = "qup6";
3098 bias-pull-down;
3099 };
3100
3101 qup_uart6_4pin_rts_tx: rts-tx-pins {
3102 pins = "gpio46", "gpio47";
3103 function = "qup6";
3104 drive-strength = <2>;
3105 bias-disable;
3106 };
3107
3108 qup_uart6_4pin_rx: rx-pins {
3109 pins = "gpio48";
3110 function = "qup6";
3111 bias-pull-up;
3112 };
3113 };
3114
3115 qup_uart7_default: qup-uart7-default-state {
3116 qup_uart7_tx: tx-pins {
3117 pins = "gpio95";
3118 function = "qup7";
3119 };
3120
3121 qup_uart7_rx: rx-pins {
3122 pins = "gpio96";
3123 function = "qup7";
3124 };
3125 };
3126
3127 qup_uart8_default: qup-uart8-default-state {
3128 qup_uart8_tx: tx-pins {
3129 pins = "gpio67";
3130 function = "qup8";
3131 };
3132
3133 qup_uart8_rx: rx-pins {
3134 pins = "gpio68";
3135 function = "qup8";
3136 };
3137 };
3138
3139 qup_uart9_default: qup-uart9-default-state {
3140 qup_uart9_tx: tx-pins {
3141 pins = "gpio4";
3142 function = "qup9";
3143 };
3144
3145 qup_uart9_rx: rx-pins {
3146 pins = "gpio5";
3147 function = "qup9";
3148 };
3149 };
3150
3151 qup_uart10_default: qup-uart10-default-state {
3152 qup_uart10_tx: tx-pins {
3153 pins = "gpio53";
3154 function = "qup10";
3155 };
3156
3157 qup_uart10_rx: rx-pins {
3158 pins = "gpio54";
3159 function = "qup10";
3160 };
3161 };
3162
3163 qup_uart11_default: qup-uart11-default-state {
3164 qup_uart11_tx: tx-pins {
3165 pins = "gpio33";
3166 function = "qup11";
3167 };
3168
3169 qup_uart11_rx: rx-pins {
3170 pins = "gpio34";
3171 function = "qup11";
3172 };
3173 };
3174
3175 qup_uart12_default: qup-uart12-default-state {
3176 qup_uart12_tx: tx-pins {
3177 pins = "gpio51";
3178 function = "qup0";
3179 };
3180
3181 qup_uart12_rx: rx-pins {
3182 pins = "gpio52";
3183 function = "qup0";
3184 };
3185 };
3186
3187 qup_uart13_default: qup-uart13-default-state {
3188 qup_uart13_tx: tx-pins {
3189 pins = "gpio107";
3190 function = "qup13";
3191 };
3192
3193 qup_uart13_rx: rx-pins {
3194 pins = "gpio108";
3195 function = "qup13";
3196 };
3197 };
3198
3199 qup_uart14_default: qup-uart14-default-state {
3200 qup_uart14_tx: tx-pins {
3201 pins = "gpio31";
3202 function = "qup14";
3203 };
3204
3205 qup_uart14_rx: rx-pins {
3206 pins = "gpio32";
3207 function = "qup14";
3208 };
3209 };
3210
3211 qup_uart15_default: qup-uart15-default-state {
3212 qup_uart15_tx: tx-pins {
3213 pins = "gpio83";
3214 function = "qup15";
3215 };
3216
3217 qup_uart15_rx: rx-pins {
3218 pins = "gpio84";
3219 function = "qup15";
3220 };
3221 };
3222
3223 quat_mi2s_sleep: quat-mi2s-sleep-state {
3224 pins = "gpio58", "gpio59";
3225 function = "gpio";
3226 drive-strength = <2>;
3227 bias-pull-down;
3228 };
3229
3230 quat_mi2s_active: quat-mi2s-active-state {
3231 pins = "gpio58", "gpio59";
3232 function = "qua_mi2s";
3233 drive-strength = <8>;
3234 bias-disable;
3235 output-high;
3236 };
3237
3238 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3239 pins = "gpio60";
3240 function = "gpio";
3241 drive-strength = <2>;
3242 bias-pull-down;
3243 };
3244
3245 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3246 pins = "gpio60";
3247 function = "qua_mi2s";
3248 drive-strength = <8>;
3249 bias-disable;
3250 };
3251
3252 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3253 pins = "gpio61";
3254 function = "gpio";
3255 drive-strength = <2>;
3256 bias-pull-down;
3257 };
3258
3259 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3260 pins = "gpio61";
3261 function = "qua_mi2s";
3262 drive-strength = <8>;
3263 bias-disable;
3264 };
3265
3266 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3267 pins = "gpio62";
3268 function = "gpio";
3269 drive-strength = <2>;
3270 bias-pull-down;
3271 };
3272
3273 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3274 pins = "gpio62";
3275 function = "qua_mi2s";
3276 drive-strength = <8>;
3277 bias-disable;
3278 };
3279
3280 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3281 pins = "gpio63";
3282 function = "gpio";
3283 drive-strength = <2>;
3284 bias-pull-down;
3285 };
3286
3287 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3288 pins = "gpio63";
3289 function = "qua_mi2s";
3290 drive-strength = <8>;
3291 bias-disable;
3292 };
3293 };
3294
3295 mss_pil: remoteproc@4080000 {
3296 compatible = "qcom,sdm845-mss-pil";
3297 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3298 reg-names = "qdsp6", "rmb";
3299
3300 interrupts-extended =
3301 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3302 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3303 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3304 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3307 interrupt-names = "wdog", "fatal", "ready",
3308 "handover", "stop-ack",
3309 "shutdown-ack";
3310
3311 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3312 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3313 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3314 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3315 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3316 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3317 <&gcc GCC_PRNG_AHB_CLK>,
3318 <&rpmhcc RPMH_CXO_CLK>;
3319 clock-names = "iface", "bus", "mem", "gpll0_mss",
3320 "snoc_axi", "mnoc_axi", "prng", "xo";
3321
3322 qcom,qmp = <&aoss_qmp>;
3323
3324 qcom,smem-states = <&modem_smp2p_out 0>;
3325 qcom,smem-state-names = "stop";
3326
3327 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3328 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3329 reset-names = "mss_restart", "pdc_reset";
3330
3331 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3332
3333 power-domains = <&rpmhpd SDM845_CX>,
3334 <&rpmhpd SDM845_MX>,
3335 <&rpmhpd SDM845_MSS>;
3336 power-domain-names = "cx", "mx", "mss";
3337
3338 status = "disabled";
3339
3340 mba {
3341 memory-region = <&mba_region>;
3342 };
3343
3344 mpss {
3345 memory-region = <&mpss_region>;
3346 };
3347
3348 metadata {
3349 memory-region = <&mdata_mem>;
3350 };
3351
3352 glink-edge {
3353 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3354 label = "modem";
3355 qcom,remote-pid = <1>;
3356 mboxes = <&apss_shared 12>;
3357 };
3358 };
3359
3360 gpucc: clock-controller@5090000 {
3361 compatible = "qcom,sdm845-gpucc";
3362 reg = <0 0x05090000 0 0x9000>;
3363 #clock-cells = <1>;
3364 #reset-cells = <1>;
3365 #power-domain-cells = <1>;
3366 clocks = <&rpmhcc RPMH_CXO_CLK>,
3367 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3368 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3369 clock-names = "bi_tcxo",
3370 "gcc_gpu_gpll0_clk_src",
3371 "gcc_gpu_gpll0_div_clk_src";
3372 };
3373
3374 slpi_pas: remoteproc@5c00000 {
3375 compatible = "qcom,sdm845-slpi-pas";
3376 reg = <0 0x5c00000 0 0x4000>;
3377
3378 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3379 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3380 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3381 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3382 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3383 interrupt-names = "wdog", "fatal", "ready",
3384 "handover", "stop-ack";
3385
3386 clocks = <&rpmhcc RPMH_CXO_CLK>;
3387 clock-names = "xo";
3388
3389 qcom,qmp = <&aoss_qmp>;
3390
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]3391 power-domains = <&rpmhpd SDM845_LCX>,
3392 <&rpmhpd SDM845_LMX>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3393 power-domain-names = "lcx", "lmx";
3394
3395 memory-region = <&slpi_mem>;
3396
3397 qcom,smem-states = <&slpi_smp2p_out 0>;
3398 qcom,smem-state-names = "stop";
3399
3400 status = "disabled";
3401
3402 glink-edge {
3403 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
3404 label = "dsps";
3405 qcom,remote-pid = <3>;
3406 mboxes = <&apss_shared 24>;
3407
3408 fastrpc {
3409 compatible = "qcom,fastrpc";
3410 qcom,glink-channels = "fastrpcglink-apps-dsp";
3411 label = "sdsp";
3412 qcom,non-secure-domain;
3413 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA
3414 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>;
3415 memory-region = <&fastrpc_mem>;
3416 #address-cells = <1>;
3417 #size-cells = <0>;
3418
3419 compute-cb@0 {
3420 compatible = "qcom,fastrpc-compute-cb";
3421 reg = <0>;
3422 };
3423 };
3424 };
3425 };
3426
3427 stm@6002000 {
3428 compatible = "arm,coresight-stm", "arm,primecell";
3429 reg = <0 0x06002000 0 0x1000>,
3430 <0 0x16280000 0 0x180000>;
3431 reg-names = "stm-base", "stm-stimulus-base";
3432
3433 clocks = <&aoss_qmp>;
3434 clock-names = "apb_pclk";
3435
3436 out-ports {
3437 port {
3438 stm_out: endpoint {
3439 remote-endpoint =
3440 <&funnel0_in7>;
3441 };
3442 };
3443 };
3444 };
3445
3446 funnel@6041000 {
3447 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3448 reg = <0 0x06041000 0 0x1000>;
3449
3450 clocks = <&aoss_qmp>;
3451 clock-names = "apb_pclk";
3452
3453 out-ports {
3454 port {
3455 funnel0_out: endpoint {
3456 remote-endpoint =
3457 <&merge_funnel_in0>;
3458 };
3459 };
3460 };
3461
3462 in-ports {
3463 #address-cells = <1>;
3464 #size-cells = <0>;
3465
3466 port@7 {
3467 reg = <7>;
3468 funnel0_in7: endpoint {
3469 remote-endpoint = <&stm_out>;
3470 };
3471 };
3472 };
3473 };
3474
3475 funnel@6043000 {
3476 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3477 reg = <0 0x06043000 0 0x1000>;
3478
3479 clocks = <&aoss_qmp>;
3480 clock-names = "apb_pclk";
3481
3482 out-ports {
3483 port {
3484 funnel2_out: endpoint {
3485 remote-endpoint =
3486 <&merge_funnel_in2>;
3487 };
3488 };
3489 };
3490
3491 in-ports {
3492 #address-cells = <1>;
3493 #size-cells = <0>;
3494
3495 port@5 {
3496 reg = <5>;
3497 funnel2_in5: endpoint {
3498 remote-endpoint =
3499 <&apss_merge_funnel_out>;
3500 };
3501 };
3502 };
3503 };
3504
3505 funnel@6045000 {
3506 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3507 reg = <0 0x06045000 0 0x1000>;
3508
3509 clocks = <&aoss_qmp>;
3510 clock-names = "apb_pclk";
3511
3512 out-ports {
3513 port {
3514 merge_funnel_out: endpoint {
3515 remote-endpoint = <&etf_in>;
3516 };
3517 };
3518 };
3519
3520 in-ports {
3521 #address-cells = <1>;
3522 #size-cells = <0>;
3523
3524 port@0 {
3525 reg = <0>;
3526 merge_funnel_in0: endpoint {
3527 remote-endpoint =
3528 <&funnel0_out>;
3529 };
3530 };
3531
3532 port@2 {
3533 reg = <2>;
3534 merge_funnel_in2: endpoint {
3535 remote-endpoint =
3536 <&funnel2_out>;
3537 };
3538 };
3539 };
3540 };
3541
3542 replicator@6046000 {
3543 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3544 reg = <0 0x06046000 0 0x1000>;
3545
3546 clocks = <&aoss_qmp>;
3547 clock-names = "apb_pclk";
3548
3549 out-ports {
3550 port {
3551 replicator_out: endpoint {
3552 remote-endpoint = <&etr_in>;
3553 };
3554 };
3555 };
3556
3557 in-ports {
3558 port {
3559 replicator_in: endpoint {
3560 remote-endpoint = <&etf_out>;
3561 };
3562 };
3563 };
3564 };
3565
3566 etf@6047000 {
3567 compatible = "arm,coresight-tmc", "arm,primecell";
3568 reg = <0 0x06047000 0 0x1000>;
3569
3570 clocks = <&aoss_qmp>;
3571 clock-names = "apb_pclk";
3572
3573 out-ports {
3574 port {
3575 etf_out: endpoint {
3576 remote-endpoint =
3577 <&replicator_in>;
3578 };
3579 };
3580 };
3581
3582 in-ports {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3583
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3584 port {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3585 etf_in: endpoint {
3586 remote-endpoint =
3587 <&merge_funnel_out>;
3588 };
3589 };
3590 };
3591 };
3592
3593 etr@6048000 {
3594 compatible = "arm,coresight-tmc", "arm,primecell";
3595 reg = <0 0x06048000 0 0x1000>;
3596
3597 clocks = <&aoss_qmp>;
3598 clock-names = "apb_pclk";
3599 arm,scatter-gather;
3600
3601 in-ports {
3602 port {
3603 etr_in: endpoint {
3604 remote-endpoint =
3605 <&replicator_out>;
3606 };
3607 };
3608 };
3609 };
3610
3611 etm@7040000 {
3612 compatible = "arm,coresight-etm4x", "arm,primecell";
3613 reg = <0 0x07040000 0 0x1000>;
3614
3615 cpu = <&CPU0>;
3616
3617 clocks = <&aoss_qmp>;
3618 clock-names = "apb_pclk";
3619 arm,coresight-loses-context-with-cpu;
3620
3621 out-ports {
3622 port {
3623 etm0_out: endpoint {
3624 remote-endpoint =
3625 <&apss_funnel_in0>;
3626 };
3627 };
3628 };
3629 };
3630
3631 etm@7140000 {
3632 compatible = "arm,coresight-etm4x", "arm,primecell";
3633 reg = <0 0x07140000 0 0x1000>;
3634
3635 cpu = <&CPU1>;
3636
3637 clocks = <&aoss_qmp>;
3638 clock-names = "apb_pclk";
3639 arm,coresight-loses-context-with-cpu;
3640
3641 out-ports {
3642 port {
3643 etm1_out: endpoint {
3644 remote-endpoint =
3645 <&apss_funnel_in1>;
3646 };
3647 };
3648 };
3649 };
3650
3651 etm@7240000 {
3652 compatible = "arm,coresight-etm4x", "arm,primecell";
3653 reg = <0 0x07240000 0 0x1000>;
3654
3655 cpu = <&CPU2>;
3656
3657 clocks = <&aoss_qmp>;
3658 clock-names = "apb_pclk";
3659 arm,coresight-loses-context-with-cpu;
3660
3661 out-ports {
3662 port {
3663 etm2_out: endpoint {
3664 remote-endpoint =
3665 <&apss_funnel_in2>;
3666 };
3667 };
3668 };
3669 };
3670
3671 etm@7340000 {
3672 compatible = "arm,coresight-etm4x", "arm,primecell";
3673 reg = <0 0x07340000 0 0x1000>;
3674
3675 cpu = <&CPU3>;
3676
3677 clocks = <&aoss_qmp>;
3678 clock-names = "apb_pclk";
3679 arm,coresight-loses-context-with-cpu;
3680
3681 out-ports {
3682 port {
3683 etm3_out: endpoint {
3684 remote-endpoint =
3685 <&apss_funnel_in3>;
3686 };
3687 };
3688 };
3689 };
3690
3691 etm@7440000 {
3692 compatible = "arm,coresight-etm4x", "arm,primecell";
3693 reg = <0 0x07440000 0 0x1000>;
3694
3695 cpu = <&CPU4>;
3696
3697 clocks = <&aoss_qmp>;
3698 clock-names = "apb_pclk";
3699 arm,coresight-loses-context-with-cpu;
3700
3701 out-ports {
3702 port {
3703 etm4_out: endpoint {
3704 remote-endpoint =
3705 <&apss_funnel_in4>;
3706 };
3707 };
3708 };
3709 };
3710
3711 etm@7540000 {
3712 compatible = "arm,coresight-etm4x", "arm,primecell";
3713 reg = <0 0x07540000 0 0x1000>;
3714
3715 cpu = <&CPU5>;
3716
3717 clocks = <&aoss_qmp>;
3718 clock-names = "apb_pclk";
3719 arm,coresight-loses-context-with-cpu;
3720
3721 out-ports {
3722 port {
3723 etm5_out: endpoint {
3724 remote-endpoint =
3725 <&apss_funnel_in5>;
3726 };
3727 };
3728 };
3729 };
3730
3731 etm@7640000 {
3732 compatible = "arm,coresight-etm4x", "arm,primecell";
3733 reg = <0 0x07640000 0 0x1000>;
3734
3735 cpu = <&CPU6>;
3736
3737 clocks = <&aoss_qmp>;
3738 clock-names = "apb_pclk";
3739 arm,coresight-loses-context-with-cpu;
3740
3741 out-ports {
3742 port {
3743 etm6_out: endpoint {
3744 remote-endpoint =
3745 <&apss_funnel_in6>;
3746 };
3747 };
3748 };
3749 };
3750
3751 etm@7740000 {
3752 compatible = "arm,coresight-etm4x", "arm,primecell";
3753 reg = <0 0x07740000 0 0x1000>;
3754
3755 cpu = <&CPU7>;
3756
3757 clocks = <&aoss_qmp>;
3758 clock-names = "apb_pclk";
3759 arm,coresight-loses-context-with-cpu;
3760
3761 out-ports {
3762 port {
3763 etm7_out: endpoint {
3764 remote-endpoint =
3765 <&apss_funnel_in7>;
3766 };
3767 };
3768 };
3769 };
3770
3771 funnel@7800000 { /* APSS Funnel */
3772 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3773 reg = <0 0x07800000 0 0x1000>;
3774
3775 clocks = <&aoss_qmp>;
3776 clock-names = "apb_pclk";
3777
3778 out-ports {
3779 port {
3780 apss_funnel_out: endpoint {
3781 remote-endpoint =
3782 <&apss_merge_funnel_in>;
3783 };
3784 };
3785 };
3786
3787 in-ports {
3788 #address-cells = <1>;
3789 #size-cells = <0>;
3790
3791 port@0 {
3792 reg = <0>;
3793 apss_funnel_in0: endpoint {
3794 remote-endpoint =
3795 <&etm0_out>;
3796 };
3797 };
3798
3799 port@1 {
3800 reg = <1>;
3801 apss_funnel_in1: endpoint {
3802 remote-endpoint =
3803 <&etm1_out>;
3804 };
3805 };
3806
3807 port@2 {
3808 reg = <2>;
3809 apss_funnel_in2: endpoint {
3810 remote-endpoint =
3811 <&etm2_out>;
3812 };
3813 };
3814
3815 port@3 {
3816 reg = <3>;
3817 apss_funnel_in3: endpoint {
3818 remote-endpoint =
3819 <&etm3_out>;
3820 };
3821 };
3822
3823 port@4 {
3824 reg = <4>;
3825 apss_funnel_in4: endpoint {
3826 remote-endpoint =
3827 <&etm4_out>;
3828 };
3829 };
3830
3831 port@5 {
3832 reg = <5>;
3833 apss_funnel_in5: endpoint {
3834 remote-endpoint =
3835 <&etm5_out>;
3836 };
3837 };
3838
3839 port@6 {
3840 reg = <6>;
3841 apss_funnel_in6: endpoint {
3842 remote-endpoint =
3843 <&etm6_out>;
3844 };
3845 };
3846
3847 port@7 {
3848 reg = <7>;
3849 apss_funnel_in7: endpoint {
3850 remote-endpoint =
3851 <&etm7_out>;
3852 };
3853 };
3854 };
3855 };
3856
3857 funnel@7810000 {
3858 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3859 reg = <0 0x07810000 0 0x1000>;
3860
3861 clocks = <&aoss_qmp>;
3862 clock-names = "apb_pclk";
3863
3864 out-ports {
3865 port {
3866 apss_merge_funnel_out: endpoint {
3867 remote-endpoint =
3868 <&funnel2_in5>;
3869 };
3870 };
3871 };
3872
3873 in-ports {
3874 port {
3875 apss_merge_funnel_in: endpoint {
3876 remote-endpoint =
3877 <&apss_funnel_out>;
3878 };
3879 };
3880 };
3881 };
3882
3883 sdhc_2: mmc@8804000 {
3884 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3885 reg = <0 0x08804000 0 0x1000>;
3886
3887 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3888 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3889 interrupt-names = "hc_irq", "pwr_irq";
3890
3891 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3892 <&gcc GCC_SDCC2_APPS_CLK>,
3893 <&rpmhcc RPMH_CXO_CLK>;
3894 clock-names = "iface", "core", "xo";
3895 iommus = <&apps_smmu 0xa0 0xf>;
3896 power-domains = <&rpmhpd SDM845_CX>;
3897 operating-points-v2 = <&sdhc2_opp_table>;
3898
3899 status = "disabled";
3900
3901 sdhc2_opp_table: opp-table {
3902 compatible = "operating-points-v2";
3903
3904 opp-9600000 {
3905 opp-hz = /bits/ 64 <9600000>;
3906 required-opps = <&rpmhpd_opp_min_svs>;
3907 };
3908
3909 opp-19200000 {
3910 opp-hz = /bits/ 64 <19200000>;
3911 required-opps = <&rpmhpd_opp_low_svs>;
3912 };
3913
3914 opp-100000000 {
3915 opp-hz = /bits/ 64 <100000000>;
3916 required-opps = <&rpmhpd_opp_svs>;
3917 };
3918
3919 opp-201500000 {
3920 opp-hz = /bits/ 64 <201500000>;
3921 required-opps = <&rpmhpd_opp_svs_l1>;
3922 };
3923 };
3924 };
3925
3926 qspi: spi@88df000 {
3927 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3928 reg = <0 0x088df000 0 0x600>;
3929 iommus = <&apps_smmu 0x160 0x0>;
3930 #address-cells = <1>;
3931 #size-cells = <0>;
3932 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3933 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3934 <&gcc GCC_QSPI_CORE_CLK>;
3935 clock-names = "iface", "core";
3936 power-domains = <&rpmhpd SDM845_CX>;
3937 operating-points-v2 = <&qspi_opp_table>;
3938 status = "disabled";
3939 };
3940
3941 slim: slim-ngd@171c0000 {
3942 compatible = "qcom,slim-ngd-v2.1.0";
3943 reg = <0 0x171c0000 0 0x2c000>;
3944 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3945
3946 dmas = <&slimbam 3>, <&slimbam 4>;
3947 dma-names = "rx", "tx";
3948
3949 iommus = <&apps_smmu 0x1806 0x0>;
3950 #address-cells = <1>;
3951 #size-cells = <0>;
3952 status = "disabled";
3953 };
3954
3955 lmh_cluster1: lmh@17d70800 {
3956 compatible = "qcom,sdm845-lmh";
3957 reg = <0 0x17d70800 0 0x400>;
3958 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3959 cpus = <&CPU4>;
3960 qcom,lmh-temp-arm-millicelsius = <65000>;
3961 qcom,lmh-temp-low-millicelsius = <94500>;
3962 qcom,lmh-temp-high-millicelsius = <95000>;
3963 interrupt-controller;
3964 #interrupt-cells = <1>;
3965 };
3966
3967 lmh_cluster0: lmh@17d78800 {
3968 compatible = "qcom,sdm845-lmh";
3969 reg = <0 0x17d78800 0 0x400>;
3970 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3971 cpus = <&CPU0>;
3972 qcom,lmh-temp-arm-millicelsius = <65000>;
3973 qcom,lmh-temp-low-millicelsius = <94500>;
3974 qcom,lmh-temp-high-millicelsius = <95000>;
3975 interrupt-controller;
3976 #interrupt-cells = <1>;
3977 };
3978
3979 usb_1_hsphy: phy@88e2000 {
3980 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3981 reg = <0 0x088e2000 0 0x400>;
3982 status = "disabled";
3983 #phy-cells = <0>;
3984
3985 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3986 <&rpmhcc RPMH_CXO_CLK>;
3987 clock-names = "cfg_ahb", "ref";
3988
3989 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3990
3991 nvmem-cells = <&qusb2p_hstx_trim>;
3992 };
3993
3994 usb_2_hsphy: phy@88e3000 {
3995 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3996 reg = <0 0x088e3000 0 0x400>;
3997 status = "disabled";
3998 #phy-cells = <0>;
3999
4000 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4001 <&rpmhcc RPMH_CXO_CLK>;
4002 clock-names = "cfg_ahb", "ref";
4003
4004 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4005
4006 nvmem-cells = <&qusb2s_hstx_trim>;
4007 };
4008
4009 usb_1_qmpphy: phy@88e8000 {
4010 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
4011 reg = <0 0x088e8000 0 0x3000>;
4012 status = "disabled";
4013
4014 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
4015 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4016 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
4017 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
4018 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
4019 clock-names = "aux",
4020 "ref",
4021 "com_aux",
4022 "usb3_pipe",
4023 "cfg_ahb";
4024
4025 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
4026 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
4027 reset-names = "phy", "common";
4028
4029 #clock-cells = <1>;
4030 #phy-cells = <1>;
4031 };
4032
4033 usb_2_qmpphy: phy@88eb000 {
4034 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]4035 reg = <0 0x088eb000 0 0x1000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4036
4037 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4038 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4039 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]4040 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
4041 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
4042 clock-names = "aux",
4043 "cfg_ahb",
4044 "ref",
4045 "com_aux",
4046 "pipe";
4047 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4048 #clock-cells = <0>;
4049 #phy-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4050
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]4051 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
4052 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
4053 reset-names = "phy",
4054 "phy_phy";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4055
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]4056 status = "disabled";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4057 };
4058
4059 usb_1: usb@a6f8800 {
4060 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4061 reg = <0 0x0a6f8800 0 0x400>;
4062 status = "disabled";
4063 #address-cells = <2>;
4064 #size-cells = <2>;
4065 ranges;
4066 dma-ranges;
4067
4068 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4069 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4070 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4071 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4072 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4073 clock-names = "cfg_noc",
4074 "core",
4075 "iface",
4076 "sleep",
4077 "mock_utmi";
4078
4079 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4080 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4081 assigned-clock-rates = <19200000>, <150000000>;
4082
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]4083 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4084 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4085 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]4086 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]4087 <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>;
4088 interrupt-names = "pwr_event",
4089 "hs_phy_irq",
4090 "dp_hs_phy_irq",
4091 "dm_hs_phy_irq",
4092 "ss_phy_irq";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4093
4094 power-domains = <&gcc USB30_PRIM_GDSC>;
4095
4096 resets = <&gcc GCC_USB30_PRIM_BCR>;
4097
4098 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4099 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4100 interconnect-names = "usb-ddr", "apps-usb";
4101
4102 usb_1_dwc3: usb@a600000 {
4103 compatible = "snps,dwc3";
4104 reg = <0 0x0a600000 0 0xcd00>;
4105 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4106 iommus = <&apps_smmu 0x740 0>;
4107 snps,dis_u2_susphy_quirk;
4108 snps,dis_enblslpm_quirk;
4109 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4110 phy-names = "usb2-phy", "usb3-phy";
4111 };
4112 };
4113
4114 usb_2: usb@a8f8800 {
4115 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4116 reg = <0 0x0a8f8800 0 0x400>;
4117 status = "disabled";
4118 #address-cells = <2>;
4119 #size-cells = <2>;
4120 ranges;
4121 dma-ranges;
4122
4123 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4124 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4125 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4126 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4127 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4128 clock-names = "cfg_noc",
4129 "core",
4130 "iface",
4131 "sleep",
4132 "mock_utmi";
4133
4134 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4135 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4136 assigned-clock-rates = <19200000>, <150000000>;
4137
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]4138 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4139 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4140 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]4141 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]4142 <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>;
4143 interrupt-names = "pwr_event",
4144 "hs_phy_irq",
4145 "dp_hs_phy_irq",
4146 "dm_hs_phy_irq",
4147 "ss_phy_irq";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4148
4149 power-domains = <&gcc USB30_SEC_GDSC>;
4150
4151 resets = <&gcc GCC_USB30_SEC_BCR>;
4152
4153 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4154 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4155 interconnect-names = "usb-ddr", "apps-usb";
4156
4157 usb_2_dwc3: usb@a800000 {
4158 compatible = "snps,dwc3";
4159 reg = <0 0x0a800000 0 0xcd00>;
4160 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4161 iommus = <&apps_smmu 0x760 0>;
4162 snps,dis_u2_susphy_quirk;
4163 snps,dis_enblslpm_quirk;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]4164 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4165 phy-names = "usb2-phy", "usb3-phy";
4166 };
4167 };
4168
4169 venus: video-codec@aa00000 {
4170 compatible = "qcom,sdm845-venus-v2";
4171 reg = <0 0x0aa00000 0 0xff000>;
4172 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4173 power-domains = <&videocc VENUS_GDSC>,
4174 <&videocc VCODEC0_GDSC>,
4175 <&videocc VCODEC1_GDSC>,
4176 <&rpmhpd SDM845_CX>;
4177 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4178 operating-points-v2 = <&venus_opp_table>;
4179 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4180 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4181 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4182 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4183 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4184 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4185 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4186 clock-names = "core", "iface", "bus",
4187 "vcodec0_core", "vcodec0_bus",
4188 "vcodec1_core", "vcodec1_bus";
4189 iommus = <&apps_smmu 0x10a0 0x8>,
4190 <&apps_smmu 0x10b0 0x0>;
4191 memory-region = <&venus_mem>;
4192 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4193 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4194 interconnect-names = "video-mem", "cpu-cfg";
4195
4196 status = "disabled";
4197
4198 video-core0 {
4199 compatible = "venus-decoder";
4200 };
4201
4202 video-core1 {
4203 compatible = "venus-encoder";
4204 };
4205
4206 venus_opp_table: opp-table {
4207 compatible = "operating-points-v2";
4208
4209 opp-100000000 {
4210 opp-hz = /bits/ 64 <100000000>;
4211 required-opps = <&rpmhpd_opp_min_svs>;
4212 };
4213
4214 opp-200000000 {
4215 opp-hz = /bits/ 64 <200000000>;
4216 required-opps = <&rpmhpd_opp_low_svs>;
4217 };
4218
4219 opp-320000000 {
4220 opp-hz = /bits/ 64 <320000000>;
4221 required-opps = <&rpmhpd_opp_svs>;
4222 };
4223
4224 opp-380000000 {
4225 opp-hz = /bits/ 64 <380000000>;
4226 required-opps = <&rpmhpd_opp_svs_l1>;
4227 };
4228
4229 opp-444000000 {
4230 opp-hz = /bits/ 64 <444000000>;
4231 required-opps = <&rpmhpd_opp_nom>;
4232 };
4233
4234 opp-533000097 {
4235 opp-hz = /bits/ 64 <533000097>;
4236 required-opps = <&rpmhpd_opp_turbo>;
4237 };
4238 };
4239 };
4240
4241 videocc: clock-controller@ab00000 {
4242 compatible = "qcom,sdm845-videocc";
4243 reg = <0 0x0ab00000 0 0x10000>;
4244 clocks = <&rpmhcc RPMH_CXO_CLK>;
4245 clock-names = "bi_tcxo";
4246 #clock-cells = <1>;
4247 #power-domain-cells = <1>;
4248 #reset-cells = <1>;
4249 };
4250
4251 camss: camss@acb3000 {
4252 compatible = "qcom,sdm845-camss";
4253
4254 reg = <0 0x0acb3000 0 0x1000>,
4255 <0 0x0acba000 0 0x1000>,
4256 <0 0x0acc8000 0 0x1000>,
4257 <0 0x0ac65000 0 0x1000>,
4258 <0 0x0ac66000 0 0x1000>,
4259 <0 0x0ac67000 0 0x1000>,
4260 <0 0x0ac68000 0 0x1000>,
4261 <0 0x0acaf000 0 0x4000>,
4262 <0 0x0acb6000 0 0x4000>,
4263 <0 0x0acc4000 0 0x4000>;
4264 reg-names = "csid0",
4265 "csid1",
4266 "csid2",
4267 "csiphy0",
4268 "csiphy1",
4269 "csiphy2",
4270 "csiphy3",
4271 "vfe0",
4272 "vfe1",
4273 "vfe_lite";
4274
4275 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4285 interrupt-names = "csid0",
4286 "csid1",
4287 "csid2",
4288 "csiphy0",
4289 "csiphy1",
4290 "csiphy2",
4291 "csiphy3",
4292 "vfe0",
4293 "vfe1",
4294 "vfe_lite";
4295
4296 power-domains = <&clock_camcc IFE_0_GDSC>,
4297 <&clock_camcc IFE_1_GDSC>,
4298 <&clock_camcc TITAN_TOP_GDSC>;
4299
4300 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4301 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4302 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4303 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4304 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4305 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4306 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4307 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4308 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4309 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4310 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4311 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4312 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4313 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4314 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4315 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4316 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4317 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4318 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4319 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4320 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4321 <&gcc GCC_CAMERA_AHB_CLK>,
4322 <&gcc GCC_CAMERA_AXI_CLK>,
4323 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4324 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4325 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4326 <&clock_camcc CAM_CC_IFE_0_CLK>,
4327 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4328 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4329 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4330 <&clock_camcc CAM_CC_IFE_1_CLK>,
4331 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4332 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4333 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4334 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4335 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4336 clock-names = "camnoc_axi",
4337 "cpas_ahb",
4338 "cphy_rx_src",
4339 "csi0",
4340 "csi0_src",
4341 "csi1",
4342 "csi1_src",
4343 "csi2",
4344 "csi2_src",
4345 "csiphy0",
4346 "csiphy0_timer",
4347 "csiphy0_timer_src",
4348 "csiphy1",
4349 "csiphy1_timer",
4350 "csiphy1_timer_src",
4351 "csiphy2",
4352 "csiphy2_timer",
4353 "csiphy2_timer_src",
4354 "csiphy3",
4355 "csiphy3_timer",
4356 "csiphy3_timer_src",
4357 "gcc_camera_ahb",
4358 "gcc_camera_axi",
4359 "slow_ahb_src",
4360 "soc_ahb",
4361 "vfe0_axi",
4362 "vfe0",
4363 "vfe0_cphy_rx",
4364 "vfe0_src",
4365 "vfe1_axi",
4366 "vfe1",
4367 "vfe1_cphy_rx",
4368 "vfe1_src",
4369 "vfe_lite",
4370 "vfe_lite_cphy_rx",
4371 "vfe_lite_src";
4372
4373 iommus = <&apps_smmu 0x0808 0x0>,
4374 <&apps_smmu 0x0810 0x8>,
4375 <&apps_smmu 0x0c08 0x0>,
4376 <&apps_smmu 0x0c10 0x8>;
4377
4378 status = "disabled";
4379
4380 ports {
4381 #address-cells = <1>;
4382 #size-cells = <0>;
4383
4384 port@0 {
4385 reg = <0>;
4386 };
4387
4388 port@1 {
4389 reg = <1>;
4390 };
4391
4392 port@2 {
4393 reg = <2>;
4394 };
4395
4396 port@3 {
4397 reg = <3>;
4398 };
4399 };
4400 };
4401
4402 cci: cci@ac4a000 {
4403 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4404 #address-cells = <1>;
4405 #size-cells = <0>;
4406
4407 reg = <0 0x0ac4a000 0 0x4000>;
4408 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4409 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4410
4411 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4412 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4413 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4414 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4415 <&clock_camcc CAM_CC_CCI_CLK>,
4416 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4417 clock-names = "camnoc_axi",
4418 "soc_ahb",
4419 "slow_ahb_src",
4420 "cpas_ahb",
4421 "cci",
4422 "cci_src";
4423
4424 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4425 <&clock_camcc CAM_CC_CCI_CLK>;
4426 assigned-clock-rates = <80000000>, <37500000>;
4427
4428 pinctrl-names = "default", "sleep";
4429 pinctrl-0 = <&cci0_default &cci1_default>;
4430 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4431
4432 status = "disabled";
4433
4434 cci_i2c0: i2c-bus@0 {
4435 reg = <0>;
4436 clock-frequency = <1000000>;
4437 #address-cells = <1>;
4438 #size-cells = <0>;
4439 };
4440
4441 cci_i2c1: i2c-bus@1 {
4442 reg = <1>;
4443 clock-frequency = <1000000>;
4444 #address-cells = <1>;
4445 #size-cells = <0>;
4446 };
4447 };
4448
4449 clock_camcc: clock-controller@ad00000 {
4450 compatible = "qcom,sdm845-camcc";
4451 reg = <0 0x0ad00000 0 0x10000>;
4452 #clock-cells = <1>;
4453 #reset-cells = <1>;
4454 #power-domain-cells = <1>;
4455 clocks = <&rpmhcc RPMH_CXO_CLK>;
4456 clock-names = "bi_tcxo";
4457 };
4458
4459 mdss: display-subsystem@ae00000 {
4460 compatible = "qcom,sdm845-mdss";
4461 reg = <0 0x0ae00000 0 0x1000>;
4462 reg-names = "mdss";
4463
4464 power-domains = <&dispcc MDSS_GDSC>;
4465
4466 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4467 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4468 clock-names = "iface", "core";
4469
4470 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4471 interrupt-controller;
4472 #interrupt-cells = <1>;
4473
4474 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4475 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4476 interconnect-names = "mdp0-mem", "mdp1-mem";
4477
4478 iommus = <&apps_smmu 0x880 0x8>,
4479 <&apps_smmu 0xc80 0x8>;
4480
4481 status = "disabled";
4482
4483 #address-cells = <2>;
4484 #size-cells = <2>;
4485 ranges;
4486
4487 mdss_mdp: display-controller@ae01000 {
4488 compatible = "qcom,sdm845-dpu";
4489 reg = <0 0x0ae01000 0 0x8f000>,
4490 <0 0x0aeb0000 0 0x2008>;
4491 reg-names = "mdp", "vbif";
4492
4493 clocks = <&gcc GCC_DISP_AXI_CLK>,
4494 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4495 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4496 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4497 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4498 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4499
4500 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4501 assigned-clock-rates = <19200000>;
4502 operating-points-v2 = <&mdp_opp_table>;
4503 power-domains = <&rpmhpd SDM845_CX>;
4504
4505 interrupt-parent = <&mdss>;
4506 interrupts = <0>;
4507
4508 ports {
4509 #address-cells = <1>;
4510 #size-cells = <0>;
4511
4512 port@0 {
4513 reg = <0>;
4514 dpu_intf0_out: endpoint {
4515 remote-endpoint = <&dp_in>;
4516 };
4517 };
4518
4519 port@1 {
4520 reg = <1>;
4521 dpu_intf1_out: endpoint {
4522 remote-endpoint = <&mdss_dsi0_in>;
4523 };
4524 };
4525
4526 port@2 {
4527 reg = <2>;
4528 dpu_intf2_out: endpoint {
4529 remote-endpoint = <&mdss_dsi1_in>;
4530 };
4531 };
4532 };
4533
4534 mdp_opp_table: opp-table {
4535 compatible = "operating-points-v2";
4536
4537 opp-19200000 {
4538 opp-hz = /bits/ 64 <19200000>;
4539 required-opps = <&rpmhpd_opp_min_svs>;
4540 };
4541
4542 opp-171428571 {
4543 opp-hz = /bits/ 64 <171428571>;
4544 required-opps = <&rpmhpd_opp_low_svs>;
4545 };
4546
4547 opp-344000000 {
4548 opp-hz = /bits/ 64 <344000000>;
4549 required-opps = <&rpmhpd_opp_svs_l1>;
4550 };
4551
4552 opp-430000000 {
4553 opp-hz = /bits/ 64 <430000000>;
4554 required-opps = <&rpmhpd_opp_nom>;
4555 };
4556 };
4557 };
4558
4559 mdss_dp: displayport-controller@ae90000 {
4560 status = "disabled";
4561 compatible = "qcom,sdm845-dp";
4562
4563 reg = <0 0x0ae90000 0 0x200>,
4564 <0 0x0ae90200 0 0x200>,
4565 <0 0x0ae90400 0 0x600>,
4566 <0 0x0ae90a00 0 0x600>,
4567 <0 0x0ae91000 0 0x600>;
4568
4569 interrupt-parent = <&mdss>;
4570 interrupts = <12>;
4571
4572 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4573 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4574 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4575 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4576 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4577 clock-names = "core_iface", "core_aux", "ctrl_link",
4578 "ctrl_link_iface", "stream_pixel";
4579 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4580 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4581 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4582 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4583 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4584 phy-names = "dp";
4585
4586 operating-points-v2 = <&dp_opp_table>;
4587 power-domains = <&rpmhpd SDM845_CX>;
4588
4589 ports {
4590 #address-cells = <1>;
4591 #size-cells = <0>;
4592 port@0 {
4593 reg = <0>;
4594 dp_in: endpoint {
4595 remote-endpoint = <&dpu_intf0_out>;
4596 };
4597 };
4598
4599 port@1 {
4600 reg = <1>;
4601 dp_out: endpoint { };
4602 };
4603 };
4604
4605 dp_opp_table: opp-table {
4606 compatible = "operating-points-v2";
4607
4608 opp-162000000 {
4609 opp-hz = /bits/ 64 <162000000>;
4610 required-opps = <&rpmhpd_opp_low_svs>;
4611 };
4612
4613 opp-270000000 {
4614 opp-hz = /bits/ 64 <270000000>;
4615 required-opps = <&rpmhpd_opp_svs>;
4616 };
4617
4618 opp-540000000 {
4619 opp-hz = /bits/ 64 <540000000>;
4620 required-opps = <&rpmhpd_opp_svs_l1>;
4621 };
4622
4623 opp-810000000 {
4624 opp-hz = /bits/ 64 <810000000>;
4625 required-opps = <&rpmhpd_opp_nom>;
4626 };
4627 };
4628 };
4629
4630 mdss_dsi0: dsi@ae94000 {
4631 compatible = "qcom,sdm845-dsi-ctrl",
4632 "qcom,mdss-dsi-ctrl";
4633 reg = <0 0x0ae94000 0 0x400>;
4634 reg-names = "dsi_ctrl";
4635
4636 interrupt-parent = <&mdss>;
4637 interrupts = <4>;
4638
4639 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4640 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4641 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4642 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4643 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4644 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4645 clock-names = "byte",
4646 "byte_intf",
4647 "pixel",
4648 "core",
4649 "iface",
4650 "bus";
4651 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4652 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4653
4654 operating-points-v2 = <&dsi_opp_table>;
4655 power-domains = <&rpmhpd SDM845_CX>;
4656
4657 phys = <&mdss_dsi0_phy>;
4658
4659 status = "disabled";
4660
4661 #address-cells = <1>;
4662 #size-cells = <0>;
4663
4664 ports {
4665 #address-cells = <1>;
4666 #size-cells = <0>;
4667
4668 port@0 {
4669 reg = <0>;
4670 mdss_dsi0_in: endpoint {
4671 remote-endpoint = <&dpu_intf1_out>;
4672 };
4673 };
4674
4675 port@1 {
4676 reg = <1>;
4677 mdss_dsi0_out: endpoint {
4678 };
4679 };
4680 };
4681 };
4682
4683 mdss_dsi0_phy: phy@ae94400 {
4684 compatible = "qcom,dsi-phy-10nm";
4685 reg = <0 0x0ae94400 0 0x200>,
4686 <0 0x0ae94600 0 0x280>,
4687 <0 0x0ae94a00 0 0x1e0>;
4688 reg-names = "dsi_phy",
4689 "dsi_phy_lane",
4690 "dsi_pll";
4691
4692 #clock-cells = <1>;
4693 #phy-cells = <0>;
4694
4695 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4696 <&rpmhcc RPMH_CXO_CLK>;
4697 clock-names = "iface", "ref";
4698
4699 status = "disabled";
4700 };
4701
4702 mdss_dsi1: dsi@ae96000 {
4703 compatible = "qcom,sdm845-dsi-ctrl",
4704 "qcom,mdss-dsi-ctrl";
4705 reg = <0 0x0ae96000 0 0x400>;
4706 reg-names = "dsi_ctrl";
4707
4708 interrupt-parent = <&mdss>;
4709 interrupts = <5>;
4710
4711 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4712 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4713 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4714 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4715 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4716 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4717 clock-names = "byte",
4718 "byte_intf",
4719 "pixel",
4720 "core",
4721 "iface",
4722 "bus";
4723 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4724 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4725
4726 operating-points-v2 = <&dsi_opp_table>;
4727 power-domains = <&rpmhpd SDM845_CX>;
4728
4729 phys = <&mdss_dsi1_phy>;
4730
4731 status = "disabled";
4732
4733 #address-cells = <1>;
4734 #size-cells = <0>;
4735
4736 ports {
4737 #address-cells = <1>;
4738 #size-cells = <0>;
4739
4740 port@0 {
4741 reg = <0>;
4742 mdss_dsi1_in: endpoint {
4743 remote-endpoint = <&dpu_intf2_out>;
4744 };
4745 };
4746
4747 port@1 {
4748 reg = <1>;
4749 mdss_dsi1_out: endpoint {
4750 };
4751 };
4752 };
4753 };
4754
4755 mdss_dsi1_phy: phy@ae96400 {
4756 compatible = "qcom,dsi-phy-10nm";
4757 reg = <0 0x0ae96400 0 0x200>,
4758 <0 0x0ae96600 0 0x280>,
4759 <0 0x0ae96a00 0 0x10e>;
4760 reg-names = "dsi_phy",
4761 "dsi_phy_lane",
4762 "dsi_pll";
4763
4764 #clock-cells = <1>;
4765 #phy-cells = <0>;
4766
4767 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4768 <&rpmhcc RPMH_CXO_CLK>;
4769 clock-names = "iface", "ref";
4770
4771 status = "disabled";
4772 };
4773 };
4774
4775 gpu: gpu@5000000 {
4776 compatible = "qcom,adreno-630.2", "qcom,adreno";
4777
4778 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4779 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4780
4781 /*
4782 * Look ma, no clocks! The GPU clocks and power are
4783 * controlled entirely by the GMU
4784 */
4785
4786 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4787
4788 iommus = <&adreno_smmu 0>;
4789
4790 operating-points-v2 = <&gpu_opp_table>;
4791
4792 qcom,gmu = <&gmu>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]4793 #cooling-cells = <2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4794
4795 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4796 interconnect-names = "gfx-mem";
4797
4798 status = "disabled";
4799
4800 gpu_opp_table: opp-table {
4801 compatible = "operating-points-v2";
4802
4803 opp-710000000 {
4804 opp-hz = /bits/ 64 <710000000>;
4805 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4806 opp-peak-kBps = <7216000>;
4807 };
4808
4809 opp-675000000 {
4810 opp-hz = /bits/ 64 <675000000>;
4811 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4812 opp-peak-kBps = <7216000>;
4813 };
4814
4815 opp-596000000 {
4816 opp-hz = /bits/ 64 <596000000>;
4817 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4818 opp-peak-kBps = <6220000>;
4819 };
4820
4821 opp-520000000 {
4822 opp-hz = /bits/ 64 <520000000>;
4823 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4824 opp-peak-kBps = <6220000>;
4825 };
4826
4827 opp-414000000 {
4828 opp-hz = /bits/ 64 <414000000>;
4829 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4830 opp-peak-kBps = <4068000>;
4831 };
4832
4833 opp-342000000 {
4834 opp-hz = /bits/ 64 <342000000>;
4835 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4836 opp-peak-kBps = <2724000>;
4837 };
4838
4839 opp-257000000 {
4840 opp-hz = /bits/ 64 <257000000>;
4841 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4842 opp-peak-kBps = <1648000>;
4843 };
4844 };
4845 };
4846
4847 adreno_smmu: iommu@5040000 {
4848 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4849 reg = <0 0x05040000 0 0x10000>;
4850 #iommu-cells = <1>;
4851 #global-interrupts = <2>;
4852 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4853 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4854 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4855 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4856 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4857 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4858 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4859 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4860 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4861 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4862 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4863 <&gcc GCC_GPU_CFG_AHB_CLK>;
4864 clock-names = "bus", "iface";
4865
4866 power-domains = <&gpucc GPU_CX_GDSC>;
4867 };
4868
4869 gmu: gmu@506a000 {
4870 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4871
4872 reg = <0 0x0506a000 0 0x30000>,
4873 <0 0x0b280000 0 0x10000>,
4874 <0 0x0b480000 0 0x10000>;
4875 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4876
4877 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4878 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4879 interrupt-names = "hfi", "gmu";
4880
4881 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4882 <&gpucc GPU_CC_CXO_CLK>,
4883 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4884 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4885 clock-names = "gmu", "cxo", "axi", "memnoc";
4886
4887 power-domains = <&gpucc GPU_CX_GDSC>,
4888 <&gpucc GPU_GX_GDSC>;
4889 power-domain-names = "cx", "gx";
4890
4891 iommus = <&adreno_smmu 5>;
4892
4893 operating-points-v2 = <&gmu_opp_table>;
4894
4895 status = "disabled";
4896
4897 gmu_opp_table: opp-table {
4898 compatible = "operating-points-v2";
4899
4900 opp-400000000 {
4901 opp-hz = /bits/ 64 <400000000>;
4902 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4903 };
4904
4905 opp-200000000 {
4906 opp-hz = /bits/ 64 <200000000>;
4907 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4908 };
4909 };
4910 };
4911
4912 dispcc: clock-controller@af00000 {
4913 compatible = "qcom,sdm845-dispcc";
4914 reg = <0 0x0af00000 0 0x10000>;
4915 clocks = <&rpmhcc RPMH_CXO_CLK>,
4916 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4917 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4918 <&mdss_dsi0_phy 0>,
4919 <&mdss_dsi0_phy 1>,
4920 <&mdss_dsi1_phy 0>,
4921 <&mdss_dsi1_phy 1>,
4922 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4923 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4924 clock-names = "bi_tcxo",
4925 "gcc_disp_gpll0_clk_src",
4926 "gcc_disp_gpll0_div_clk_src",
4927 "dsi0_phy_pll_out_byteclk",
4928 "dsi0_phy_pll_out_dsiclk",
4929 "dsi1_phy_pll_out_byteclk",
4930 "dsi1_phy_pll_out_dsiclk",
4931 "dp_link_clk_divsel_ten",
4932 "dp_vco_divided_clk_src_mux";
4933 #clock-cells = <1>;
4934 #reset-cells = <1>;
4935 #power-domain-cells = <1>;
4936 };
4937
4938 pdc_intc: interrupt-controller@b220000 {
4939 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4940 reg = <0 0x0b220000 0 0x30000>;
4941 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4942 #interrupt-cells = <2>;
4943 interrupt-parent = <&intc>;
4944 interrupt-controller;
4945 };
4946
4947 pdc_reset: reset-controller@b2e0000 {
4948 compatible = "qcom,sdm845-pdc-global";
4949 reg = <0 0x0b2e0000 0 0x20000>;
4950 #reset-cells = <1>;
4951 };
4952
4953 tsens0: thermal-sensor@c263000 {
4954 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4955 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4956 <0 0x0c222000 0 0x1ff>; /* SROT */
4957 #qcom,sensors = <13>;
4958 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4959 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4960 interrupt-names = "uplow", "critical";
4961 #thermal-sensor-cells = <1>;
4962 };
4963
4964 tsens1: thermal-sensor@c265000 {
4965 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4966 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4967 <0 0x0c223000 0 0x1ff>; /* SROT */
4968 #qcom,sensors = <8>;
4969 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4970 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4971 interrupt-names = "uplow", "critical";
4972 #thermal-sensor-cells = <1>;
4973 };
4974
4975 aoss_reset: reset-controller@c2a0000 {
4976 compatible = "qcom,sdm845-aoss-cc";
4977 reg = <0 0x0c2a0000 0 0x31000>;
4978 #reset-cells = <1>;
4979 };
4980
4981 aoss_qmp: power-management@c300000 {
4982 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
4983 reg = <0 0x0c300000 0 0x400>;
4984 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4985 mboxes = <&apss_shared 0>;
4986
4987 #clock-cells = <0>;
4988
4989 cx_cdev: cx {
4990 #cooling-cells = <2>;
4991 };
4992
4993 ebi_cdev: ebi {
4994 #cooling-cells = <2>;
4995 };
4996 };
4997
4998 sram@c3f0000 {
4999 compatible = "qcom,sdm845-rpmh-stats";
5000 reg = <0 0x0c3f0000 0 0x400>;
5001 };
5002
5003 spmi_bus: spmi@c440000 {
5004 compatible = "qcom,spmi-pmic-arb";
5005 reg = <0 0x0c440000 0 0x1100>,
5006 <0 0x0c600000 0 0x2000000>,
5007 <0 0x0e600000 0 0x100000>,
5008 <0 0x0e700000 0 0xa0000>,
5009 <0 0x0c40a000 0 0x26000>;
5010 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5011 interrupt-names = "periph_irq";
5012 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5013 qcom,ee = <0>;
5014 qcom,channel = <0>;
5015 #address-cells = <2>;
5016 #size-cells = <0>;
5017 interrupt-controller;
5018 #interrupt-cells = <4>;
5019 };
5020
5021 sram@146bf000 {
5022 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5023 reg = <0 0x146bf000 0 0x1000>;
5024
5025 #address-cells = <1>;
5026 #size-cells = <1>;
5027
5028 ranges = <0 0 0x146bf000 0x1000>;
5029
5030 pil-reloc@94c {
5031 compatible = "qcom,pil-reloc-info";
5032 reg = <0x94c 0xc8>;
5033 };
5034 };
5035
5036 apps_smmu: iommu@15000000 {
5037 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5038 reg = <0 0x15000000 0 0x80000>;
5039 #iommu-cells = <2>;
5040 #global-interrupts = <1>;
5041 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5042 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5043 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5045 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5046 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5047 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5048 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5049 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5050 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5051 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5052 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5053 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5054 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5056 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5057 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5058 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5059 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5060 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5061 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5062 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5063 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5064 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5065 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5066 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5067 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5068 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5069 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5070 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5071 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5072 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5073 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5074 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5075 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5076 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5077 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5078 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5079 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5080 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5081 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5082 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5083 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5084 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5085 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5086 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5087 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5088 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5089 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5090 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5091 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5092 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5093 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5094 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5095 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5096 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5097 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5106 };
5107
5108 lpasscc: clock-controller@17014000 {
5109 compatible = "qcom,sdm845-lpasscc";
5110 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5111 reg-names = "cc", "qdsp6ss";
5112 #clock-cells = <1>;
5113 status = "disabled";
5114 };
5115
5116 gladiator_noc: interconnect@17900000 {
5117 compatible = "qcom,sdm845-gladiator-noc";
5118 reg = <0 0x17900000 0 0xd080>;
5119 #interconnect-cells = <2>;
5120 qcom,bcm-voters = <&apps_bcm_voter>;
5121 };
5122
5123 watchdog@17980000 {
5124 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5125 reg = <0 0x17980000 0 0x1000>;
5126 clocks = <&sleep_clk>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]5127 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]5128 };
5129
5130 apss_shared: mailbox@17990000 {
5131 compatible = "qcom,sdm845-apss-shared";
5132 reg = <0 0x17990000 0 0x1000>;
5133 #mbox-cells = <1>;
5134 };
5135
5136 apps_rsc: rsc@179c0000 {
5137 label = "apps_rsc";
5138 compatible = "qcom,rpmh-rsc";
5139 reg = <0 0x179c0000 0 0x10000>,
5140 <0 0x179d0000 0 0x10000>,
5141 <0 0x179e0000 0 0x10000>;
5142 reg-names = "drv-0", "drv-1", "drv-2";
5143 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5146 qcom,tcs-offset = <0xd00>;
5147 qcom,drv-id = <2>;
5148 qcom,tcs-config = <ACTIVE_TCS 2>,
5149 <SLEEP_TCS 3>,
5150 <WAKE_TCS 3>,
5151 <CONTROL_TCS 1>;
5152 power-domains = <&CLUSTER_PD>;
5153
5154 apps_bcm_voter: bcm-voter {
5155 compatible = "qcom,bcm-voter";
5156 };
5157
5158 rpmhcc: clock-controller {
5159 compatible = "qcom,sdm845-rpmh-clk";
5160 #clock-cells = <1>;
5161 clock-names = "xo";
5162 clocks = <&xo_board>;
5163 };
5164
5165 rpmhpd: power-controller {
5166 compatible = "qcom,sdm845-rpmhpd";
5167 #power-domain-cells = <1>;
5168 operating-points-v2 = <&rpmhpd_opp_table>;
5169
5170 rpmhpd_opp_table: opp-table {
5171 compatible = "operating-points-v2";
5172
5173 rpmhpd_opp_ret: opp1 {
5174 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5175 };
5176
5177 rpmhpd_opp_min_svs: opp2 {
5178 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5179 };
5180
5181 rpmhpd_opp_low_svs: opp3 {
5182 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5183 };
5184
5185 rpmhpd_opp_svs: opp4 {
5186 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5187 };
5188
5189 rpmhpd_opp_svs_l1: opp5 {
5190 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5191 };
5192
5193 rpmhpd_opp_nom: opp6 {
5194 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5195 };
5196
5197 rpmhpd_opp_nom_l1: opp7 {
5198 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5199 };
5200
5201 rpmhpd_opp_nom_l2: opp8 {
5202 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5203 };
5204
5205 rpmhpd_opp_turbo: opp9 {
5206 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5207 };
5208
5209 rpmhpd_opp_turbo_l1: opp10 {
5210 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5211 };
5212 };
5213 };
5214 };
5215
5216 intc: interrupt-controller@17a00000 {
5217 compatible = "arm,gic-v3";
5218 #address-cells = <2>;
5219 #size-cells = <2>;
5220 ranges;
5221 #interrupt-cells = <3>;
5222 interrupt-controller;
5223 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5224 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5225 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5226
5227 msi-controller@17a40000 {
5228 compatible = "arm,gic-v3-its";
5229 msi-controller;
5230 #msi-cells = <1>;
5231 reg = <0 0x17a40000 0 0x20000>;
5232 status = "disabled";
5233 };
5234 };
5235
5236 slimbam: dma-controller@17184000 {
5237 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5238 qcom,controlled-remotely;
5239 reg = <0 0x17184000 0 0x2a000>;
5240 num-channels = <31>;
5241 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5242 #dma-cells = <1>;
5243 qcom,ee = <1>;
5244 qcom,num-ees = <2>;
5245 iommus = <&apps_smmu 0x1806 0x0>;
5246 };
5247
5248 timer@17c90000 {
5249 #address-cells = <1>;
5250 #size-cells = <1>;
5251 ranges = <0 0 0 0x20000000>;
5252 compatible = "arm,armv7-timer-mem";
5253 reg = <0 0x17c90000 0 0x1000>;
5254
5255 frame@17ca0000 {
5256 frame-number = <0>;
5257 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5258 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5259 reg = <0x17ca0000 0x1000>,
5260 <0x17cb0000 0x1000>;
5261 };
5262
5263 frame@17cc0000 {
5264 frame-number = <1>;
5265 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5266 reg = <0x17cc0000 0x1000>;
5267 status = "disabled";
5268 };
5269
5270 frame@17cd0000 {
5271 frame-number = <2>;
5272 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5273 reg = <0x17cd0000 0x1000>;
5274 status = "disabled";
5275 };
5276
5277 frame@17ce0000 {
5278 frame-number = <3>;
5279 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5280 reg = <0x17ce0000 0x1000>;
5281 status = "disabled";
5282 };
5283
5284 frame@17cf0000 {
5285 frame-number = <4>;
5286 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5287 reg = <0x17cf0000 0x1000>;
5288 status = "disabled";
5289 };
5290
5291 frame@17d00000 {
5292 frame-number = <5>;
5293 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5294 reg = <0x17d00000 0x1000>;
5295 status = "disabled";
5296 };
5297
5298 frame@17d10000 {
5299 frame-number = <6>;
5300 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5301 reg = <0x17d10000 0x1000>;
5302 status = "disabled";
5303 };
5304 };
5305
5306 osm_l3: interconnect@17d41000 {
5307 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5308 reg = <0 0x17d41000 0 0x1400>;
5309
5310 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5311 clock-names = "xo", "alternate";
5312
5313 #interconnect-cells = <1>;
5314 };
5315
5316 cpufreq_hw: cpufreq@17d43000 {
5317 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5318 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5319 reg-names = "freq-domain0", "freq-domain1";
5320
5321 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5322
5323 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5324 clock-names = "xo", "alternate";
5325
5326 #freq-domain-cells = <1>;
5327 #clock-cells = <1>;
5328 };
5329
5330 wifi: wifi@18800000 {
5331 compatible = "qcom,wcn3990-wifi";
5332 status = "disabled";
5333 reg = <0 0x18800000 0 0x800000>;
5334 reg-names = "membase";
5335 memory-region = <&wlan_msa_mem>;
5336 clock-names = "cxo_ref_clk_pin";
5337 clocks = <&rpmhcc RPMH_RF_CLK2>;
5338 interrupts =
5339 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5340 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5341 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5342 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5343 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5344 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5345 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5346 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5347 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5348 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5349 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5350 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5351 iommus = <&apps_smmu 0x0040 0x1>;
5352 };
5353 };
5354
5355 sound: sound {
5356 };
5357
5358 thermal-zones {
5359 cpu0-thermal {
5360 polling-delay-passive = <250>;
5361 polling-delay = <1000>;
5362
5363 thermal-sensors = <&tsens0 1>;
5364
5365 trips {
5366 cpu0_alert0: trip-point0 {
5367 temperature = <90000>;
5368 hysteresis = <2000>;
5369 type = "passive";
5370 };
5371
5372 cpu0_alert1: trip-point1 {
5373 temperature = <95000>;
5374 hysteresis = <2000>;
5375 type = "passive";
5376 };
5377
5378 cpu0_crit: cpu-crit {
5379 temperature = <110000>;
5380 hysteresis = <1000>;
5381 type = "critical";
5382 };
5383 };
5384 };
5385
5386 cpu1-thermal {
5387 polling-delay-passive = <250>;
5388 polling-delay = <1000>;
5389
5390 thermal-sensors = <&tsens0 2>;
5391
5392 trips {
5393 cpu1_alert0: trip-point0 {
5394 temperature = <90000>;
5395 hysteresis = <2000>;
5396 type = "passive";
5397 };
5398
5399 cpu1_alert1: trip-point1 {
5400 temperature = <95000>;
5401 hysteresis = <2000>;
5402 type = "passive";
5403 };
5404
5405 cpu1_crit: cpu-crit {
5406 temperature = <110000>;
5407 hysteresis = <1000>;
5408 type = "critical";
5409 };
5410 };
5411 };
5412
5413 cpu2-thermal {
5414 polling-delay-passive = <250>;
5415 polling-delay = <1000>;
5416
5417 thermal-sensors = <&tsens0 3>;
5418
5419 trips {
5420 cpu2_alert0: trip-point0 {
5421 temperature = <90000>;
5422 hysteresis = <2000>;
5423 type = "passive";
5424 };
5425
5426 cpu2_alert1: trip-point1 {
5427 temperature = <95000>;
5428 hysteresis = <2000>;
5429 type = "passive";
5430 };
5431
5432 cpu2_crit: cpu-crit {
5433 temperature = <110000>;
5434 hysteresis = <1000>;
5435 type = "critical";
5436 };
5437 };
5438 };
5439
5440 cpu3-thermal {
5441 polling-delay-passive = <250>;
5442 polling-delay = <1000>;
5443
5444 thermal-sensors = <&tsens0 4>;
5445
5446 trips {
5447 cpu3_alert0: trip-point0 {
5448 temperature = <90000>;
5449 hysteresis = <2000>;
5450 type = "passive";
5451 };
5452
5453 cpu3_alert1: trip-point1 {
5454 temperature = <95000>;
5455 hysteresis = <2000>;
5456 type = "passive";
5457 };
5458
5459 cpu3_crit: cpu-crit {
5460 temperature = <110000>;
5461 hysteresis = <1000>;
5462 type = "critical";
5463 };
5464 };
5465 };
5466
5467 cpu4-thermal {
5468 polling-delay-passive = <250>;
5469 polling-delay = <1000>;
5470
5471 thermal-sensors = <&tsens0 7>;
5472
5473 trips {
5474 cpu4_alert0: trip-point0 {
5475 temperature = <90000>;
5476 hysteresis = <2000>;
5477 type = "passive";
5478 };
5479
5480 cpu4_alert1: trip-point1 {
5481 temperature = <95000>;
5482 hysteresis = <2000>;
5483 type = "passive";
5484 };
5485
5486 cpu4_crit: cpu-crit {
5487 temperature = <110000>;
5488 hysteresis = <1000>;
5489 type = "critical";
5490 };
5491 };
5492 };
5493
5494 cpu5-thermal {
5495 polling-delay-passive = <250>;
5496 polling-delay = <1000>;
5497
5498 thermal-sensors = <&tsens0 8>;
5499
5500 trips {
5501 cpu5_alert0: trip-point0 {
5502 temperature = <90000>;
5503 hysteresis = <2000>;
5504 type = "passive";
5505 };
5506
5507 cpu5_alert1: trip-point1 {
5508 temperature = <95000>;
5509 hysteresis = <2000>;
5510 type = "passive";
5511 };
5512
5513 cpu5_crit: cpu-crit {
5514 temperature = <110000>;
5515 hysteresis = <1000>;
5516 type = "critical";
5517 };
5518 };
5519 };
5520
5521 cpu6-thermal {
5522 polling-delay-passive = <250>;
5523 polling-delay = <1000>;
5524
5525 thermal-sensors = <&tsens0 9>;
5526
5527 trips {
5528 cpu6_alert0: trip-point0 {
5529 temperature = <90000>;
5530 hysteresis = <2000>;
5531 type = "passive";
5532 };
5533
5534 cpu6_alert1: trip-point1 {
5535 temperature = <95000>;
5536 hysteresis = <2000>;
5537 type = "passive";
5538 };
5539
5540 cpu6_crit: cpu-crit {
5541 temperature = <110000>;
5542 hysteresis = <1000>;
5543 type = "critical";
5544 };
5545 };
5546 };
5547
5548 cpu7-thermal {
5549 polling-delay-passive = <250>;
5550 polling-delay = <1000>;
5551
5552 thermal-sensors = <&tsens0 10>;
5553
5554 trips {
5555 cpu7_alert0: trip-point0 {
5556 temperature = <90000>;
5557 hysteresis = <2000>;
5558 type = "passive";
5559 };
5560
5561 cpu7_alert1: trip-point1 {
5562 temperature = <95000>;
5563 hysteresis = <2000>;
5564 type = "passive";
5565 };
5566
5567 cpu7_crit: cpu-crit {
5568 temperature = <110000>;
5569 hysteresis = <1000>;
5570 type = "critical";
5571 };
5572 };
5573 };
5574
5575 aoss0-thermal {
5576 polling-delay-passive = <250>;
5577 polling-delay = <1000>;
5578
5579 thermal-sensors = <&tsens0 0>;
5580
5581 trips {
5582 aoss0_alert0: trip-point0 {
5583 temperature = <90000>;
5584 hysteresis = <2000>;
5585 type = "hot";
5586 };
5587 };
5588 };
5589
5590 cluster0-thermal {
5591 polling-delay-passive = <250>;
5592 polling-delay = <1000>;
5593
5594 thermal-sensors = <&tsens0 5>;
5595
5596 trips {
5597 cluster0_alert0: trip-point0 {
5598 temperature = <90000>;
5599 hysteresis = <2000>;
5600 type = "hot";
5601 };
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]5602 cluster0_crit: cluster0-crit {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]5603 temperature = <110000>;
5604 hysteresis = <2000>;
5605 type = "critical";
5606 };
5607 };
5608 };
5609
5610 cluster1-thermal {
5611 polling-delay-passive = <250>;
5612 polling-delay = <1000>;
5613
5614 thermal-sensors = <&tsens0 6>;
5615
5616 trips {
5617 cluster1_alert0: trip-point0 {
5618 temperature = <90000>;
5619 hysteresis = <2000>;
5620 type = "hot";
5621 };
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]5622 cluster1_crit: cluster1-crit {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]5623 temperature = <110000>;
5624 hysteresis = <2000>;
5625 type = "critical";
5626 };
5627 };
5628 };
5629
5630 gpu-top-thermal {
5631 polling-delay-passive = <250>;
5632 polling-delay = <1000>;
5633
5634 thermal-sensors = <&tsens0 11>;
5635
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]5636 cooling-maps {
5637 map0 {
5638 trip = <&gpu_top_alert0>;
5639 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5640 };
5641 };
5642
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]5643 trips {
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]5644 gpu_top_alert0: trip-point0 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]5645 temperature = <90000>;
5646 hysteresis = <2000>;
5647 type = "hot";
5648 };
5649 };
5650 };
5651
5652 gpu-bottom-thermal {
5653 polling-delay-passive = <250>;
5654 polling-delay = <1000>;
5655
5656 thermal-sensors = <&tsens0 12>;
5657
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]5658 cooling-maps {
5659 map0 {
5660 trip = <&gpu_bottom_alert0>;
5661 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5662 };
5663 };
5664
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]5665 trips {
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]5666 gpu_bottom_alert0: trip-point0 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]5667 temperature = <90000>;
5668 hysteresis = <2000>;
5669 type = "hot";
5670 };
5671 };
5672 };
5673
5674 aoss1-thermal {
5675 polling-delay-passive = <250>;
5676 polling-delay = <1000>;
5677
5678 thermal-sensors = <&tsens1 0>;
5679
5680 trips {
5681 aoss1_alert0: trip-point0 {
5682 temperature = <90000>;
5683 hysteresis = <2000>;
5684 type = "hot";
5685 };
5686 };
5687 };
5688
5689 q6-modem-thermal {
5690 polling-delay-passive = <250>;
5691 polling-delay = <1000>;
5692
5693 thermal-sensors = <&tsens1 1>;
5694
5695 trips {
5696 q6_modem_alert0: trip-point0 {
5697 temperature = <90000>;
5698 hysteresis = <2000>;
5699 type = "hot";
5700 };
5701 };
5702 };
5703
5704 mem-thermal {
5705 polling-delay-passive = <250>;
5706 polling-delay = <1000>;
5707
5708 thermal-sensors = <&tsens1 2>;
5709
5710 trips {
5711 mem_alert0: trip-point0 {
5712 temperature = <90000>;
5713 hysteresis = <2000>;
5714 type = "hot";
5715 };
5716 };
5717 };
5718
5719 wlan-thermal {
5720 polling-delay-passive = <250>;
5721 polling-delay = <1000>;
5722
5723 thermal-sensors = <&tsens1 3>;
5724
5725 trips {
5726 wlan_alert0: trip-point0 {
5727 temperature = <90000>;
5728 hysteresis = <2000>;
5729 type = "hot";
5730 };
5731 };
5732 };
5733
5734 q6-hvx-thermal {
5735 polling-delay-passive = <250>;
5736 polling-delay = <1000>;
5737
5738 thermal-sensors = <&tsens1 4>;
5739
5740 trips {
5741 q6_hvx_alert0: trip-point0 {
5742 temperature = <90000>;
5743 hysteresis = <2000>;
5744 type = "hot";
5745 };
5746 };
5747 };
5748
5749 camera-thermal {
5750 polling-delay-passive = <250>;
5751 polling-delay = <1000>;
5752
5753 thermal-sensors = <&tsens1 5>;
5754
5755 trips {
5756 camera_alert0: trip-point0 {
5757 temperature = <90000>;
5758 hysteresis = <2000>;
5759 type = "hot";
5760 };
5761 };
5762 };
5763
5764 video-thermal {
5765 polling-delay-passive = <250>;
5766 polling-delay = <1000>;
5767
5768 thermal-sensors = <&tsens1 6>;
5769
5770 trips {
5771 video_alert0: trip-point0 {
5772 temperature = <90000>;
5773 hysteresis = <2000>;
5774 type = "hot";
5775 };
5776 };
5777 };
5778
5779 modem-thermal {
5780 polling-delay-passive = <250>;
5781 polling-delay = <1000>;
5782
5783 thermal-sensors = <&tsens1 7>;
5784
5785 trips {
5786 modem_alert0: trip-point0 {
5787 temperature = <90000>;
5788 hysteresis = <2000>;
5789 type = "hot";
5790 };
5791 };
5792 };
5793 };
5794
5795 timer {
5796 compatible = "arm,armv8-timer";
5797 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
5798 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
5799 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
5800 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
5801 };
5802};