Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /dts-v1/; |
| 3 | |
| 4 | #include <dt-bindings/input/input.h> |
| 5 | #include "tegra132.dtsi" |
| 6 | |
| 7 | / { |
| 8 | model = "NVIDIA Tegra132 Norrin"; |
| 9 | compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124"; |
| 10 | |
| 11 | aliases { |
Tom Rini | 762f85b | 2024-07-20 11:15:10 -0600 | [diff] [blame^] | 12 | rtc0 = &as3722; |
| 13 | rtc1 = &tegra_rtc; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 14 | serial0 = &uarta; |
| 15 | }; |
| 16 | |
| 17 | chosen { |
| 18 | stdout-path = "serial0:115200n8"; |
| 19 | }; |
| 20 | |
| 21 | memory@80000000 { |
| 22 | device_type = "memory"; |
| 23 | reg = <0x0 0x80000000 0x0 0x80000000>; |
| 24 | }; |
| 25 | |
| 26 | host1x@50000000 { |
| 27 | hdmi@54280000 { |
| 28 | status = "disabled"; |
| 29 | |
| 30 | vdd-supply = <&vdd_3v3_hdmi>; |
| 31 | pll-supply = <&vdd_hdmi_pll>; |
| 32 | hdmi-supply = <&vdd_5v0_hdmi>; |
| 33 | |
| 34 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 35 | nvidia,hpd-gpio = |
| 36 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; |
| 37 | }; |
| 38 | |
| 39 | sor@54540000 { |
| 40 | status = "okay"; |
| 41 | |
| 42 | avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; |
| 43 | vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>; |
| 44 | |
| 45 | nvidia,dpaux = <&dpaux>; |
| 46 | nvidia,panel = <&panel>; |
| 47 | }; |
| 48 | |
| 49 | dpaux: dpaux@545c0000 { |
| 50 | vdd-supply = <&vdd_3v3_panel>; |
| 51 | status = "okay"; |
| 52 | }; |
| 53 | }; |
| 54 | |
| 55 | gpu@57000000 { |
| 56 | status = "okay"; |
| 57 | |
| 58 | vdd-supply = <&vdd_gpu>; |
| 59 | }; |
| 60 | |
| 61 | pinmux@70000868 { |
| 62 | pinctrl-names = "default"; |
| 63 | pinctrl-0 = <&pinmux_default>; |
| 64 | |
| 65 | pinmux_default: pinmux { |
| 66 | dap_mclk1_pw4 { |
| 67 | nvidia,pins = "dap_mclk1_pw4"; |
| 68 | nvidia,function = "extperiph1"; |
| 69 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 70 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 71 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 72 | }; |
| 73 | dap2_din_pa4 { |
| 74 | nvidia,pins = "dap2_din_pa4"; |
| 75 | nvidia,function = "i2s1"; |
| 76 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 77 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 78 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 79 | }; |
| 80 | dap2_dout_pa5 { |
| 81 | nvidia,pins = "dap2_dout_pa5", |
| 82 | "dap2_fs_pa2", |
| 83 | "dap2_sclk_pa3"; |
| 84 | nvidia,function = "i2s1"; |
| 85 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 86 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 87 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 88 | }; |
| 89 | dap3_dout_pp2 { |
| 90 | nvidia,pins = "dap3_dout_pp2"; |
| 91 | nvidia,function = "i2s2"; |
| 92 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 93 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 94 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 95 | }; |
| 96 | dvfs_pwm_px0 { |
| 97 | nvidia,pins = "dvfs_pwm_px0", |
| 98 | "dvfs_clk_px2"; |
| 99 | nvidia,function = "cldvfs"; |
| 100 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 101 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 102 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 103 | }; |
| 104 | ulpi_clk_py0 { |
| 105 | nvidia,pins = "ulpi_clk_py0", |
| 106 | "ulpi_nxt_py2", |
| 107 | "ulpi_stp_py3"; |
| 108 | nvidia,function = "spi1"; |
| 109 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 110 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 111 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 112 | }; |
| 113 | ulpi_dir_py1 { |
| 114 | nvidia,pins = "ulpi_dir_py1"; |
| 115 | nvidia,function = "spi1"; |
| 116 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 117 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 118 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 119 | }; |
| 120 | cam_i2c_scl_pbb1 { |
| 121 | nvidia,pins = "cam_i2c_scl_pbb1", |
| 122 | "cam_i2c_sda_pbb2"; |
| 123 | nvidia,function = "i2c3"; |
| 124 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 125 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 126 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 127 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 128 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 129 | }; |
| 130 | gen2_i2c_scl_pt5 { |
| 131 | nvidia,pins = "gen2_i2c_scl_pt5", |
| 132 | "gen2_i2c_sda_pt6"; |
| 133 | nvidia,function = "i2c2"; |
| 134 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 135 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 136 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 137 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 138 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 139 | }; |
| 140 | pj7 { |
| 141 | nvidia,pins = "pj7"; |
| 142 | nvidia,function = "uartd"; |
| 143 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 144 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 145 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 146 | }; |
| 147 | spdif_in_pk6 { |
| 148 | nvidia,pins = "spdif_in_pk6"; |
| 149 | nvidia,function = "spdif"; |
| 150 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 151 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 152 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 153 | }; |
| 154 | pk7 { |
| 155 | nvidia,pins = "pk7"; |
| 156 | nvidia,function = "uartd"; |
| 157 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 158 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 159 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 160 | }; |
| 161 | pg4 { |
| 162 | nvidia,pins = "pg4", |
| 163 | "pg5", |
| 164 | "pg6", |
| 165 | "pi3"; |
| 166 | nvidia,function = "spi4"; |
| 167 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 169 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 170 | }; |
| 171 | pg7 { |
| 172 | nvidia,pins = "pg7"; |
| 173 | nvidia,function = "spi4"; |
| 174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 175 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 176 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 177 | }; |
| 178 | ph1 { |
| 179 | nvidia,pins = "ph1"; |
| 180 | nvidia,function = "pwm1"; |
| 181 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 182 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 183 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 184 | }; |
| 185 | pk0 { |
| 186 | nvidia,pins = "pk0", |
| 187 | "kb_row15_ps7", |
| 188 | "clk_32k_out_pa0"; |
| 189 | nvidia,function = "soc"; |
| 190 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 191 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 192 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 193 | }; |
| 194 | sdmmc1_clk_pz0 { |
| 195 | nvidia,pins = "sdmmc1_clk_pz0"; |
| 196 | nvidia,function = "sdmmc1"; |
| 197 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 198 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 199 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 200 | }; |
| 201 | sdmmc1_cmd_pz1 { |
| 202 | nvidia,pins = "sdmmc1_cmd_pz1", |
| 203 | "sdmmc1_dat0_py7", |
| 204 | "sdmmc1_dat1_py6", |
| 205 | "sdmmc1_dat2_py5", |
| 206 | "sdmmc1_dat3_py4"; |
| 207 | nvidia,function = "sdmmc1"; |
| 208 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 209 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 210 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 211 | }; |
| 212 | sdmmc3_clk_pa6 { |
| 213 | nvidia,pins = "sdmmc3_clk_pa6"; |
| 214 | nvidia,function = "sdmmc3"; |
| 215 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 216 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 217 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 218 | }; |
| 219 | sdmmc3_cmd_pa7 { |
| 220 | nvidia,pins = "sdmmc3_cmd_pa7", |
| 221 | "sdmmc3_dat0_pb7", |
| 222 | "sdmmc3_dat1_pb6", |
| 223 | "sdmmc3_dat2_pb5", |
| 224 | "sdmmc3_dat3_pb4", |
| 225 | "kb_col4_pq4", |
| 226 | "sdmmc3_clk_lb_out_pee4", |
| 227 | "sdmmc3_clk_lb_in_pee5", |
| 228 | "sdmmc3_cd_n_pv2"; |
| 229 | nvidia,function = "sdmmc3"; |
| 230 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 231 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 232 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 233 | }; |
| 234 | sdmmc4_clk_pcc4 { |
| 235 | nvidia,pins = "sdmmc4_clk_pcc4"; |
| 236 | nvidia,function = "sdmmc4"; |
| 237 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 238 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 239 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 240 | }; |
| 241 | sdmmc4_cmd_pt7 { |
| 242 | nvidia,pins = "sdmmc4_cmd_pt7", |
| 243 | "sdmmc4_dat0_paa0", |
| 244 | "sdmmc4_dat1_paa1", |
| 245 | "sdmmc4_dat2_paa2", |
| 246 | "sdmmc4_dat3_paa3", |
| 247 | "sdmmc4_dat4_paa4", |
| 248 | "sdmmc4_dat5_paa5", |
| 249 | "sdmmc4_dat6_paa6", |
| 250 | "sdmmc4_dat7_paa7"; |
| 251 | nvidia,function = "sdmmc4"; |
| 252 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 253 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 254 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 255 | }; |
| 256 | mic_det_l { |
| 257 | nvidia,pins = "kb_row7_pr7"; |
| 258 | nvidia,function = "rsvd2"; |
| 259 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 260 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 261 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 262 | }; |
| 263 | kb_row10_ps2 { |
| 264 | nvidia,pins = "kb_row10_ps2"; |
| 265 | nvidia,function = "uarta"; |
| 266 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 267 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 268 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 269 | }; |
| 270 | kb_row9_ps1 { |
| 271 | nvidia,pins = "kb_row9_ps1"; |
| 272 | nvidia,function = "uarta"; |
| 273 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 274 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 275 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 276 | }; |
| 277 | pwr_i2c_scl_pz6 { |
| 278 | nvidia,pins = "pwr_i2c_scl_pz6", |
| 279 | "pwr_i2c_sda_pz7"; |
| 280 | nvidia,function = "i2cpwr"; |
| 281 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 282 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 283 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 284 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 285 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 286 | }; |
| 287 | jtag_rtck { |
| 288 | nvidia,pins = "jtag_rtck"; |
| 289 | nvidia,function = "rtck"; |
| 290 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 291 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 292 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 293 | }; |
| 294 | clk_32k_in { |
| 295 | nvidia,pins = "clk_32k_in"; |
| 296 | nvidia,function = "clk"; |
| 297 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 298 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 299 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 300 | }; |
| 301 | core_pwr_req { |
| 302 | nvidia,pins = "core_pwr_req"; |
| 303 | nvidia,function = "pwron"; |
| 304 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 305 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 306 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 307 | }; |
| 308 | cpu_pwr_req { |
| 309 | nvidia,pins = "cpu_pwr_req"; |
| 310 | nvidia,function = "cpu"; |
| 311 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 312 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 313 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 314 | }; |
| 315 | kb_col0_ap { |
| 316 | nvidia,pins = "kb_col0_pq0"; |
| 317 | nvidia,function = "rsvd4"; |
| 318 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 319 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 320 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 321 | }; |
| 322 | en_vdd_sd { |
| 323 | nvidia,pins = "kb_row0_pr0"; |
| 324 | nvidia,function = "rsvd4"; |
| 325 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 326 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 327 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 328 | }; |
| 329 | lid_open { |
| 330 | nvidia,pins = "kb_row4_pr4"; |
| 331 | nvidia,function = "rsvd3"; |
| 332 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 333 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 334 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 335 | }; |
| 336 | pwr_int_n { |
| 337 | nvidia,pins = "pwr_int_n"; |
| 338 | nvidia,function = "pmi"; |
| 339 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 340 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 341 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 342 | }; |
| 343 | reset_out_n { |
| 344 | nvidia,pins = "reset_out_n"; |
| 345 | nvidia,function = "reset_out_n"; |
| 346 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 347 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 348 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 349 | }; |
| 350 | clk3_out_pee0 { |
| 351 | nvidia,pins = "clk3_out_pee0"; |
| 352 | nvidia,function = "extperiph3"; |
| 353 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 354 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 355 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 356 | }; |
| 357 | gen1_i2c_scl_pc4 { |
| 358 | nvidia,pins = "gen1_i2c_scl_pc4", |
| 359 | "gen1_i2c_sda_pc5"; |
| 360 | nvidia,function = "i2c1"; |
| 361 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 362 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 363 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 364 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 365 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 366 | }; |
| 367 | hdmi_cec_pee3 { |
| 368 | nvidia,pins = "hdmi_cec_pee3"; |
| 369 | nvidia,function = "cec"; |
| 370 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 371 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 372 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 373 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 374 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 375 | }; |
| 376 | hdmi_int_pn7 { |
| 377 | nvidia,pins = "hdmi_int_pn7"; |
| 378 | nvidia,function = "rsvd1"; |
| 379 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 380 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 381 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 382 | }; |
| 383 | ddc_scl_pv4 { |
| 384 | nvidia,pins = "ddc_scl_pv4", |
| 385 | "ddc_sda_pv5"; |
| 386 | nvidia,function = "i2c4"; |
| 387 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 388 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 389 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 390 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 391 | nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; |
| 392 | }; |
| 393 | usb_vbus_en0_pn4 { |
| 394 | nvidia,pins = "usb_vbus_en0_pn4", |
| 395 | "usb_vbus_en1_pn5", |
| 396 | "usb_vbus_en2_pff1"; |
| 397 | nvidia,function = "usb"; |
| 398 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 399 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 400 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 401 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 402 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 403 | }; |
| 404 | drive_sdio1 { |
| 405 | nvidia,pins = "drive_sdio1"; |
| 406 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| 407 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 408 | nvidia,pull-down-strength = <36>; |
| 409 | nvidia,pull-up-strength = <20>; |
| 410 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; |
| 411 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; |
| 412 | }; |
| 413 | drive_sdio3 { |
| 414 | nvidia,pins = "drive_sdio3"; |
| 415 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| 416 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 417 | nvidia,pull-down-strength = <22>; |
| 418 | nvidia,pull-up-strength = <36>; |
| 419 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 420 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 421 | }; |
| 422 | drive_gma { |
| 423 | nvidia,pins = "drive_gma"; |
| 424 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| 425 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 426 | nvidia,pull-down-strength = <2>; |
| 427 | nvidia,pull-up-strength = <1>; |
| 428 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 429 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 430 | nvidia,drive-type = <1>; |
| 431 | }; |
| 432 | ac_ok { |
| 433 | nvidia,pins = "pj0"; |
| 434 | nvidia,function = "gmi"; |
| 435 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 436 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 437 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 438 | }; |
| 439 | codec_irq_l { |
| 440 | nvidia,pins = "ph4"; |
| 441 | nvidia,function = "gmi"; |
| 442 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 443 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 444 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 445 | }; |
| 446 | lcd_bl_en { |
| 447 | nvidia,pins = "ph2"; |
| 448 | nvidia,function = "gmi"; |
| 449 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 450 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 451 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 452 | }; |
| 453 | touch_irq_l { |
| 454 | nvidia,pins = "gpio_w3_aud_pw3"; |
| 455 | nvidia,function = "spi6"; |
| 456 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 457 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 458 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 459 | }; |
| 460 | tpm_davint_l { |
| 461 | nvidia,pins = "ph6"; |
| 462 | nvidia,function = "gmi"; |
| 463 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 464 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 465 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 466 | }; |
| 467 | ts_irq_l { |
| 468 | nvidia,pins = "pk2"; |
| 469 | nvidia,function = "gmi"; |
| 470 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 471 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 472 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 473 | }; |
| 474 | ts_reset_l { |
| 475 | nvidia,pins = "pk4"; |
| 476 | nvidia,function = "gmi"; |
| 477 | nvidia,pull = <1>; |
| 478 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 479 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 480 | }; |
| 481 | ts_shdn_l { |
| 482 | nvidia,pins = "pk1"; |
| 483 | nvidia,function = "gmi"; |
| 484 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 485 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 486 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 487 | }; |
| 488 | ph7 { |
| 489 | nvidia,pins = "ph7"; |
| 490 | nvidia,function = "gmi"; |
| 491 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 492 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 493 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 494 | }; |
| 495 | sensor_irq_l { |
| 496 | nvidia,pins = "pi6"; |
| 497 | nvidia,function = "gmi"; |
| 498 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 499 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 500 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 501 | }; |
| 502 | wifi_en { |
| 503 | nvidia,pins = "gpio_x7_aud_px7"; |
| 504 | nvidia,function = "rsvd4"; |
| 505 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 506 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 507 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 508 | }; |
| 509 | chromeos_write_protect { |
| 510 | nvidia,pins = "kb_row1_pr1"; |
| 511 | nvidia,function = "rsvd4"; |
| 512 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 513 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 514 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 515 | }; |
| 516 | hp_det_l { |
| 517 | nvidia,pins = "pi7"; |
| 518 | nvidia,function = "rsvd1"; |
| 519 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 520 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 521 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 522 | }; |
| 523 | soc_warm_reset_l { |
| 524 | nvidia,pins = "pi5"; |
| 525 | nvidia,function = "gmi"; |
| 526 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 527 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 528 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 529 | }; |
| 530 | }; |
| 531 | }; |
| 532 | |
| 533 | serial@70006000 { |
| 534 | /delete-property/ dmas; |
| 535 | /delete-property/ dma-names; |
| 536 | status = "okay"; |
| 537 | }; |
| 538 | |
| 539 | pwm: pwm@7000a000 { |
| 540 | status = "okay"; |
| 541 | }; |
| 542 | |
| 543 | /* HDMI DDC */ |
| 544 | hdmi_ddc: i2c@7000c700 { |
| 545 | status = "okay"; |
| 546 | clock-frequency = <100000>; |
| 547 | }; |
| 548 | |
| 549 | i2c@7000d000 { |
| 550 | status = "okay"; |
| 551 | clock-frequency = <400000>; |
| 552 | |
| 553 | as3722: pmic@40 { |
| 554 | compatible = "ams,as3722"; |
| 555 | reg = <0x40>; |
| 556 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 557 | |
| 558 | ams,system-power-controller; |
| 559 | |
| 560 | #interrupt-cells = <2>; |
| 561 | interrupt-controller; |
| 562 | |
| 563 | #gpio-cells = <2>; |
| 564 | gpio-controller; |
| 565 | |
| 566 | pinctrl-names = "default"; |
| 567 | pinctrl-0 = <&as3722_default>; |
| 568 | |
| 569 | as3722_default: pinmux { |
| 570 | gpio0 { |
| 571 | pins = "gpio0"; |
| 572 | function = "gpio"; |
| 573 | bias-pull-down; |
| 574 | }; |
| 575 | |
| 576 | gpio1 { |
| 577 | pins = "gpio1"; |
| 578 | function = "gpio"; |
| 579 | bias-pull-up; |
| 580 | }; |
| 581 | |
| 582 | gpio2_4_7 { |
| 583 | pins = "gpio2", "gpio4", "gpio7"; |
| 584 | function = "gpio"; |
| 585 | bias-pull-up; |
| 586 | }; |
| 587 | |
| 588 | gpio3 { |
| 589 | pins = "gpio3"; |
| 590 | function = "gpio"; |
| 591 | bias-high-impedance; |
| 592 | }; |
| 593 | |
| 594 | gpio5 { |
| 595 | pins = "gpio5"; |
| 596 | function = "clk32k-out"; |
| 597 | bias-pull-down; |
| 598 | }; |
| 599 | |
| 600 | gpio6 { |
| 601 | pins = "gpio6"; |
| 602 | function = "clk32k-out"; |
| 603 | bias-pull-down; |
| 604 | }; |
| 605 | }; |
| 606 | |
| 607 | regulators { |
| 608 | vsup-sd2-supply = <&vdd_5v0_sys>; |
| 609 | vsup-sd3-supply = <&vdd_5v0_sys>; |
| 610 | vsup-sd4-supply = <&vdd_5v0_sys>; |
| 611 | vsup-sd5-supply = <&vdd_5v0_sys>; |
| 612 | vin-ldo0-supply = <&vdd_1v35_lp0>; |
| 613 | vin-ldo1-6-supply = <&vdd_3v3_sys>; |
| 614 | vin-ldo2-5-7-supply = <&vddio_1v8>; |
| 615 | vin-ldo3-4-supply = <&vdd_3v3_sys>; |
| 616 | vin-ldo9-10-supply = <&vdd_5v0_sys>; |
| 617 | vin-ldo11-supply = <&vdd_3v3_run>; |
| 618 | |
| 619 | sd0 { |
| 620 | regulator-name = "+VDD_CPU_AP"; |
| 621 | regulator-min-microvolt = <700000>; |
| 622 | regulator-max-microvolt = <1350000>; |
| 623 | regulator-max-microamp = <3500000>; |
| 624 | regulator-always-on; |
| 625 | regulator-boot-on; |
| 626 | ams,ext-control = <2>; |
| 627 | }; |
| 628 | |
| 629 | sd1 { |
| 630 | regulator-name = "+VDD_CORE"; |
| 631 | regulator-min-microvolt = <700000>; |
| 632 | regulator-max-microvolt = <1350000>; |
| 633 | regulator-max-microamp = <4000000>; |
| 634 | regulator-always-on; |
| 635 | regulator-boot-on; |
| 636 | ams,ext-control = <1>; |
| 637 | }; |
| 638 | |
| 639 | vdd_1v35_lp0: sd2 { |
| 640 | regulator-name = "+1.35V_LP0(sd2)"; |
| 641 | regulator-min-microvolt = <1350000>; |
| 642 | regulator-max-microvolt = <1350000>; |
| 643 | regulator-always-on; |
| 644 | regulator-boot-on; |
| 645 | }; |
| 646 | |
| 647 | sd3 { |
| 648 | regulator-name = "+1.35V_LP0(sd3)"; |
| 649 | regulator-min-microvolt = <1350000>; |
| 650 | regulator-max-microvolt = <1350000>; |
| 651 | regulator-always-on; |
| 652 | regulator-boot-on; |
| 653 | }; |
| 654 | |
| 655 | vdd_1v05_run: sd4 { |
| 656 | regulator-name = "+1.05V_RUN"; |
| 657 | regulator-min-microvolt = <1050000>; |
| 658 | regulator-max-microvolt = <1050000>; |
| 659 | }; |
| 660 | |
| 661 | vddio_1v8: sd5 { |
| 662 | regulator-name = "+1.8V_VDDIO"; |
| 663 | regulator-min-microvolt = <1800000>; |
| 664 | regulator-max-microvolt = <1800000>; |
| 665 | regulator-always-on; |
| 666 | regulator-boot-on; |
| 667 | }; |
| 668 | |
| 669 | vdd_gpu: sd6 { |
| 670 | regulator-name = "+VDD_GPU_AP"; |
| 671 | regulator-min-microvolt = <800000>; |
| 672 | regulator-max-microvolt = <1200000>; |
| 673 | regulator-min-microamp = <3500000>; |
| 674 | regulator-max-microamp = <3500000>; |
| 675 | regulator-always-on; |
| 676 | regulator-boot-on; |
| 677 | }; |
| 678 | |
| 679 | avdd_1v05_run: ldo0 { |
| 680 | regulator-name = "+1.05_RUN_AVDD"; |
| 681 | regulator-min-microvolt = <1050000>; |
| 682 | regulator-max-microvolt = <1050000>; |
| 683 | regulator-always-on; |
| 684 | regulator-boot-on; |
| 685 | ams,ext-control = <1>; |
| 686 | }; |
| 687 | |
| 688 | ldo1 { |
| 689 | regulator-name = "+1.8V_RUN_CAM"; |
| 690 | regulator-min-microvolt = <1800000>; |
| 691 | regulator-max-microvolt = <1800000>; |
| 692 | }; |
| 693 | |
| 694 | ldo2 { |
| 695 | regulator-name = "+1.2V_GEN_AVDD"; |
| 696 | regulator-min-microvolt = <1200000>; |
| 697 | regulator-max-microvolt = <1200000>; |
| 698 | regulator-always-on; |
| 699 | regulator-boot-on; |
| 700 | }; |
| 701 | |
| 702 | ldo3 { |
| 703 | regulator-name = "+1.00V_LP0_VDD_RTC"; |
| 704 | regulator-min-microvolt = <1000000>; |
| 705 | regulator-max-microvolt = <1000000>; |
| 706 | regulator-always-on; |
| 707 | regulator-boot-on; |
| 708 | ams,enable-tracking; |
| 709 | }; |
| 710 | |
| 711 | vdd_run_cam: ldo4 { |
| 712 | regulator-name = "+2.8V_RUN_CAM"; |
| 713 | regulator-min-microvolt = <2800000>; |
| 714 | regulator-max-microvolt = <2800000>; |
| 715 | }; |
| 716 | |
| 717 | ldo5 { |
| 718 | regulator-name = "+1.2V_RUN_CAM_FRONT"; |
| 719 | regulator-min-microvolt = <1200000>; |
| 720 | regulator-max-microvolt = <1200000>; |
| 721 | }; |
| 722 | |
| 723 | vddio_sdmmc3: ldo6 { |
| 724 | regulator-name = "+VDDIO_SDMMC3"; |
| 725 | regulator-min-microvolt = <1800000>; |
| 726 | regulator-max-microvolt = <3300000>; |
| 727 | }; |
| 728 | |
| 729 | ldo7 { |
| 730 | regulator-name = "+1.05V_RUN_CAM_REAR"; |
| 731 | regulator-min-microvolt = <1050000>; |
| 732 | regulator-max-microvolt = <1050000>; |
| 733 | }; |
| 734 | |
| 735 | ldo9 { |
| 736 | regulator-name = "+2.8V_RUN_TOUCH"; |
| 737 | regulator-min-microvolt = <2800000>; |
| 738 | regulator-max-microvolt = <2800000>; |
| 739 | }; |
| 740 | |
| 741 | ldo10 { |
| 742 | regulator-name = "+2.8V_RUN_CAM_AF"; |
| 743 | regulator-min-microvolt = <2800000>; |
| 744 | regulator-max-microvolt = <2800000>; |
| 745 | }; |
| 746 | |
| 747 | ldo11 { |
| 748 | regulator-name = "+1.8V_RUN_VPP_FUSE"; |
| 749 | regulator-min-microvolt = <1800000>; |
| 750 | regulator-max-microvolt = <1800000>; |
| 751 | }; |
| 752 | }; |
| 753 | }; |
| 754 | }; |
| 755 | |
| 756 | spi@7000d400 { |
| 757 | status = "okay"; |
| 758 | |
| 759 | ec: cros-ec@0 { |
| 760 | compatible = "google,cros-ec-spi"; |
| 761 | spi-max-frequency = <3000000>; |
| 762 | interrupt-parent = <&gpio>; |
| 763 | interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; |
| 764 | reg = <0>; |
Tom Rini | 6bb92fc | 2024-05-20 09:54:58 -0600 | [diff] [blame] | 765 | wakeup-source; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 766 | |
| 767 | google,cros-ec-spi-msg-delay = <2000>; |
| 768 | |
| 769 | i2c_20: i2c-tunnel { |
| 770 | compatible = "google,cros-ec-i2c-tunnel"; |
| 771 | #address-cells = <1>; |
| 772 | #size-cells = <0>; |
| 773 | |
| 774 | google,remote-bus = <0>; |
| 775 | |
| 776 | charger: bq24735@9 { |
| 777 | compatible = "ti,bq24735"; |
| 778 | reg = <0x9>; |
| 779 | interrupt-parent = <&gpio>; |
| 780 | interrupts = <TEGRA_GPIO(J, 0) |
| 781 | GPIO_ACTIVE_HIGH>; |
| 782 | ti,ac-detect-gpios = <&gpio |
| 783 | TEGRA_GPIO(J, 0) |
| 784 | GPIO_ACTIVE_HIGH>; |
| 785 | }; |
| 786 | |
| 787 | battery: smart-battery@b { |
| 788 | compatible = "sbs,sbs-battery"; |
| 789 | reg = <0xb>; |
| 790 | sbs,i2c-retry-count = <2>; |
| 791 | sbs,poll-retry-count = <10>; |
| 792 | /* power-supplies = <&charger>; */ |
| 793 | }; |
| 794 | }; |
| 795 | |
| 796 | keyboard-controller { |
| 797 | compatible = "google,cros-ec-keyb"; |
| 798 | keypad,num-rows = <8>; |
| 799 | keypad,num-columns = <13>; |
| 800 | google,needs-ghost-filter; |
| 801 | linux,keymap = |
| 802 | <MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) |
| 803 | MATRIX_KEY(0x00, 0x02, KEY_F1) |
| 804 | MATRIX_KEY(0x00, 0x03, KEY_B) |
| 805 | MATRIX_KEY(0x00, 0x04, KEY_F10) |
| 806 | MATRIX_KEY(0x00, 0x06, KEY_N) |
| 807 | MATRIX_KEY(0x00, 0x08, KEY_EQUAL) |
| 808 | MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) |
| 809 | |
| 810 | MATRIX_KEY(0x01, 0x01, KEY_ESC) |
| 811 | MATRIX_KEY(0x01, 0x02, KEY_F4) |
| 812 | MATRIX_KEY(0x01, 0x03, KEY_G) |
| 813 | MATRIX_KEY(0x01, 0x04, KEY_F7) |
| 814 | MATRIX_KEY(0x01, 0x06, KEY_H) |
| 815 | MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) |
| 816 | MATRIX_KEY(0x01, 0x09, KEY_F9) |
| 817 | MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) |
| 818 | |
| 819 | MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) |
| 820 | MATRIX_KEY(0x02, 0x01, KEY_TAB) |
| 821 | MATRIX_KEY(0x02, 0x02, KEY_F3) |
| 822 | MATRIX_KEY(0x02, 0x03, KEY_T) |
| 823 | MATRIX_KEY(0x02, 0x04, KEY_F6) |
| 824 | MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) |
| 825 | MATRIX_KEY(0x02, 0x06, KEY_Y) |
| 826 | MATRIX_KEY(0x02, 0x07, KEY_102ND) |
| 827 | MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) |
| 828 | MATRIX_KEY(0x02, 0x09, KEY_F8) |
| 829 | |
| 830 | MATRIX_KEY(0x03, 0x01, KEY_GRAVE) |
| 831 | MATRIX_KEY(0x03, 0x02, KEY_F2) |
| 832 | MATRIX_KEY(0x03, 0x03, KEY_5) |
| 833 | MATRIX_KEY(0x03, 0x04, KEY_F5) |
| 834 | MATRIX_KEY(0x03, 0x06, KEY_6) |
| 835 | MATRIX_KEY(0x03, 0x08, KEY_MINUS) |
| 836 | MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) |
| 837 | |
| 838 | MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) |
| 839 | MATRIX_KEY(0x04, 0x01, KEY_A) |
| 840 | MATRIX_KEY(0x04, 0x02, KEY_D) |
| 841 | MATRIX_KEY(0x04, 0x03, KEY_F) |
| 842 | MATRIX_KEY(0x04, 0x04, KEY_S) |
| 843 | MATRIX_KEY(0x04, 0x05, KEY_K) |
| 844 | MATRIX_KEY(0x04, 0x06, KEY_J) |
| 845 | MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) |
| 846 | MATRIX_KEY(0x04, 0x09, KEY_L) |
| 847 | MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) |
| 848 | MATRIX_KEY(0x04, 0x0b, KEY_ENTER) |
| 849 | |
| 850 | MATRIX_KEY(0x05, 0x01, KEY_Z) |
| 851 | MATRIX_KEY(0x05, 0x02, KEY_C) |
| 852 | MATRIX_KEY(0x05, 0x03, KEY_V) |
| 853 | MATRIX_KEY(0x05, 0x04, KEY_X) |
| 854 | MATRIX_KEY(0x05, 0x05, KEY_COMMA) |
| 855 | MATRIX_KEY(0x05, 0x06, KEY_M) |
| 856 | MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) |
| 857 | MATRIX_KEY(0x05, 0x08, KEY_SLASH) |
| 858 | MATRIX_KEY(0x05, 0x09, KEY_DOT) |
| 859 | MATRIX_KEY(0x05, 0x0b, KEY_SPACE) |
| 860 | |
| 861 | MATRIX_KEY(0x06, 0x01, KEY_1) |
| 862 | MATRIX_KEY(0x06, 0x02, KEY_3) |
| 863 | MATRIX_KEY(0x06, 0x03, KEY_4) |
| 864 | MATRIX_KEY(0x06, 0x04, KEY_2) |
| 865 | MATRIX_KEY(0x06, 0x05, KEY_8) |
| 866 | MATRIX_KEY(0x06, 0x06, KEY_7) |
| 867 | MATRIX_KEY(0x06, 0x08, KEY_0) |
| 868 | MATRIX_KEY(0x06, 0x09, KEY_9) |
| 869 | MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) |
| 870 | MATRIX_KEY(0x06, 0x0b, KEY_DOWN) |
| 871 | MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) |
| 872 | |
| 873 | MATRIX_KEY(0x07, 0x01, KEY_Q) |
| 874 | MATRIX_KEY(0x07, 0x02, KEY_E) |
| 875 | MATRIX_KEY(0x07, 0x03, KEY_R) |
| 876 | MATRIX_KEY(0x07, 0x04, KEY_W) |
| 877 | MATRIX_KEY(0x07, 0x05, KEY_I) |
| 878 | MATRIX_KEY(0x07, 0x06, KEY_U) |
| 879 | MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) |
| 880 | MATRIX_KEY(0x07, 0x08, KEY_P) |
| 881 | MATRIX_KEY(0x07, 0x09, KEY_O) |
| 882 | MATRIX_KEY(0x07, 0x0b, KEY_UP) |
| 883 | MATRIX_KEY(0x07, 0x0c, KEY_LEFT)>; |
| 884 | }; |
| 885 | }; |
| 886 | }; |
| 887 | |
| 888 | pmc@7000e400 { |
| 889 | nvidia,invert-interrupt; |
| 890 | nvidia,suspend-mode = <0>; |
| 891 | nvidia,cpu-pwr-good-time = <500>; |
| 892 | nvidia,cpu-pwr-off-time = <300>; |
| 893 | nvidia,core-pwr-good-time = <641 3845>; |
| 894 | nvidia,core-pwr-off-time = <61036>; |
| 895 | nvidia,core-power-req-active-high; |
| 896 | nvidia,sys-clock-req-active-high; |
| 897 | }; |
| 898 | |
| 899 | usb@70090000 { |
| 900 | phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ |
| 901 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ |
| 902 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ |
| 903 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ |
| 904 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ |
| 905 | phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; |
| 906 | |
| 907 | avddio-pex-supply = <&vdd_1v05_run>; |
| 908 | dvddio-pex-supply = <&vdd_1v05_run>; |
| 909 | avdd-usb-supply = <&vdd_3v3_lp0>; |
| 910 | hvdd-usb-ss-supply = <&vdd_3v3_lp0>; |
| 911 | |
| 912 | status = "okay"; |
| 913 | }; |
| 914 | |
| 915 | padctl@7009f000 { |
| 916 | avdd-pll-utmip-supply = <&vddio_1v8>; |
| 917 | avdd-pll-erefe-supply = <&avdd_1v05_run>; |
| 918 | avdd-pex-pll-supply = <&vdd_1v05_run>; |
| 919 | hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; |
| 920 | |
| 921 | pads { |
| 922 | usb2 { |
| 923 | status = "okay"; |
| 924 | |
| 925 | lanes { |
| 926 | usb2-0 { |
| 927 | nvidia,function = "xusb"; |
| 928 | status = "okay"; |
| 929 | }; |
| 930 | |
| 931 | usb2-1 { |
| 932 | nvidia,function = "xusb"; |
| 933 | status = "okay"; |
| 934 | }; |
| 935 | |
| 936 | usb2-2 { |
| 937 | nvidia,function = "xusb"; |
| 938 | status = "okay"; |
| 939 | }; |
| 940 | }; |
| 941 | }; |
| 942 | |
| 943 | pcie { |
| 944 | status = "okay"; |
| 945 | |
| 946 | lanes { |
| 947 | pcie-0 { |
| 948 | nvidia,function = "usb3-ss"; |
| 949 | status = "okay"; |
| 950 | }; |
| 951 | |
| 952 | pcie-1 { |
| 953 | nvidia,function = "usb3-ss"; |
| 954 | status = "okay"; |
| 955 | }; |
| 956 | }; |
| 957 | }; |
| 958 | }; |
| 959 | |
| 960 | ports { |
| 961 | usb2-0 { |
| 962 | status = "okay"; |
| 963 | mode = "otg"; |
| 964 | |
| 965 | vbus-supply = <&vdd_usb1_vbus>; |
| 966 | }; |
| 967 | |
| 968 | usb2-1 { |
| 969 | status = "okay"; |
| 970 | mode = "host"; |
| 971 | |
| 972 | vbus-supply = <&vdd_run_cam>; |
| 973 | }; |
| 974 | |
| 975 | usb2-2 { |
| 976 | status = "okay"; |
| 977 | mode = "host"; |
| 978 | |
| 979 | vbus-supply = <&vdd_usb3_vbus>; |
| 980 | }; |
| 981 | |
| 982 | usb3-0 { |
| 983 | nvidia,usb2-companion = <0>; |
| 984 | status = "okay"; |
| 985 | }; |
| 986 | |
| 987 | usb3-1 { |
| 988 | nvidia,usb2-companion = <2>; |
| 989 | status = "okay"; |
| 990 | }; |
| 991 | }; |
| 992 | }; |
| 993 | |
| 994 | /* WIFI/BT module */ |
| 995 | mmc@700b0000 { |
| 996 | status = "disabled"; |
| 997 | }; |
| 998 | |
| 999 | /* external SD/MMC */ |
| 1000 | mmc@700b0400 { |
| 1001 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 1002 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; |
| 1003 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; |
| 1004 | status = "okay"; |
| 1005 | bus-width = <4>; |
| 1006 | vqmmc-supply = <&vddio_sdmmc3>; |
| 1007 | }; |
| 1008 | |
| 1009 | /* EMMC 4.51 */ |
| 1010 | mmc@700b0600 { |
| 1011 | status = "okay"; |
| 1012 | bus-width = <8>; |
| 1013 | non-removable; |
| 1014 | }; |
| 1015 | |
| 1016 | backlight: backlight { |
| 1017 | compatible = "pwm-backlight"; |
| 1018 | |
| 1019 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| 1020 | power-supply = <&vdd_led>; |
| 1021 | pwms = <&pwm 1 1000000>; |
| 1022 | |
| 1023 | brightness-levels = <0 4 8 16 32 64 128 255>; |
| 1024 | default-brightness-level = <6>; |
| 1025 | }; |
| 1026 | |
| 1027 | clk32k_in: clock-32k { |
| 1028 | compatible = "fixed-clock"; |
| 1029 | clock-frequency = <32768>; |
| 1030 | #clock-cells = <0>; |
| 1031 | }; |
| 1032 | |
| 1033 | gpio-keys { |
| 1034 | compatible = "gpio-keys"; |
| 1035 | |
| 1036 | key-power { |
| 1037 | label = "Power"; |
| 1038 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; |
| 1039 | linux,code = <KEY_POWER>; |
| 1040 | debounce-interval = <10>; |
| 1041 | wakeup-source; |
| 1042 | }; |
| 1043 | |
| 1044 | switch-lid { |
| 1045 | label = "Lid"; |
| 1046 | gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; |
| 1047 | linux,input-type = <5>; |
| 1048 | linux,code = <0>; |
| 1049 | debounce-interval = <1>; |
| 1050 | wakeup-source; |
| 1051 | }; |
| 1052 | }; |
| 1053 | |
| 1054 | panel: panel { |
| 1055 | compatible = "innolux,n116bge"; |
| 1056 | power-supply = <&vdd_3v3_panel>; |
| 1057 | backlight = <&backlight>; |
| 1058 | ddc-i2c-bus = <&dpaux>; |
| 1059 | }; |
| 1060 | |
| 1061 | vdd_mux: regulator-vdd-mux { |
| 1062 | compatible = "regulator-fixed"; |
| 1063 | regulator-name = "+VDD_MUX"; |
| 1064 | regulator-min-microvolt = <19000000>; |
| 1065 | regulator-max-microvolt = <19000000>; |
| 1066 | regulator-always-on; |
| 1067 | regulator-boot-on; |
| 1068 | }; |
| 1069 | |
| 1070 | vdd_5v0_sys: regulator-vdd-5v0-sys { |
| 1071 | compatible = "regulator-fixed"; |
| 1072 | regulator-name = "+5V_SYS"; |
| 1073 | regulator-min-microvolt = <5000000>; |
| 1074 | regulator-max-microvolt = <5000000>; |
| 1075 | regulator-always-on; |
| 1076 | regulator-boot-on; |
| 1077 | vin-supply = <&vdd_mux>; |
| 1078 | }; |
| 1079 | |
| 1080 | vdd_3v3_sys: regulator-vdd-3v3-sys { |
| 1081 | compatible = "regulator-fixed"; |
| 1082 | regulator-name = "+3.3V_SYS"; |
| 1083 | regulator-min-microvolt = <3300000>; |
| 1084 | regulator-max-microvolt = <3300000>; |
| 1085 | regulator-always-on; |
| 1086 | regulator-boot-on; |
| 1087 | vin-supply = <&vdd_mux>; |
| 1088 | }; |
| 1089 | |
| 1090 | vdd_3v3_run: regulator-vdd-3v3-run { |
| 1091 | compatible = "regulator-fixed"; |
| 1092 | regulator-name = "+3.3V_RUN"; |
| 1093 | regulator-min-microvolt = <3300000>; |
| 1094 | regulator-max-microvolt = <3300000>; |
| 1095 | regulator-always-on; |
| 1096 | regulator-boot-on; |
| 1097 | gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; |
| 1098 | enable-active-high; |
| 1099 | vin-supply = <&vdd_3v3_sys>; |
| 1100 | }; |
| 1101 | |
| 1102 | vdd_3v3_hdmi: regulator-vdd-3v3-hdmi { |
| 1103 | compatible = "regulator-fixed"; |
| 1104 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; |
| 1105 | regulator-min-microvolt = <3300000>; |
| 1106 | regulator-max-microvolt = <3300000>; |
| 1107 | vin-supply = <&vdd_3v3_run>; |
| 1108 | }; |
| 1109 | |
| 1110 | vdd_led: regulator-vdd-led { |
| 1111 | compatible = "regulator-fixed"; |
| 1112 | regulator-name = "+VDD_LED"; |
| 1113 | regulator-min-microvolt = <3300000>; |
| 1114 | regulator-max-microvolt = <3300000>; |
| 1115 | gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; |
| 1116 | enable-active-high; |
| 1117 | vin-supply = <&vdd_mux>; |
| 1118 | }; |
| 1119 | |
| 1120 | vdd_usb1_vbus: regulator-vdd-usb1-vbus { |
| 1121 | compatible = "regulator-fixed"; |
| 1122 | regulator-name = "+5V_USB_HS"; |
| 1123 | regulator-min-microvolt = <5000000>; |
| 1124 | regulator-max-microvolt = <5000000>; |
| 1125 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; |
| 1126 | enable-active-high; |
| 1127 | gpio-open-drain; |
| 1128 | vin-supply = <&vdd_5v0_sys>; |
| 1129 | }; |
| 1130 | |
| 1131 | vdd_usb3_vbus: regulator-vdd-usb3-vbus { |
| 1132 | compatible = "regulator-fixed"; |
| 1133 | regulator-name = "+5V_USB_SS"; |
| 1134 | regulator-min-microvolt = <5000000>; |
| 1135 | regulator-max-microvolt = <5000000>; |
| 1136 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; |
| 1137 | enable-active-high; |
| 1138 | gpio-open-drain; |
| 1139 | vin-supply = <&vdd_5v0_sys>; |
| 1140 | }; |
| 1141 | |
| 1142 | vdd_3v3_panel: regulator-vdd-3v3-panel { |
| 1143 | compatible = "regulator-fixed"; |
| 1144 | regulator-name = "+3.3V_PANEL"; |
| 1145 | regulator-min-microvolt = <3300000>; |
| 1146 | regulator-max-microvolt = <3300000>; |
| 1147 | gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; |
| 1148 | enable-active-high; |
| 1149 | vin-supply = <&vdd_3v3_sys>; |
| 1150 | }; |
| 1151 | |
| 1152 | vdd_hdmi_pll: regulator-vdd-hdmi-pll { |
| 1153 | compatible = "regulator-fixed"; |
| 1154 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; |
| 1155 | regulator-min-microvolt = <1050000>; |
| 1156 | regulator-max-microvolt = <1050000>; |
| 1157 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; |
| 1158 | vin-supply = <&vdd_1v05_run>; |
| 1159 | }; |
| 1160 | |
| 1161 | vdd_5v0_hdmi: regulator-vdd-5v0-hdmi { |
| 1162 | compatible = "regulator-fixed"; |
| 1163 | regulator-name = "+5V_HDMI_CON"; |
| 1164 | regulator-min-microvolt = <5000000>; |
| 1165 | regulator-max-microvolt = <5000000>; |
| 1166 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
| 1167 | enable-active-high; |
| 1168 | vin-supply = <&vdd_5v0_sys>; |
| 1169 | }; |
| 1170 | |
| 1171 | vdd_5v0_ts: regulator-vdd-5v0-ts { |
| 1172 | compatible = "regulator-fixed"; |
| 1173 | regulator-name = "+5V_VDD_TS"; |
| 1174 | regulator-min-microvolt = <5000000>; |
| 1175 | regulator-max-microvolt = <5000000>; |
| 1176 | regulator-always-on; |
| 1177 | regulator-boot-on; |
| 1178 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; |
| 1179 | enable-active-high; |
| 1180 | }; |
| 1181 | |
| 1182 | vdd_3v3_lp0: regulator-vdd-3v3-lp0 { |
| 1183 | compatible = "regulator-fixed"; |
| 1184 | regulator-name = "+3.3V_LP0"; |
| 1185 | regulator-min-microvolt = <3300000>; |
| 1186 | regulator-max-microvolt = <3300000>; |
| 1187 | /* |
| 1188 | * TODO: find a way to wire this up with the USB EHCI |
| 1189 | * controllers so that it can be enabled on demand. |
| 1190 | */ |
| 1191 | regulator-always-on; |
| 1192 | gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; |
| 1193 | enable-active-high; |
| 1194 | vin-supply = <&vdd_3v3_sys>; |
| 1195 | }; |
| 1196 | }; |