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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / hisilicon / hi3670.dtsi
blob: 886b93c5893a09b8e2e7bf22ee8afba3a5f9a045 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, HiSilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/hi3670-clock.h>
11
12/ {
13 compatible = "hisilicon,hi3670";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 psci {
19 compatible = "arm,psci-0.2";
20 method = "smc";
21 };
22
23 cpus {
24 #address-cells = <2>;
25 #size-cells = <0>;
26
27 cpu-map {
28 cluster0 {
29 core0 {
30 cpu = <&cpu0>;
31 };
32 core1 {
33 cpu = <&cpu1>;
34 };
35 core2 {
36 cpu = <&cpu2>;
37 };
38 core3 {
39 cpu = <&cpu3>;
40 };
41 };
42 cluster1 {
43 core0 {
44 cpu = <&cpu4>;
45 };
46 core1 {
47 cpu = <&cpu5>;
48 };
49 core2 {
50 cpu = <&cpu6>;
51 };
52 core3 {
53 cpu = <&cpu7>;
54 };
55 };
56 };
57
58 cpu0: cpu@0 {
59 compatible = "arm,cortex-a53";
60 device_type = "cpu";
61 reg = <0x0 0x0>;
62 enable-method = "psci";
63 };
64
65 cpu1: cpu@1 {
66 compatible = "arm,cortex-a53";
67 device_type = "cpu";
68 reg = <0x0 0x1>;
69 enable-method = "psci";
70 };
71
72 cpu2: cpu@2 {
73 compatible = "arm,cortex-a53";
74 device_type = "cpu";
75 reg = <0x0 0x2>;
76 enable-method = "psci";
77 };
78
79 cpu3: cpu@3 {
80 compatible = "arm,cortex-a53";
81 device_type = "cpu";
82 reg = <0x0 0x3>;
83 enable-method = "psci";
84 };
85
86 cpu4: cpu@100 {
87 compatible = "arm,cortex-a73";
88 device_type = "cpu";
89 reg = <0x0 0x100>;
90 enable-method = "psci";
91 };
92
93 cpu5: cpu@101 {
94 compatible = "arm,cortex-a73";
95 device_type = "cpu";
96 reg = <0x0 0x101>;
97 enable-method = "psci";
98 };
99
100 cpu6: cpu@102 {
101 compatible = "arm,cortex-a73";
102 device_type = "cpu";
103 reg = <0x0 0x102>;
104 enable-method = "psci";
105 };
106
107 cpu7: cpu@103 {
108 compatible = "arm,cortex-a73";
109 device_type = "cpu";
110 reg = <0x0 0x103>;
111 enable-method = "psci";
112 };
113 };
114
115 gic: interrupt-controller@e82b0000 {
116 compatible = "arm,gic-400";
117 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
118 <0x0 0xe82b2000 0 0x2000>, /* GICC */
119 <0x0 0xe82b4000 0 0x2000>, /* GICH */
120 <0x0 0xe82b6000 0 0x2000>; /* GICV */
121 #interrupt-cells = <3>;
122 #address-cells = <0>;
123 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
124 IRQ_TYPE_LEVEL_HIGH)>;
125 interrupt-controller;
126 };
127
128 timer {
129 compatible = "arm,armv8-timer";
130 interrupt-parent = <&gic>;
131 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
132 IRQ_TYPE_LEVEL_LOW)>,
133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
134 IRQ_TYPE_LEVEL_LOW)>,
135 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
136 IRQ_TYPE_LEVEL_LOW)>,
137 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
138 IRQ_TYPE_LEVEL_LOW)>;
139 clock-frequency = <1920000>;
140 };
141
142 soc {
143 compatible = "simple-bus";
144 #address-cells = <2>;
145 #size-cells = <2>;
146 ranges;
147
148 crg_ctrl: crg_ctrl@fff35000 {
149 compatible = "hisilicon,hi3670-crgctrl", "syscon";
150 reg = <0x0 0xfff35000 0x0 0x1000>;
151 #clock-cells = <1>;
152 };
153
154 crg_rst: crg_rst_controller {
155 compatible = "hisilicon,hi3670-reset",
156 "hisilicon,hi3660-reset";
157 #reset-cells = <2>;
158 hisi,rst-syscon = <&crg_ctrl>;
159 };
160
161 pctrl: pctrl@e8a09000 {
162 compatible = "hisilicon,hi3670-pctrl", "syscon";
163 reg = <0x0 0xe8a09000 0x0 0x1000>;
164 #clock-cells = <1>;
165 };
166
167 pmuctrl: crg_ctrl@fff34000 {
168 compatible = "hisilicon,hi3670-pmuctrl", "syscon";
169 reg = <0x0 0xfff34000 0x0 0x1000>;
170 #clock-cells = <1>;
171 };
172
173 sctrl: sctrl@fff0a000 {
174 compatible = "hisilicon,hi3670-sctrl", "syscon";
175 reg = <0x0 0xfff0a000 0x0 0x1000>;
176 #clock-cells = <1>;
177 };
178
179 iomcu: iomcu@ffd7e000 {
180 compatible = "hisilicon,hi3670-iomcu", "syscon";
181 reg = <0x0 0xffd7e000 0x0 0x1000>;
182 #clock-cells = <1>;
183 };
184
185 media1_crg: media1_crgctrl@e87ff000 {
186 compatible = "hisilicon,hi3670-media1-crg", "syscon";
187 reg = <0x0 0xe87ff000 0x0 0x1000>;
188 #clock-cells = <1>;
189 };
190
191 media2_crg: media2_crgctrl@e8900000 {
192 compatible = "hisilicon,hi3670-media2-crg","syscon";
193 reg = <0x0 0xe8900000 0x0 0x1000>;
194 #clock-cells = <1>;
195 };
196
197 iomcu_rst: reset {
198 compatible = "hisilicon,hi3660-reset";
199 hisi,rst-syscon = <&iomcu>;
200 #reset-cells = <2>;
201 };
202
203 uart0: serial@fdf02000 {
204 compatible = "arm,pl011", "arm,primecell";
205 reg = <0x0 0xfdf02000 0x0 0x1000>;
206 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
208 <&crg_ctrl HI3670_PCLK>;
209 clock-names = "uartclk", "apb_pclk";
210 pinctrl-names = "default";
211 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
212 status = "disabled";
213 };
214
215 uart1: serial@fdf00000 {
216 compatible = "arm,pl011", "arm,primecell";
217 reg = <0x0 0xfdf00000 0x0 0x1000>;
218 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
220 <&crg_ctrl HI3670_PCLK>;
221 clock-names = "uartclk", "apb_pclk";
222 status = "disabled";
223 };
224
225 uart2: serial@fdf03000 {
226 compatible = "arm,pl011", "arm,primecell";
227 reg = <0x0 0xfdf03000 0x0 0x1000>;
228 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
230 <&crg_ctrl HI3670_PCLK>;
231 clock-names = "uartclk", "apb_pclk";
232 pinctrl-names = "default";
233 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
234 status = "disabled";
235 };
236
237 uart3: serial@ffd74000 {
238 compatible = "arm,pl011", "arm,primecell";
239 reg = <0x0 0xffd74000 0x0 0x1000>;
240 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
242 <&crg_ctrl HI3670_PCLK>;
243 clock-names = "uartclk", "apb_pclk";
244 pinctrl-names = "default";
245 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
246 status = "disabled";
247 };
248
249 uart4: serial@fdf01000 {
250 compatible = "arm,pl011", "arm,primecell";
251 reg = <0x0 0xfdf01000 0x0 0x1000>;
252 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>,
254 <&crg_ctrl HI3670_PCLK>;
255 clock-names = "uartclk", "apb_pclk";
256 pinctrl-names = "default";
257 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
258 status = "disabled";
259 };
260
261 uart5: serial@fdf05000 {
262 compatible = "arm,pl011", "arm,primecell";
263 reg = <0x0 0xfdf05000 0x0 0x1000>;
264 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
266 <&crg_ctrl HI3670_PCLK>;
267 clock-names = "uartclk", "apb_pclk";
268 status = "disabled";
269 };
270
271 uart6: serial@fff32000 {
272 compatible = "arm,pl011", "arm,primecell";
273 reg = <0x0 0xfff32000 0x0 0x1000>;
274 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&crg_ctrl HI3670_CLK_UART6>,
276 <&crg_ctrl HI3670_PCLK>;
277 clock-names = "uartclk", "apb_pclk";
278 pinctrl-names = "default";
279 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
280 status = "disabled";
281 };
282
283 gpio0: gpio@e8a0b000 {
284 compatible = "arm,pl061", "arm,primecell";
285 reg = <0x0 0xe8a0b000 0x0 0x1000>;
286 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
287 gpio-controller;
288 #gpio-cells = <2>;
289 gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 clocks = <&crg_ctrl HI3670_PCLK_GPIO0>;
293 clock-names = "apb_pclk";
294 };
295
296 gpio1: gpio@e8a0c000 {
297 compatible = "arm,pl061", "arm,primecell";
298 reg = <0x0 0xe8a0c000 0x0 0x1000>;
299 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
300 gpio-controller;
301 #gpio-cells = <2>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
304 clocks = <&crg_ctrl HI3670_PCLK_GPIO1>;
305 clock-names = "apb_pclk";
306 };
307
308 gpio2: gpio@e8a0d000 {
309 compatible = "arm,pl061", "arm,primecell";
310 reg = <0x0 0xe8a0d000 0x0 0x1000>;
311 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
312 gpio-controller;
313 #gpio-cells = <2>;
314 gpio-ranges = <&pmx0 1 6 7>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 clocks = <&crg_ctrl HI3670_PCLK_GPIO2>;
318 clock-names = "apb_pclk";
319 };
320
321 gpio3: gpio@e8a0e000 {
322 compatible = "arm,pl061", "arm,primecell";
323 reg = <0x0 0xe8a0e000 0x0 0x1000>;
324 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
325 gpio-controller;
326 #gpio-cells = <2>;
327 gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;
331 clock-names = "apb_pclk";
332 };
333
334 gpio4: gpio@e8a0f000 {
335 compatible = "arm,pl061", "arm,primecell";
336 reg = <0x0 0xe8a0f000 0x0 0x1000>;
337 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
338 gpio-controller;
339 #gpio-cells = <2>;
340 gpio-ranges = <&pmx0 0 18 8>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
343 clocks = <&crg_ctrl HI3670_PCLK_GPIO4>;
344 clock-names = "apb_pclk";
345 };
346
347 gpio5: gpio@e8a10000 {
348 compatible = "arm,pl061", "arm,primecell";
349 reg = <0x0 0xe8a10000 0x0 0x1000>;
350 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 gpio-ranges = <&pmx0 0 26 8>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 clocks = <&crg_ctrl HI3670_PCLK_GPIO5>;
357 clock-names = "apb_pclk";
358 };
359
360 gpio6: gpio@e8a11000 {
361 compatible = "arm,pl061", "arm,primecell";
362 reg = <0x0 0xe8a11000 0x0 0x1000>;
363 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 gpio-ranges = <&pmx0 1 34 7>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 clocks = <&crg_ctrl HI3670_PCLK_GPIO6>;
370 clock-names = "apb_pclk";
371 };
372
373 gpio7: gpio@e8a12000 {
374 compatible = "arm,pl061", "arm,primecell";
375 reg = <0x0 0xe8a12000 0x0 0x1000>;
376 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
377 gpio-controller;
378 #gpio-cells = <2>;
379 gpio-ranges = <&pmx0 0 41 8>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 clocks = <&crg_ctrl HI3670_PCLK_GPIO7>;
383 clock-names = "apb_pclk";
384 };
385
386 gpio8: gpio@e8a13000 {
387 compatible = "arm,pl061", "arm,primecell";
388 reg = <0x0 0xe8a13000 0x0 0x1000>;
389 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 gpio-ranges = <&pmx0 0 49 8>;
393 interrupt-controller;
394 #interrupt-cells = <2>;
395 clocks = <&crg_ctrl HI3670_PCLK_GPIO8>;
396 clock-names = "apb_pclk";
397 };
398
399 gpio9: gpio@e8a14000 {
400 compatible = "arm,pl061", "arm,primecell";
401 reg = <0x0 0xe8a14000 0x0 0x1000>;
402 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
403 gpio-controller;
404 #gpio-cells = <2>;
405 gpio-ranges = <&pmx0 0 57 8>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 clocks = <&crg_ctrl HI3670_PCLK_GPIO9>;
409 clock-names = "apb_pclk";
410 };
411
412 gpio10: gpio@e8a15000 {
413 compatible = "arm,pl061", "arm,primecell";
414 reg = <0x0 0xe8a15000 0x0 0x1000>;
415 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
416 gpio-controller;
417 #gpio-cells = <2>;
418 gpio-ranges = <&pmx0 0 65 8>;
419 interrupt-controller;
420 #interrupt-cells = <2>;
421 clocks = <&crg_ctrl HI3670_PCLK_GPIO10>;
422 clock-names = "apb_pclk";
423 };
424
425 gpio11: gpio@e8a16000 {
426 compatible = "arm,pl061", "arm,primecell";
427 reg = <0x0 0xe8a16000 0x0 0x1000>;
428 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
429 gpio-controller;
430 #gpio-cells = <2>;
431 gpio-ranges = <&pmx0 0 73 8>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
434 clocks = <&crg_ctrl HI3670_PCLK_GPIO11>;
435 clock-names = "apb_pclk";
436 };
437
438 gpio12: gpio@e8a17000 {
439 compatible = "arm,pl061", "arm,primecell";
440 reg = <0x0 0xe8a17000 0x0 0x1000>;
441 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
442 gpio-controller;
443 #gpio-cells = <2>;
444 gpio-ranges = <&pmx0 0 81 1>;
445 interrupt-controller;
446 #interrupt-cells = <2>;
447 clocks = <&crg_ctrl HI3670_PCLK_GPIO12>;
448 clock-names = "apb_pclk";
449 };
450
451 gpio13: gpio@e8a18000 {
452 compatible = "arm,pl061", "arm,primecell";
453 reg = <0x0 0xe8a18000 0x0 0x1000>;
454 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
455 gpio-controller;
456 #gpio-cells = <2>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
459 clocks = <&crg_ctrl HI3670_PCLK_GPIO13>;
460 clock-names = "apb_pclk";
461 };
462
463 gpio14: gpio@e8a19000 {
464 compatible = "arm,pl061", "arm,primecell";
465 reg = <0x0 0xe8a19000 0x0 0x1000>;
466 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
467 gpio-controller;
468 #gpio-cells = <2>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
471 clocks = <&crg_ctrl HI3670_PCLK_GPIO14>;
472 clock-names = "apb_pclk";
473 };
474
475 gpio15: gpio@e8a1a000 {
476 compatible = "arm,pl061", "arm,primecell";
477 reg = <0x0 0xe8a1a000 0x0 0x1000>;
478 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
479 gpio-controller;
480 #gpio-cells = <2>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 clocks = <&crg_ctrl HI3670_PCLK_GPIO15>;
484 clock-names = "apb_pclk";
485 };
486
487 gpio16: gpio@e8a1b000 {
488 compatible = "arm,pl061", "arm,primecell";
489 reg = <0x0 0xe8a1b000 0x0 0x1000>;
490 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
491 gpio-controller;
492 #gpio-cells = <2>;
493 gpio-ranges = <&pmx5 0 0 8>;
494 interrupt-controller;
495 #interrupt-cells = <2>;
496 clocks = <&crg_ctrl HI3670_PCLK_GPIO16>;
497 clock-names = "apb_pclk";
498 };
499
500 gpio17: gpio@e8a1c000 {
501 compatible = "arm,pl061", "arm,primecell";
502 reg = <0x0 0xe8a1c000 0x0 0x1000>;
503 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
504 gpio-controller;
505 #gpio-cells = <2>;
506 gpio-ranges = <&pmx5 0 8 2>;
507 interrupt-controller;
508 #interrupt-cells = <2>;
509 clocks = <&crg_ctrl HI3670_PCLK_GPIO17>;
510 clock-names = "apb_pclk";
511 };
512
513 gpio18: gpio@fff28000 {
514 compatible = "arm,pl061", "arm,primecell";
515 reg = <0x0 0xfff28000 0x0 0x1000>;
516 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
517 gpio-controller;
518 #gpio-cells = <2>;
519 gpio-ranges = <&pmx1 4 42 4>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
522 clocks = <&sctrl HI3670_PCLK_GPIO18>;
523 clock-names = "apb_pclk";
524 };
525
526 gpio19: gpio@fff29000 {
527 compatible = "arm,pl061", "arm,primecell";
528 reg = <0x0 0xfff29000 0x0 0x1000>;
529 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
530 gpio-controller;
531 #gpio-cells = <2>;
532 gpio-ranges = <&pmx1 0 61 2>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
535 clocks = <&sctrl HI3670_PCLK_GPIO19>;
536 clock-names = "apb_pclk";
537 };
538
539 gpio20: gpio@e8a1f000 {
540 compatible = "arm,pl061", "arm,primecell";
541 reg = <0x0 0xe8a1f000 0x0 0x1000>;
542 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
543 gpio-controller;
544 #gpio-cells = <2>;
545 gpio-ranges = <&pmx7 0 0 8>;
546 interrupt-controller;
547 #interrupt-cells = <2>;
548 clocks = <&crg_ctrl HI3670_PCLK_GPIO20>;
549 clock-names = "apb_pclk";
550 };
551
552 gpio21: gpio@e8a20000 {
553 compatible = "arm,pl061", "arm,primecell";
554 reg = <0x0 0xe8a20000 0x0 0x1000>;
555 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
556 gpio-controller;
557 #gpio-cells = <2>;
558 gpio-ranges = <&pmx7 0 8 4>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
561 clocks = <&crg_ctrl HI3670_PCLK_GPIO21>;
562 clock-names = "apb_pclk";
563 };
564
565 gpio22: gpio@fff0b000 {
566 compatible = "arm,pl061", "arm,primecell";
567 reg = <0x0 0xfff0b000 0x0 0x1000>;
568 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
569 gpio-controller;
570 #gpio-cells = <2>;
571 /* GPIO176 */
572 gpio-ranges = <&pmx1 2 0 6>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 clocks = <&sctrl HI3670_PCLK_AO_GPIO0>;
576 clock-names = "apb_pclk";
577 };
578
579 gpio23: gpio@fff0c000 {
580 compatible = "arm,pl061", "arm,primecell";
581 reg = <0x0 0xfff0c000 0x0 0x1000>;
582 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
583 gpio-controller;
584 #gpio-cells = <2>;
585 /* GPIO184 */
586 gpio-ranges = <&pmx1 0 6 8>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
589 clocks = <&sctrl HI3670_PCLK_AO_GPIO1>;
590 clock-names = "apb_pclk";
591 };
592
593 gpio24: gpio@fff0d000 {
594 compatible = "arm,pl061", "arm,primecell";
595 reg = <0x0 0xfff0d000 0x0 0x1000>;
596 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
597 gpio-controller;
598 #gpio-cells = <2>;
599 /* GPIO192 */
600 gpio-ranges = <&pmx1 0 14 8>;
601 interrupt-controller;
602 #interrupt-cells = <2>;
603 clocks = <&sctrl HI3670_PCLK_AO_GPIO2>;
604 clock-names = "apb_pclk";
605 };
606
607 gpio25: gpio@fff0e000 {
608 compatible = "arm,pl061", "arm,primecell";
609 reg = <0x0 0xfff0e000 0x0 0x1000>;
610 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
611 gpio-controller;
612 #gpio-cells = <2>;
613 /* GPIO200 */
614 gpio-ranges = <&pmx1 0 22 8>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
617 clocks = <&sctrl HI3670_PCLK_AO_GPIO3>;
618 clock-names = "apb_pclk";
619 };
620
621 gpio26: gpio@fff0f000 {
622 compatible = "arm,pl061", "arm,primecell";
623 reg = <0x0 0xfff0f000 0x0 0x1000>;
624 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
625 gpio-controller;
626 #gpio-cells = <2>;
627 /* GPIO208 */
628 gpio-ranges = <&pmx1 0 30 1>;
629 interrupt-controller;
630 #interrupt-cells = <2>;
631 clocks = <&sctrl HI3670_PCLK_AO_GPIO4>;
632 clock-names = "apb_pclk";
633 };
634
635 gpio27: gpio@fff10000 {
636 compatible = "arm,pl061", "arm,primecell";
637 reg = <0x0 0xfff10000 0x0 0x1000>;
638 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
639 gpio-controller;
640 #gpio-cells = <2>;
641 /* GPIO216 */
642 gpio-ranges = <&pmx1 4 31 4>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
645 clocks = <&sctrl HI3670_PCLK_AO_GPIO5>;
646 clock-names = "apb_pclk";
647 };
648
649 gpio28: gpio@fff1d000 {
650 compatible = "arm,pl061", "arm,primecell";
651 reg = <0x0 0xfff1d000 0x0 0x1000>;
652 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
653 gpio-controller;
654 #gpio-cells = <2>;
655 gpio-ranges = <&pmx1 1 35 7>;
656 interrupt-controller;
657 #interrupt-cells = <2>;
658 clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;
659 clock-names = "apb_pclk";
660 };
661
662 /* UFS */
663 ufs: ufs@ff3c0000 {
664 compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
665 /* 0: HCI standard */
666 /* 1: UFS SYS CTRL */
667 reg = <0x0 0xff3c0000 0x0 0x1000>,
668 <0x0 0xff3e0000 0x0 0x1000>;
669 interrupt-parent = <&gic>;
670 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
672 <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
673 clock-names = "ref_clk", "phy_clk";
674 freq-table-hz = <0 0>,
675 <0 0>;
676 /* offset: 0x84; bit: 12 */
677 resets = <&crg_rst 0x84 12>;
678 reset-names = "rst";
679 };
680
681 /* SD */
682 dwmmc1: dwmmc1@ff37f000 {
683 compatible = "hisilicon,hi3670-dw-mshc",
684 "hisilicon,hi3660-dw-mshc";
685 reg = <0x0 0xff37f000 0x0 0x1000>;
686 #address-cells = <1>;
687 #size-cells = <0>;
688 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&crg_ctrl HI3670_CLK_GATE_SD>,
690 <&crg_ctrl HI3670_HCLK_GATE_SD>;
691 clock-names = "ciu", "biu";
692 clock-frequency = <3200000>;
693 resets = <&crg_rst 0x94 18>;
694 reset-names = "reset";
695 hisilicon,peripheral-syscon = <&sctrl>;
696 card-detect-delay = <200>;
697 status = "disabled";
698 };
699
700 /* SDIO */
701 dwmmc2: dwmmc2@fc183000 {
702 compatible = "hisilicon,hi3670-dw-mshc",
703 "hisilicon,hi3660-dw-mshc";
704 reg = <0x0 0xfc183000 0x0 0x1000>;
705 #address-cells = <1>;
706 #size-cells = <0>;
707 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>,
709 <&crg_ctrl HI3670_HCLK_GATE_SDIO>;
710 clock-names = "ciu", "biu";
711 clock-frequency = <3200000>;
712 resets = <&crg_rst 0x94 20>;
713 reset-names = "reset";
714 card-detect-delay = <200>;
715 status = "disabled";
716 };
717
718 /* I2C */
719 i2c0: i2c@ffd71000 {
720 compatible = "snps,designware-i2c";
721 reg = <0x0 0xffd71000 0x0 0x1000>;
722 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
723 #address-cells = <1>;
724 #size-cells = <0>;
725 clock-frequency = <400000>;
726 clocks = <&iomcu HI3670_CLK_GATE_I2C0>;
727 resets = <&iomcu_rst 0x20 3>;
728 pinctrl-names = "default";
729 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
730 status = "disabled";
731 };
732
733 i2c1: i2c@ffd72000 {
734 compatible = "snps,designware-i2c";
735 reg = <0x0 0xffd72000 0x0 0x1000>;
736 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
737 #address-cells = <1>;
738 #size-cells = <0>;
739 clock-frequency = <400000>;
740 clocks = <&iomcu HI3670_CLK_GATE_I2C1>;
741 resets = <&iomcu_rst 0x20 4>;
742 pinctrl-names = "default";
743 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
744 status = "disabled";
745 };
746
747 i2c2: i2c@ffd73000 {
748 compatible = "snps,designware-i2c";
749 reg = <0x0 0xffd73000 0x0 0x1000>;
750 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
751 #address-cells = <1>;
752 #size-cells = <0>;
753 clock-frequency = <400000>;
754 clocks = <&iomcu HI3670_CLK_GATE_I2C2>;
755 resets = <&iomcu_rst 0x20 5>;
756 pinctrl-names = "default";
757 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
758 status = "disabled";
759 };
760
761 i2c3: i2c@fdf0c000 {
762 compatible = "snps,designware-i2c";
763 reg = <0x0 0xfdf0c000 0x0 0x1000>;
764 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
765 #address-cells = <1>;
766 #size-cells = <0>;
767 clock-frequency = <400000>;
768 clocks = <&crg_ctrl HI3670_CLK_GATE_I2C3>;
769 resets = <&crg_rst 0x78 7>;
770 pinctrl-names = "default";
771 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
772 status = "disabled";
773 };
774
775 i2c4: i2c@fdf0d000 {
776 compatible = "snps,designware-i2c";
777 reg = <0x0 0xfdf0d000 0x0 0x1000>;
778 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
779 #address-cells = <1>;
780 #size-cells = <0>;
781 clock-frequency = <400000>;
782 clocks = <&crg_ctrl HI3670_CLK_GATE_I2C4>;
783 resets = <&crg_rst 0x78 27>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>;
786 status = "disabled";
787 };
788 };
789};