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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / freescale / mba8xx.dtsi
blob: 276d1683b03bb0fa431aac63b337b46d8fc0e4be [file] [log] [blame]
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
2/*
3 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/leds/common.h>
10#include <dt-bindings/net/ti-dp83867.h>
11
12/ {
13 adc {
14 compatible = "iio-hwmon";
15 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
16 };
17
18 aliases {
19 rtc0 = &pcf85063;
20 rtc1 = &rtc;
21 };
22
23 backlight_lvds: backlight-lvds {
24 compatible = "pwm-backlight";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_bl_lvds>;
27 pwms = <&adma_pwm 0 5000000 0>;
28 brightness-levels = <0 4 8 16 32 64 128 255>;
29 default-brightness-level = <7>;
30 power-supply = <&reg_12v0>;
31 enable-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>;
32 status = "disabled";
33 };
34
35 chosen {
36 stdout-path = &lpuart1;
37 };
38
39 gpio-keys {
40 compatible = "gpio-keys";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_gpiobuttons>;
43 autorepeat;
44
45 switch-a {
46 label = "switcha";
47 linux,code = <BTN_0>;
48 gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>;
49 };
50
51 switch-b {
52 label = "switchb";
53 linux,code = <BTN_1>;
54 gpios = <&lsio_gpio1 14 GPIO_ACTIVE_LOW>;
55 };
56 };
57
58 gpio-leds {
59 compatible = "gpio-leds";
60
61 led1 {
62 color = <LED_COLOR_ID_GREEN>;
63 function = LED_FUNCTION_STATUS;
64 gpios = <&expander 1 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "default-on";
66 };
67
68 led2 {
69 color = <LED_COLOR_ID_GREEN>;
70 function = LED_FUNCTION_HEARTBEAT;
71 gpios = <&expander 2 GPIO_ACTIVE_HIGH>;
72 linux,default-trigger = "heartbeat";
73 };
74 };
75
76 /* TODO LVDS panels */
77
78 reg_12v0: regulator-12v0 {
79 compatible = "regulator-fixed";
80 regulator-name = "V_12V";
81 regulator-min-microvolt = <12000000>;
82 regulator-max-microvolt = <12000000>;
83 gpio = <&expander 6 GPIO_ACTIVE_HIGH>;
84 enable-active-high;
85 };
86
87 reg_pcie_1v5: regulator-pcie-1v5 {
88 compatible = "regulator-fixed";
89 regulator-name = "MBA8XX_PCIE_1V5";
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_reg_pcie_1v5>;
92 regulator-min-microvolt = <1500000>;
93 regulator-max-microvolt = <1500000>;
94 gpio = <&lsio_gpio0 30 GPIO_ACTIVE_HIGH>;
95 startup-delay-us = <1000>;
96 enable-active-high;
97 };
98
99 reg_pcie_3v3: regulator-pcie-3v3 {
100 compatible = "regulator-fixed";
101 regulator-name = "MBA8XX_PCIE_3V3";
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_reg_pcie_3v3>;
104 regulator-min-microvolt = <3300000>;
105 regulator-max-microvolt = <3300000>;
106 gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
107 startup-delay-us = <1000>;
108 enable-active-high;
109 regulator-always-on;
110 };
111
112 reg_3v3_mb: regulator-usdhc2-vmmc {
113 compatible = "regulator-fixed";
114 regulator-name = "V_3V3_MB";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 };
118
119 sound {
120 compatible = "fsl,imx-audio-tlv320aic32x4";
121 model = "tqm-tlv320aic32";
122 audio-codec = <&tlv320aic3x04>;
123 ssi-controller = <&sai1>;
124 };
125};
126
127&adc0 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_adc0>;
130 vref-supply = <&reg_1v8>;
131 #io-channel-cells = <1>;
132 status = "okay";
133};
134
135&adma_pwm {
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_admapwm>;
138};
139
140&fec1 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_fec1>;
143 phy-mode = "rgmii-id";
144 phy-handle = <&ethphy0>;
145 status = "okay";
146
147 mdio {
148 #address-cells = <1>;
149 #size-cells = <0>;
150
151 ethphy0: ethernet-phy@0 {
152 compatible = "ethernet-phy-ieee802.3-c22";
153 reg = <0>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_ethphy0>;
156 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
157 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
158 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
159 ti,dp83867-rxctrl-strap-quirk;
160 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
161 reset-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_LOW>;
162 reset-assert-us = <500000>;
163 reset-deassert-us = <50000>;
164 enet-phy-lane-no-swap;
165 interrupt-parent = <&lsio_gpio3>;
166 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
167 };
168
169 ethphy3: ethernet-phy@3 {
170 compatible = "ethernet-phy-ieee802.3-c22";
171 reg = <3>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_ethphy3>;
174 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
175 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
176 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
177 ti,dp83867-rxctrl-strap-quirk;
178 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
179 reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>;
180 reset-assert-us = <500000>;
181 reset-deassert-us = <50000>;
182 enet-phy-lane-no-swap;
183 interrupt-parent = <&lsio_gpio3>;
184 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
185 };
186 };
187};
188
189&fec2 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_fec2>;
192 phy-mode = "rgmii-id";
193 phy-handle = <&ethphy3>;
194 status = "okay";
195};
196
197&flexcan1 {
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_can0>;
200 xceiver-supply = <&reg_3v3>;
201 status = "okay";
202};
203
204&flexcan2 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_can1>;
207 xceiver-supply = <&reg_3v3>;
208 status = "okay";
209};
210
211&i2c1 {
212 tlv320aic3x04: audio-codec@18 {
213 compatible = "ti,tlv320aic32x4";
214 reg = <0x18>;
215 clocks = <&mclkout0_lpcg 0>;
216 clock-names = "mclk";
217 iov-supply = <&reg_1v8>;
218 ldoin-supply = <&reg_3v3>;
219 };
220
221 se97b_1c: temperature-sensor@1c {
222 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
223 reg = <0x1c>;
224 };
225
226 at24c02_54: eeprom@54 {
227 compatible = "nxp,se97b", "atmel,24c02";
228 reg = <0x54>;
229 pagesize = <16>;
230 vcc-supply = <&reg_3v3>;
231 };
232
233 expander: gpio@70 {
234 compatible = "nxp,pca9538";
235 reg = <0x70>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_pca9538>;
238 gpio-controller;
239 #gpio-cells = <2>;
240 interrupt-parent = <&lsio_gpio4>;
241 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
244 vcc-supply = <&reg_1v8>;
245
246 gpio-line-names = "", "LED_A",
247 "LED_B", "",
248 "DSI_EN", "USB_RESET#",
249 "V_12V_EN", "PCIE_DIS#";
250 };
251};
252
253&i2c2 {
254 clock-frequency = <100000>;
255 pinctrl-names = "default", "gpio";
256 pinctrl-0 = <&pinctrl_lpi2c2>;
257 pinctrl-1 = <&pinctrl_lpi2c2gpio>;
258 scl-gpios = <&lsio_gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
259 sda-gpios = <&lsio_gpio2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
260 status = "okay";
261};
262
263/* TODO LDB */
264
265&lpspi1 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_spi1>;
268 cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>;
269 status = "okay";
270};
271
272&lpspi2 {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_spi2>;
275 cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
276 status = "okay";
277};
278
279&lpspi3 {
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_spi3>;
282 num-cs = <2>;
283 cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>;
284 status = "okay";
285};
286
287&lpuart1 {
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_lpuart1>;
290 status = "okay";
291};
292
293&lpuart3 {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_lpuart3>;
296 status = "okay";
297};
298
299&lsio_gpio3 {
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_lsgpio3>;
302 gpio-line-names = "", "", "", "",
303 "", "", "", "",
304 "", "", "", "",
305 "", "", "", "X4_15",
306 "", "", "", "",
307 "", "", "", "",
308 "", "", "", "",
309 "", "", "", "";
310};
311
312/* TODO: Mini-PCIe */
313
314&sai1 {
315 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
316 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
317 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
318 <&sai1_lpcg 0>;
319 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_sai1>;
322 status = "okay";
323};
324
325&usbotg1 {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_usbotg1>;
328 srp-disable;
329 hnp-disable;
330 adp-disable;
331 power-active-high;
332 over-current-active-low;
333 dr_mode = "otg";
334 status = "okay";
335};
336
337&usbotg3 {
338 status = "okay";
339};
340
341&usbotg3_cdns3 {
342 dr_mode = "host";
343 status = "okay";
344};
345
346&usbphy1 {
347 status = "okay";
348};
349
350&usb3_phy {
351 status = "okay";
352};
353
354&usdhc2 {
355 pinctrl-names = "default", "state_100mhz", "state_200mhz";
356 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
357 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
358 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
359 bus-width = <4>;
360 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
361 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
362 vmmc-supply = <&reg_3v3_mb>;
363 no-1-8-v;
364 no-sdio;
365 no-mmc;
366 status = "okay";
367};
368
369&iomuxc {
370 pinctrl_adc0: adc0grp {
371 fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x02000060>,
372 <IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x02000060>,
373 <IMX8QXP_ADC_IN2_ADMA_ADC_IN2 0x02000060>,
374 <IMX8QXP_ADC_IN3_ADMA_ADC_IN3 0x02000060>;
375 };
376
377 pinctrl_admapwm: admapwmgrp {
378 fsl,pins = <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000021>;
379 };
380
381 pinctrl_bl_lvds: bllvdsgrp {
382 fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 0x00000021>;
383 };
384
385 pinctrl_can0: can0grp {
386 fsl,pins = <IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX 0x00000021>,
387 <IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX 0x00000021>;
388 };
389
390 pinctrl_can1: can1grp {
391 fsl,pins = <IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021>,
392 <IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021>;
393 };
394
395 pinctrl_ethphy0: ethphy0grp {
396 fsl,pins = <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x00000040>,
397 <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x00000040>;
398 };
399
400 pinctrl_ethphy3: ethphy3grp {
401 fsl,pins = <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x00000040>,
402 <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x00000040>;
403 };
404
405 pinctrl_fec1: fec1grp {
406 fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000041>,
407 <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000041>,
408 <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000040>,
409 <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000040>,
410 <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000040>,
411 <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000040>,
412 <IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000040>,
413 <IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000040>,
414 <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000040>,
415 <IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000040>,
416 <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000040>,
417 <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000040>,
418 <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000040>,
419 <IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000040>;
420 };
421
422 pinctrl_fec2: fec2grp {
423 fsl,pins = <IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000040>,
424 <IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000040>,
425 <IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000040>,
426 <IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000040>,
427 <IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000040>,
428 <IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000040>,
429 <IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000040>,
430 <IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000040>,
431 <IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000040>,
432 <IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000040>,
433 <IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000040>,
434 <IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000040>;
435 };
436
437 pinctrl_gpiobuttons: gpiobuttonsgrp {
438 fsl,pins = <IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 0x00000020>,
439 <IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 0x00000020>;
440 };
441
442 pinctrl_lpi2c2: lpi2c2grp {
443 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL 0x06000021>,
444 <IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA 0x06000021>;
445 };
446
447 pinctrl_lpi2c2gpio: lpi2c2gpiogrp {
448 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021>,
449 <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x06000021>;
450 };
451
452 pinctrl_lpuart1: lpuart1grp {
453 fsl,pins = <IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020>,
454 <IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020>;
455 };
456
457 pinctrl_lpuart3: lpuart3grp {
458 fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>,
459 <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>;
460 };
461
462 pinctrl_lsgpio3: lsgpio3grp {
463 fsl,pins = <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000021>;
464 };
465
466 pinctrl_pca9538: pca9538grp {
467 fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000020>;
468 };
469
470 pinctrl_pcieb: pcieagrp {
471 fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>,
472 <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>,
473 <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>;
474 };
475
476 pinctrl_reg_pcie_1v5: regpcie1v5grp {
477 fsl,pins = <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x00000021>;
478 };
479
480 pinctrl_reg_pcie_3v3: regpcie3v3grp {
481 fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000021>;
482 };
483
484 pinctrl_sai1: sai1grp {
485 fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x06000041>,
486 <IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000041>,
487 <IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000041>,
488 <IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000041>,
489 <IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000041>;
490 };
491
492 pinctrl_spi1: spi1grp {
493 fsl,pins = <IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI 0x00000041>,
494 <IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO 0x00000041>,
495 <IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK 0x00000041>,
496 <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x00000021>,
497 <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x00000021>;
498 };
499
500 pinctrl_spi2: spi2grp {
501 fsl,pins = <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x00000041>,
502 <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x00000041>,
503 <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x00000041>,
504 <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x00000021>;
505 };
506
507 pinctrl_spi3: spi3grp {
508 fsl,pins = <IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK 0x00000041>,
509 <IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI 0x00000041>,
510 <IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO 0x00000041>,
511 <IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 0x00000021>,
512 <IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 0x00000021>;
513 };
514
515 pinctrl_usbotg1: usbotg1grp {
516 fsl,pins = <IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>,
517 <IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC 0x00000021>;
518 };
519
520 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
521 fsl,pins = <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021>,
522 <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021>;
523 };
524
525 pinctrl_usdhc2: usdhc2grp {
526 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>,
527 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>,
528 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>,
529 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>,
530 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>,
531 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>,
532 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
533 };
534
535 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
536 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
537 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
538 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
539 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
540 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
541 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
542 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>;
543 };
544
545 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
546 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
547 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
548 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
549 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
550 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
551 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
552 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>;
553 };
554};