Blame - src/arm64/freescale/imx8ulp-pinfunc.h - filogic/uboot

Tom Rini

53633a8

2024-02-29 12:33:36 -0500

[diff] [blame]

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/* SPDX-License-Identifier: GPL-2.0+ OR MIT */

/*

*/

#ifndef __DTS_IMX8ULP_PINFUNC_H

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#define __DTS_IMX8ULP_PINFUNC_H

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/*

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* The pin function ID is a tuple of

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* <mux_reg input_reg mux_mode input_val>

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*/

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#define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1

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#define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1

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#define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0

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#define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD1__PTD1 0x0004 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1

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#define MX8ULP_PAD_PTD1__SDHC0_CMD 0x0004 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7 0x0004 0x0970 0x9 0x1

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#define MX8ULP_PAD_PTD1__EPDC0_SDCLK 0x0004 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD1__DPI0_PCLK 0x0004 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_1 0x0004 0x0000 0xd 0x0

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#define MX8ULP_PAD_PTD1__DEBUG_MUX0_1 0x0004 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD1__DEBUG_MUX1_1 0x0004 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD2__PTD2 0x0008 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1

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#define MX8ULP_PAD_PTD2__SDHC0_CLK 0x0008 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6 0x0008 0x096C 0x9 0x1

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#define MX8ULP_PAD_PTD2__EPDC0_SDLE 0x0008 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD2__DPI0_HSYNC 0x0008 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_2 0x0008 0x0000 0xd 0x0

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#define MX8ULP_PAD_PTD2__DEBUG_MUX0_2 0x0008 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD2__DEBUG_MUX1_2 0x0008 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD3__PTD3 0x000C 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD3__I2S6_RXD1 0x000C 0x0B38 0x7 0x1

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#define MX8ULP_PAD_PTD3__SDHC0_D7 0x000C 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA5 0x000C 0x0968 0x9 0x1

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#define MX8ULP_PAD_PTD3__EPDC0_GDSP 0x000C 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD3__DPI0_VSYNC 0x000C 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_3 0x000C 0x0000 0xd 0x0

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#define MX8ULP_PAD_PTD3__DEBUG_MUX0_3 0x000C 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD3__DEBUG_MUX1_3 0x000C 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD4__PTD4 0x0010 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3 0x0010 0x0B14 0x4 0x1

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#define MX8ULP_PAD_PTD4__SDHC0_VS 0x0010 0x0000 0x5 0x0

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#define MX8ULP_PAD_PTD4__TPM8_CH5 0x0010 0x0B2C 0x6 0x1

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#define MX8ULP_PAD_PTD4__I2S6_MCLK 0x0010 0x0000 0x7 0x0

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#define MX8ULP_PAD_PTD4__SDHC0_D6 0x0010 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA4 0x0010 0x0964 0x9 0x1

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#define MX8ULP_PAD_PTD4__EPDC0_SDCE0 0x0010 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD4__DPI0_DE 0x0010 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD4__LP_APD_DBG_MUX_4 0x0010 0x0000 0xd 0x0

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#define MX8ULP_PAD_PTD4__DEBUG_MUX0_4 0x0010 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD4__DEBUG_MUX1_4 0x0010 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD5__PTD5 0x0014 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD5__SDHC0_CD 0x0014 0x0000 0x5 0x0

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#define MX8ULP_PAD_PTD5__TPM8_CH4 0x0014 0x0B28 0x6 0x1

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#define MX8ULP_PAD_PTD5__I2S6_TX_BCLK 0x0014 0x0B4C 0x7 0x1

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#define MX8ULP_PAD_PTD5__SDHC0_D5 0x0014 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SS0_B 0x0014 0x0000 0x9 0x0

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#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SCLK_B 0x0014 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD5__EPDC0_D0 0x0014 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD5__DPI0_D0 0x0014 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD5__LP_APD_DBG_MUX_5 0x0014 0x0000 0xd 0x0

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#define MX8ULP_PAD_PTD5__DEBUG_MUX0_5 0x0014 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD5__DEBUG_MUX1_5 0x0014 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD6__PTD6 0x0018 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD6__SDHC0_WP 0x0018 0x0000 0x5 0x0

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#define MX8ULP_PAD_PTD6__TPM8_CH3 0x0018 0x0B24 0x6 0x1

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#define MX8ULP_PAD_PTD6__I2S6_TX_FS 0x0018 0x0B50 0x7 0x1

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#define MX8ULP_PAD_PTD6__SDHC0_D4 0x0018 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD6__FLEXSPI2_B_SCLK 0x0018 0x0978 0x9 0x1

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#define MX8ULP_PAD_PTD6__EPDC0_D1 0x0018 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD6__DPI0_D1 0x0018 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD6__LP_APD_DBG_MUX_6 0x0018 0x0000 0xd 0x0

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#define MX8ULP_PAD_PTD6__DEBUG_MUX0_6 0x0018 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD6__DEBUG_MUX1_6 0x0018 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD7__PTD7 0x001C 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD7__TPM8_CH2 0x001C 0x0B20 0x6 0x1

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#define MX8ULP_PAD_PTD7__I2S6_TXD0 0x001C 0x0000 0x7 0x0

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#define MX8ULP_PAD_PTD7__SDHC0_D3 0x001C 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD7__FLEXSPI2_B_DATA3 0x001C 0x0960 0x9 0x1

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#define MX8ULP_PAD_PTD7__EPDC0_D2 0x001C 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD7__DPI0_D2 0x001C 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD7__LP_APD_DBG_MUX_7 0x001C 0x0000 0xd 0x0

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#define MX8ULP_PAD_PTD7__DEBUG_MUX0_7 0x001C 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD7__DEBUG_MUX1_7 0x001C 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD8__PTD8 0x0020 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD8__TPM8_CH1 0x0020 0x0B1C 0x6 0x1

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#define MX8ULP_PAD_PTD8__I2S6_TXD1 0x0020 0x0000 0x7 0x0

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#define MX8ULP_PAD_PTD8__SDHC0_D2 0x0020 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD8__FLEXSPI2_B_DATA2 0x0020 0x095C 0x9 0x1

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#define MX8ULP_PAD_PTD8__EPDC0_D3 0x0020 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD8__DPI0_D3 0x0020 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD8__LP_APD_DBG_MUX_8 0x0020 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD8__DEBUG_MUX1_8 0x0020 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD9__PTD9 0x0024 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD9__TPM8_CLKIN 0x0024 0x0B30 0x6 0x1

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#define MX8ULP_PAD_PTD9__I2S6_TXD2 0x0024 0x0000 0x7 0x0

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#define MX8ULP_PAD_PTD9__SDHC0_D1 0x0024 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD9__FLEXSPI2_B_DATA1 0x0024 0x0958 0x9 0x1

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#define MX8ULP_PAD_PTD9__EPDC0_D4 0x0024 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD9__DPI0_D4 0x0024 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD9__LP_APD_DBG_MUX_9 0x0024 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD9__DEBUG_MUX1_9 0x0024 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD10__PTD10 0x0028 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD10__TPM8_CH0 0x0028 0x0B18 0x6 0x1

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#define MX8ULP_PAD_PTD10__I2S6_TXD3 0x0028 0x0000 0x7 0x0

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#define MX8ULP_PAD_PTD10__SDHC0_D0 0x0028 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD10__FLEXSPI2_B_DATA0 0x0028 0x0954 0x9 0x1

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#define MX8ULP_PAD_PTD10__EPDC0_D5 0x0028 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD10__DPI0_D5 0x0028 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD10__LP_APD_DBG_MUX_10 0x0028 0x0000 0xe 0x0

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#define MX8ULP_PAD_PTD10__DEBUG_MUX1_10 0x0028 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD11__PTD11 0x002C 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD11__TPM8_CH5 0x002C 0x0B2C 0x6 0x2

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#define MX8ULP_PAD_PTD11__I2S6_RXD2 0x002C 0x0B3C 0x7 0x1

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#define MX8ULP_PAD_PTD11__SDHC0_DQS 0x002C 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD11__FLEXSPI2_B_SS0_B 0x002C 0x0000 0x9 0x0

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#define MX8ULP_PAD_PTD11__FLEXSPI2_A_SS1_B 0x002C 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD11__EPDC0_D6 0x002C 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD11__DPI0_D6 0x002C 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD11__LP_APD_DBG_MUX_11 0x002C 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD12__PTD12 0x0030 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD12__USB0_ID 0x0030 0x0AC8 0x5 0x1

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#define MX8ULP_PAD_PTD12__SDHC2_D3 0x0030 0x0AA4 0x6 0x1

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#define MX8ULP_PAD_PTD12__I2S7_RX_BCLK 0x0030 0x0B64 0x7 0x1

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#define MX8ULP_PAD_PTD12__SDHC1_DQS 0x0030 0x0A84 0x8 0x1

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#define MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x0030 0x0000 0x9 0x0

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#define MX8ULP_PAD_PTD12__FLEXSPI2_B_SS1_B 0x0030 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD12__EPDC0_D7 0x0030 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD12__DPI0_D7 0x0030 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD12__LP_APD_DBG_MUX_12 0x0030 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD13__PTD13 0x0034 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD13__SPDIF_IN3 0x0034 0x0B80 0x4 0x1

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#define MX8ULP_PAD_PTD13__USB0_PWR 0x0034 0x0000 0x5 0x0

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#define MX8ULP_PAD_PTD13__SDHC2_D2 0x0034 0x0AA0 0x6 0x1

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#define MX8ULP_PAD_PTD13__I2S7_RX_FS 0x0034 0x0B68 0x7 0x1

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#define MX8ULP_PAD_PTD13__SDHC1_RESET_B 0x0034 0x0000 0x8 0x0

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#define MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x0034 0x0000 0x9 0x0

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#define MX8ULP_PAD_PTD13__CLKOUT2 0x0034 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD13__EPDC0_D8 0x0034 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD13__DPI0_D8 0x0034 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD13__CLKOUT1 0x0034 0x0000 0xd 0x0

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#define MX8ULP_PAD_PTD13__LP_APD_DBG_MUX_13 0x0034 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD14__PTD14 0x0038 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD14__SPDIF_OUT3 0x0038 0x0000 0x4 0x0

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#define MX8ULP_PAD_PTD14__USB0_OC 0x0038 0x0AC0 0x5 0x1

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#define MX8ULP_PAD_PTD14__SDHC2_D1 0x0038 0x0A9C 0x6 0x1

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#define MX8ULP_PAD_PTD14__I2S7_RXD0 0x0038 0x0B54 0x7 0x1

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#define MX8ULP_PAD_PTD14__SDHC1_D7 0x0038 0x0A80 0x8 0x1

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#define MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x0038 0x0000 0x9 0x0

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#define MX8ULP_PAD_PTD14__TRACE0_D7 0x0038 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD14__EPDC0_D9 0x0038 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD14__DPI0_D9 0x0038 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD14__LP_APD_DBG_MUX_14 0x0038 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD15__PTD15 0x003C 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD15__SPDIF_IN2 0x003C 0x0B7C 0x4 0x1

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#define MX8ULP_PAD_PTD15__SDHC1_VS 0x003C 0x0000 0x5 0x0

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#define MX8ULP_PAD_PTD15__SDHC2_D0 0x003C 0x0A98 0x6 0x1

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#define MX8ULP_PAD_PTD15__I2S7_TX_BCLK 0x003C 0x0B6C 0x7 0x1

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#define MX8ULP_PAD_PTD15__SDHC1_D6 0x003C 0x0A7C 0x8 0x1

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#define MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x003C 0x0000 0x9 0x0

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#define MX8ULP_PAD_PTD15__TRACE0_D6 0x003C 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD15__EPDC0_D10 0x003C 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD15__DPI0_D10 0x003C 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD15__LP_APD_DBG_MUX_15 0x003C 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD16__PTD16 0x0040 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD16__FXIO1_D31 0x0040 0x08A0 0x2 0x1

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#define MX8ULP_PAD_PTD16__LPSPI4_PCS1 0x0040 0x08F8 0x3 0x1

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#define MX8ULP_PAD_PTD16__SPDIF_OUT2 0x0040 0x0000 0x4 0x0

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#define MX8ULP_PAD_PTD16__SDHC1_CD 0x0040 0x0A58 0x5 0x1

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#define MX8ULP_PAD_PTD16__SDHC2_CLK 0x0040 0x0A90 0x6 0x1

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#define MX8ULP_PAD_PTD16__I2S7_TX_FS 0x0040 0x0B70 0x7 0x1

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#define MX8ULP_PAD_PTD16__SDHC1_D5 0x0040 0x0A78 0x8 0x1

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#define MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x0040 0x0000 0x9 0x0

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#define MX8ULP_PAD_PTD16__TRACE0_D5 0x0040 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD16__EPDC0_D11 0x0040 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD16__DPI0_D11 0x0040 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD16__LP_APD_DBG_MUX_16 0x0040 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD17__PTD17 0x0044 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD17__FXIO1_D30 0x0044 0x089C 0x2 0x1

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#define MX8ULP_PAD_PTD17__LPSPI4_PCS2 0x0044 0x08FC 0x3 0x1

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#define MX8ULP_PAD_PTD17__EXT_AUD_MCLK3 0x0044 0x0B14 0x4 0x2

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#define MX8ULP_PAD_PTD17__SDHC1_WP 0x0044 0x0A88 0x5 0x1

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#define MX8ULP_PAD_PTD17__SDHC2_CMD 0x0044 0x0A94 0x6 0x1

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#define MX8ULP_PAD_PTD17__I2S7_TXD0 0x0044 0x0000 0x7 0x0

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#define MX8ULP_PAD_PTD17__SDHC1_D4 0x0044 0x0A74 0x8 0x1

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#define MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x0044 0x0000 0x9 0x0

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#define MX8ULP_PAD_PTD17__TRACE0_D4 0x0044 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD17__EPDC0_D12 0x0044 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD17__DPI0_D12 0x0044 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD17__LP_APD_DBG_MUX_17 0x0044 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD18__PTD18 0x0048 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD18__FXIO1_D29 0x0048 0x0894 0x2 0x1

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#define MX8ULP_PAD_PTD18__LPSPI4_PCS3 0x0048 0x0900 0x3 0x1

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#define MX8ULP_PAD_PTD18__SPDIF_CLK 0x0048 0x0000 0x4 0x0

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#define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3 0x0048 0x0B14 0x5 0x3

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#define MX8ULP_PAD_PTD18__TPM8_CH0 0x0048 0x0B18 0x6 0x2

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#define MX8ULP_PAD_PTD18__I2S7_MCLK 0x0048 0x0000 0x7 0x0

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#define MX8ULP_PAD_PTD18__SDHC1_D3 0x0048 0x0A70 0x8 0x1

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#define MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x0048 0x0000 0x9 0x0

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#define MX8ULP_PAD_PTD18__TRACE0_D3 0x0048 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD18__EPDC0_D13 0x0048 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD18__DPI0_D13 0x0048 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD18__LP_APD_DBG_MUX_18 0x0048 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD19__PTD19 0x004C 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD19__FXIO1_D28 0x004C 0x0890 0x2 0x1

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#define MX8ULP_PAD_PTD19__SPDIF_IN0 0x004C 0x0B74 0x4 0x1

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#define MX8ULP_PAD_PTD19__TPM8_CH1 0x004C 0x0B1C 0x6 0x2

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#define MX8ULP_PAD_PTD19__I2S6_RXD3 0x004C 0x0B40 0x7 0x1

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#define MX8ULP_PAD_PTD19__SDHC1_D2 0x004C 0x0A6C 0x8 0x1

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#define MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x004C 0x0000 0x9 0x0

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#define MX8ULP_PAD_PTD19__TRACE0_D2 0x004C 0x0000 0xa 0x0

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#define MX8ULP_PAD_PTD19__EPDC0_D14 0x004C 0x0000 0xb 0x0

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#define MX8ULP_PAD_PTD19__DPI0_D14 0x004C 0x0000 0xc 0x0

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#define MX8ULP_PAD_PTD19__LP_APD_DBG_MUX_19 0x004C 0x0000 0xf 0x0

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#define MX8ULP_PAD_PTD20__PTD20 0x0050 0x0000 0x1 0x0

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#define MX8ULP_PAD_PTD20__FXIO1_D27 0x0050 0x088C 0x2 0x1

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#define MX8ULP_PAD_PTD20__LPSPI4_SIN 0x0050 0x0908 0x3 0x1

228

#define MX8ULP_PAD_PTD20__SPDIF_OUT0 0x0050 0x0000 0x4 0x0

229

#define MX8ULP_PAD_PTD20__TPM8_CLKIN 0x0050 0x0B30 0x6 0x2

230

#define MX8ULP_PAD_PTD20__I2S7_RXD1 0x0050 0x0B58 0x7 0x1

231

#define MX8ULP_PAD_PTD20__SDHC1_D1 0x0050 0x0A68 0x8 0x1

232

#define MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x0050 0x0000 0x9 0x0

233

#define MX8ULP_PAD_PTD20__TRACE0_D1 0x0050 0x0000 0xa 0x0

234

#define MX8ULP_PAD_PTD20__EPDC0_D15 0x0050 0x0000 0xb 0x0

235

#define MX8ULP_PAD_PTD20__DPI0_D15 0x0050 0x0000 0xc 0x0

236

#define MX8ULP_PAD_PTD20__LP_APD_DBG_MUX_20 0x0050 0x0000 0xf 0x0

237

#define MX8ULP_PAD_PTD21__PTD21 0x0054 0x0000 0x1 0x0

238

#define MX8ULP_PAD_PTD21__FXIO1_D26 0x0054 0x0888 0x2 0x1

239

#define MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x0054 0x090C 0x3 0x1

240

#define MX8ULP_PAD_PTD21__SPDIF_IN1 0x0054 0x0B78 0x4 0x1

241

#define MX8ULP_PAD_PTD21__USB1_PWR 0x0054 0x0000 0x5 0x0

242

#define MX8ULP_PAD_PTD21__TPM8_CH2 0x0054 0x0B20 0x6 0x2

243

#define MX8ULP_PAD_PTD21__I2S7_TXD1 0x0054 0x0000 0x7 0x0

244

#define MX8ULP_PAD_PTD21__SDHC1_D0 0x0054 0x0A64 0x8 0x1

245

#define MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x0054 0x0000 0x9 0x0

246

#define MX8ULP_PAD_PTD21__TRACE0_D0 0x0054 0x0000 0xa 0x0

247

#define MX8ULP_PAD_PTD21__DPI0_D16 0x0054 0x0000 0xc 0x0

248

#define MX8ULP_PAD_PTD21__WDOG5_RST 0x0054 0x0000 0xd 0x0

249

#define MX8ULP_PAD_PTD21__LP_APD_DBG_MUX_21 0x0054 0x0000 0xf 0x0

250

#define MX8ULP_PAD_PTD22__PTD22 0x0058 0x0000 0x1 0x0

251

#define MX8ULP_PAD_PTD22__FXIO1_D25 0x0058 0x0884 0x2 0x1

252

#define MX8ULP_PAD_PTD22__LPSPI4_SCK 0x0058 0x0904 0x3 0x1

253

#define MX8ULP_PAD_PTD22__SPDIF_OUT1 0x0058 0x0000 0x4 0x0

254

#define MX8ULP_PAD_PTD22__USB1_OC 0x0058 0x0AC4 0x5 0x1

255

#define MX8ULP_PAD_PTD22__TPM8_CH3 0x0058 0x0B24 0x6 0x2

256

#define MX8ULP_PAD_PTD22__I2S7_TXD2 0x0058 0x0000 0x7 0x0

257

#define MX8ULP_PAD_PTD22__SDHC1_CLK 0x0058 0x0A5C 0x8 0x1

258

#define MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x0058 0x0000 0x9 0x0

259

#define MX8ULP_PAD_PTD22__TRACE0_CLKOUT 0x0058 0x0000 0xa 0x0

260

#define MX8ULP_PAD_PTD22__DPI0_D17 0x0058 0x0000 0xc 0x0

261

#define MX8ULP_PAD_PTD22__LP_APD_DBG_MUX_22 0x0058 0x0000 0xf 0x0

262

#define MX8ULP_PAD_PTD23__PTD23 0x005C 0x0000 0x1 0x0

263

#define MX8ULP_PAD_PTD23__FXIO1_D24 0x005C 0x0880 0x2 0x1

264

#define MX8ULP_PAD_PTD23__LPSPI4_PCS0 0x005C 0x08F4 0x3 0x1

265

#define MX8ULP_PAD_PTD23__USB1_ID 0x005C 0x0ACC 0x5 0x1

266

#define MX8ULP_PAD_PTD23__TPM8_CH4 0x005C 0x0B28 0x6 0x2

267

#define MX8ULP_PAD_PTD23__I2S7_TXD3 0x005C 0x0000 0x7 0x0

268

#define MX8ULP_PAD_PTD23__SDHC1_CMD 0x005C 0x0A60 0x8 0x1

269

#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SS0_B 0x005C 0x0000 0x9 0x0

270

#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SCLK_B 0x005C 0x0000 0xa 0x0

271

#define MX8ULP_PAD_PTD23__DPI0_D18 0x005C 0x0000 0xc 0x0

272

#define MX8ULP_PAD_PTD23__LP_APD_DBG_MUX_23 0x005C 0x0000 0xf 0x0

273

#define MX8ULP_PAD_PTE0__PTE0 0x0080 0x0000 0x1 0x0

274

#define MX8ULP_PAD_PTE0__FXIO1_D23 0x0080 0x087C 0x2 0x1

275

#define MX8ULP_PAD_PTE0__SPDIF_IN3 0x0080 0x0B80 0x3 0x2

276

#define MX8ULP_PAD_PTE0__LPUART4_CTS_B 0x0080 0x08DC 0x4 0x1

277

#define MX8ULP_PAD_PTE0__LPI2C4_SCL 0x0080 0x08C8 0x5 0x1

278

#define MX8ULP_PAD_PTE0__TPM8_CLKIN 0x0080 0x0B30 0x6 0x3

279

#define MX8ULP_PAD_PTE0__I2S7_RXD2 0x0080 0x0B5C 0x7 0x1

280

#define MX8ULP_PAD_PTE0__SDHC2_D1 0x0080 0x0A9C 0x8 0x2

281

#define MX8ULP_PAD_PTE0__FLEXSPI2_B_DQS 0x0080 0x0974 0x9 0x2

282

#define MX8ULP_PAD_PTE0__ENET0_CRS 0x0080 0x0AE8 0xa 0x1

283

#define MX8ULP_PAD_PTE0__DBI0_WRX 0x0080 0x0000 0xb 0x0

284

#define MX8ULP_PAD_PTE0__DPI0_D19 0x0080 0x0000 0xc 0x0

285

#define MX8ULP_PAD_PTE0__WUU1_P0 0x0080 0x0000 0xd 0x0

286

#define MX8ULP_PAD_PTE0__DEBUG_MUX0_8 0x0080 0x0000 0xe 0x0

287

#define MX8ULP_PAD_PTE0__DEBUG_MUX1_11 0x0080 0x0000 0xf 0x0

288

#define MX8ULP_PAD_PTE1__PTE1 0x0084 0x0000 0x1 0x0

289

#define MX8ULP_PAD_PTE1__FXIO1_D22 0x0084 0x0878 0x2 0x1

290

#define MX8ULP_PAD_PTE1__SPDIF_OUT3 0x0084 0x0000 0x3 0x0

291

#define MX8ULP_PAD_PTE1__LPUART4_RTS_B 0x0084 0x0000 0x4 0x0

292

#define MX8ULP_PAD_PTE1__LPI2C4_SDA 0x0084 0x08CC 0x5 0x1

293

#define MX8ULP_PAD_PTE1__TPM8_CH0 0x0084 0x0B18 0x6 0x3

294

#define MX8ULP_PAD_PTE1__I2S7_RXD3 0x0084 0x0B60 0x7 0x1

295

#define MX8ULP_PAD_PTE1__SDHC2_D0 0x0084 0x0A98 0x8 0x2

296

#define MX8ULP_PAD_PTE1__FLEXSPI2_B_DATA7 0x0084 0x0970 0x9 0x2

297

#define MX8ULP_PAD_PTE1__ENET0_COL 0x0084 0x0AE4 0xa 0x1

298

#define MX8ULP_PAD_PTE1__DBI0_CSX 0x0084 0x0000 0xb 0x0

299

#define MX8ULP_PAD_PTE1__DPI0_D20 0x0084 0x0000 0xc 0x0

300

#define MX8ULP_PAD_PTE1__WUU1_P1 0x0084 0x0000 0xd 0x0

301

#define MX8ULP_PAD_PTE1__DEBUG_MUX0_9 0x0084 0x0000 0xe 0x0

302

#define MX8ULP_PAD_PTE1__DEBUG_MUX1_12 0x0084 0x0000 0xf 0x0

303

#define MX8ULP_PAD_PTE2__PTE2 0x0088 0x0000 0x1 0x0

304

#define MX8ULP_PAD_PTE2__FXIO1_D21 0x0088 0x0874 0x2 0x1

305

#define MX8ULP_PAD_PTE2__SPDIF_IN2 0x0088 0x0B7C 0x3 0x2

306

#define MX8ULP_PAD_PTE2__LPUART4_TX 0x0088 0x08E4 0x4 0x1

307

#define MX8ULP_PAD_PTE2__LPI2C4_HREQ 0x0088 0x08C4 0x5 0x1

308

#define MX8ULP_PAD_PTE2__TPM8_CH1 0x0088 0x0B1C 0x6 0x3

309

#define MX8ULP_PAD_PTE2__EXT_AUD_MCLK3 0x0088 0x0B14 0x7 0x4

310

#define MX8ULP_PAD_PTE2__SDHC2_CLK 0x0088 0x0A90 0x8 0x2

311

#define MX8ULP_PAD_PTE2__FLEXSPI2_B_DATA6 0x0088 0x096C 0x9 0x2

312

#define MX8ULP_PAD_PTE2__ENET0_TXER 0x0088 0x0000 0xa 0x0

313

#define MX8ULP_PAD_PTE2__DBI0_DCX 0x0088 0x0000 0xb 0x0

314

#define MX8ULP_PAD_PTE2__DPI0_D21 0x0088 0x0000 0xc 0x0

315

#define MX8ULP_PAD_PTE2__LP_HV_DBG_MUX_0 0x0088 0x0000 0xd 0x0

316

#define MX8ULP_PAD_PTE2__DEBUG_MUX0_10 0x0088 0x0000 0xe 0x0

317

#define MX8ULP_PAD_PTE2__DEBUG_MUX1_13 0x0088 0x0000 0xf 0x0

318

#define MX8ULP_PAD_PTE3__PTE3 0x008C 0x0000 0x1 0x0

319

#define MX8ULP_PAD_PTE3__FXIO1_D20 0x008C 0x0870 0x2 0x1

320

#define MX8ULP_PAD_PTE3__SPDIF_OUT2 0x008C 0x0000 0x3 0x0

321

#define MX8ULP_PAD_PTE3__LPUART4_RX 0x008C 0x08E0 0x4 0x1

322

#define MX8ULP_PAD_PTE3__TPM8_CH2 0x008C 0x0B20 0x6 0x3

323

#define MX8ULP_PAD_PTE3__I2S6_MCLK 0x008C 0x0000 0x7 0x0

324

#define MX8ULP_PAD_PTE3__SDHC2_CMD 0x008C 0x0A94 0x8 0x2

325

#define MX8ULP_PAD_PTE3__FLEXSPI2_B_DATA5 0x008C 0x0968 0x9 0x2

326

#define MX8ULP_PAD_PTE3__ENET0_TXCLK 0x008C 0x0B10 0xa 0x1

327

#define MX8ULP_PAD_PTE3__DBI0_RWX 0x008C 0x0000 0xb 0x0

328

#define MX8ULP_PAD_PTE3__DPI0_D22 0x008C 0x0000 0xc 0x0

329

#define MX8ULP_PAD_PTE3__WUU1_P2 0x008C 0x0000 0xd 0x0

330

#define MX8ULP_PAD_PTE3__DEBUG_MUX0_11 0x008C 0x0000 0xe 0x0

331

#define MX8ULP_PAD_PTE3__DEBUG_MUX1_14 0x008C 0x0000 0xf 0x0

332

#define MX8ULP_PAD_PTE4__PTE4 0x0090 0x0000 0x1 0x0

333

#define MX8ULP_PAD_PTE4__FXIO1_D19 0x0090 0x0868 0x2 0x1

334

#define MX8ULP_PAD_PTE4__SPDIF_CLK 0x0090 0x0000 0x3 0x0

335

#define MX8ULP_PAD_PTE4__LPUART5_CTS_B 0x0090 0x08E8 0x4 0x1

336

#define MX8ULP_PAD_PTE4__LPI2C5_SCL 0x0090 0x08D4 0x5 0x1

337

#define MX8ULP_PAD_PTE4__TPM8_CH3 0x0090 0x0B24 0x6 0x3

338

#define MX8ULP_PAD_PTE4__I2S6_RX_BCLK 0x0090 0x0B44 0x7 0x2

339

#define MX8ULP_PAD_PTE4__SDHC2_D3 0x0090 0x0AA4 0x8 0x2

340

#define MX8ULP_PAD_PTE4__FLEXSPI2_B_DATA4 0x0090 0x0964 0x9 0x2

341

#define MX8ULP_PAD_PTE4__ENET0_TXD3 0x0090 0x0000 0xa 0x0

342

#define MX8ULP_PAD_PTE4__DBI0_E 0x0090 0x0000 0xb 0x0

343

#define MX8ULP_PAD_PTE4__DPI0_D23 0x0090 0x0000 0xc 0x0

344

#define MX8ULP_PAD_PTE4__WUU1_P3 0x0090 0x0000 0xd 0x0

345

#define MX8ULP_PAD_PTE4__DEBUG_MUX0_12 0x0090 0x0000 0xe 0x0

346

#define MX8ULP_PAD_PTE4__DEBUG_MUX1_15 0x0090 0x0000 0xf 0x0

347

#define MX8ULP_PAD_PTE5__PTE5 0x0094 0x0000 0x1 0x0

348

#define MX8ULP_PAD_PTE5__FXIO1_D18 0x0094 0x0864 0x2 0x1

349

#define MX8ULP_PAD_PTE5__SPDIF_IN0 0x0094 0x0B74 0x3 0x2

350

#define MX8ULP_PAD_PTE5__LPUART5_RTS_B 0x0094 0x0000 0x4 0x0

351

#define MX8ULP_PAD_PTE5__LPI2C5_SDA 0x0094 0x08D8 0x5 0x1

352

#define MX8ULP_PAD_PTE5__TPM8_CH4 0x0094 0x0B28 0x6 0x3

353

#define MX8ULP_PAD_PTE5__I2S6_RX_FS 0x0094 0x0B48 0x7 0x2

354

#define MX8ULP_PAD_PTE5__SDHC2_D2 0x0094 0x0AA0 0x8 0x2

355

#define MX8ULP_PAD_PTE5__FLEXSPI2_B_SS0_B 0x0094 0x0000 0x9 0x0

356

#define MX8ULP_PAD_PTE5__ENET0_TXD2 0x0094 0x0000 0xa 0x0

357

#define MX8ULP_PAD_PTE5__DBI0_D0 0x0094 0x0000 0xb 0x0

358

#define MX8ULP_PAD_PTE5__LP_HV_DBG_MUX_1 0x0094 0x0000 0xd 0x0

359

#define MX8ULP_PAD_PTE5__DEBUG_MUX0_13 0x0094 0x0000 0xe 0x0

360

#define MX8ULP_PAD_PTE5__DEBUG_MUX1_16 0x0094 0x0000 0xf 0x0

361

#define MX8ULP_PAD_PTE6__PTE6 0x0098 0x0000 0x1 0x0

362

#define MX8ULP_PAD_PTE6__FXIO1_D17 0x0098 0x0860 0x2 0x1

363

#define MX8ULP_PAD_PTE6__SPDIF_OUT0 0x0098 0x0000 0x3 0x0

364

#define MX8ULP_PAD_PTE6__LPUART5_TX 0x0098 0x08F0 0x4 0x1

365

#define MX8ULP_PAD_PTE6__LPI2C5_HREQ 0x0098 0x08D0 0x5 0x1

366

#define MX8ULP_PAD_PTE6__TPM8_CH5 0x0098 0x0B2C 0x6 0x3

367

#define MX8ULP_PAD_PTE6__I2S6_RXD0 0x0098 0x0B34 0x7 0x2

368

#define MX8ULP_PAD_PTE6__SDHC2_D4 0x0098 0x0AA8 0x8 0x1

369

#define MX8ULP_PAD_PTE6__FLEXSPI2_B_SCLK 0x0098 0x0978 0x9 0x2

370

#define MX8ULP_PAD_PTE6__ENET0_RXCLK 0x0098 0x0B0C 0xa 0x1

371

#define MX8ULP_PAD_PTE6__DBI0_D1 0x0098 0x0000 0xb 0x0

372

#define MX8ULP_PAD_PTE6__LP_HV_DBG_MUX_2 0x0098 0x0000 0xc 0x0

373

#define MX8ULP_PAD_PTE6__WDOG5_RST 0x0098 0x0000 0xd 0x0

374

#define MX8ULP_PAD_PTE6__DEBUG_MUX0_14 0x0098 0x0000 0xe 0x0

375

#define MX8ULP_PAD_PTE6__DEBUG_MUX1_17 0x0098 0x0000 0xf 0x0

376

#define MX8ULP_PAD_PTE7__PTE7 0x009C 0x0000 0x1 0x0

377

#define MX8ULP_PAD_PTE7__FXIO1_D16 0x009C 0x085C 0x2 0x1

378

#define MX8ULP_PAD_PTE7__SPDIF_IN1 0x009C 0x0B78 0x3 0x2

379

#define MX8ULP_PAD_PTE7__LPUART5_RX 0x009C 0x08EC 0x4 0x1

380

#define MX8ULP_PAD_PTE7__LPI2C6_HREQ 0x009C 0x09B4 0x5 0x1

381

#define MX8ULP_PAD_PTE7__TPM4_CLKIN 0x009C 0x081C 0x6 0x1

382

#define MX8ULP_PAD_PTE7__I2S6_RXD1 0x009C 0x0B38 0x7 0x2

383

#define MX8ULP_PAD_PTE7__SDHC2_D5 0x009C 0x0AAC 0x8 0x1

384

#define MX8ULP_PAD_PTE7__FLEXSPI2_B_DATA3 0x009C 0x0960 0x9 0x2

385

#define MX8ULP_PAD_PTE7__ENET0_RXD3 0x009C 0x0B04 0xa 0x1

386

#define MX8ULP_PAD_PTE7__DBI0_D2 0x009C 0x0000 0xb 0x0

387

#define MX8ULP_PAD_PTE7__EPDC0_BDR1 0x009C 0x0000 0xc 0x0

388

#define MX8ULP_PAD_PTE7__WUU1_P4 0x009C 0x0000 0xd 0x0

389

#define MX8ULP_PAD_PTE7__DEBUG_MUX0_15 0x009C 0x0000 0xe 0x0

390

#define MX8ULP_PAD_PTE7__DEBUG_MUX1_18 0x009C 0x0000 0xf 0x0

391

#define MX8ULP_PAD_PTE8__PTE8 0x00A0 0x0000 0x1 0x0

392

#define MX8ULP_PAD_PTE8__FXIO1_D15 0x00A0 0x0858 0x2 0x1

393

#define MX8ULP_PAD_PTE8__LPSPI4_PCS1 0x00A0 0x08F8 0x3 0x2

394

#define MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x00A0 0x09CC 0x4 0x1

395

#define MX8ULP_PAD_PTE8__LPI2C6_SCL 0x00A0 0x09B8 0x5 0x1

396

#define MX8ULP_PAD_PTE8__TPM4_CH0 0x00A0 0x0804 0x6 0x1

397

#define MX8ULP_PAD_PTE8__I2S6_RXD2 0x00A0 0x0B3C 0x7 0x2

398

#define MX8ULP_PAD_PTE8__SDHC2_D6 0x00A0 0x0AB0 0x8 0x1

399

#define MX8ULP_PAD_PTE8__FLEXSPI2_B_DATA2 0x00A0 0x095C 0x9 0x2

400

#define MX8ULP_PAD_PTE8__ENET0_RXD2 0x00A0 0x0B00 0xa 0x1

401

#define MX8ULP_PAD_PTE8__DBI0_D3 0x00A0 0x0000 0xb 0x0

402

#define MX8ULP_PAD_PTE8__EPDC0_BDR0 0x00A0 0x0000 0xc 0x0

403

#define MX8ULP_PAD_PTE8__LP_HV_DBG_MUX_3 0x00A0 0x0000 0xe 0x0

404

#define MX8ULP_PAD_PTE8__DEBUG_MUX1_19 0x00A0 0x0000 0xf 0x0

405

#define MX8ULP_PAD_PTE9__PTE9 0x00A4 0x0000 0x1 0x0

406

#define MX8ULP_PAD_PTE9__FXIO1_D14 0x00A4 0x0854 0x2 0x1

407

#define MX8ULP_PAD_PTE9__LPSPI4_PCS2 0x00A4 0x08FC 0x3 0x2

408

#define MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x00A4 0x0000 0x4 0x0

409

#define MX8ULP_PAD_PTE9__LPI2C6_SDA 0x00A4 0x09BC 0x5 0x1

410

#define MX8ULP_PAD_PTE9__TPM4_CH1 0x00A4 0x0808 0x6 0x1

411

#define MX8ULP_PAD_PTE9__I2S6_RXD3 0x00A4 0x0B40 0x7 0x2

412

#define MX8ULP_PAD_PTE9__SDHC2_D7 0x00A4 0x0AB4 0x8 0x1

413

#define MX8ULP_PAD_PTE9__FLEXSPI2_B_DATA1 0x00A4 0x0958 0x9 0x2

414

#define MX8ULP_PAD_PTE9__ENET0_1588_TMR3 0x00A4 0x0AE0 0xa 0x1

415

#define MX8ULP_PAD_PTE9__DBI0_D4 0x00A4 0x0000 0xb 0x0

416

#define MX8ULP_PAD_PTE9__EPDC0_VCOM1 0x00A4 0x0000 0xc 0x0

417

#define MX8ULP_PAD_PTE9__LP_HV_DBG_MUX_4 0x00A4 0x0000 0xe 0x0

418

#define MX8ULP_PAD_PTE9__DEBUG_MUX1_20 0x00A4 0x0000 0xf 0x0

419

#define MX8ULP_PAD_PTE10__PTE10 0x00A8 0x0000 0x1 0x0

420

#define MX8ULP_PAD_PTE10__FXIO1_D13 0x00A8 0x0850 0x2 0x1

421

#define MX8ULP_PAD_PTE10__LPSPI4_PCS3 0x00A8 0x0900 0x3 0x2

422

#define MX8ULP_PAD_PTE10__LPUART6_TX 0x00A8 0x09D4 0x4 0x1

423

#define MX8ULP_PAD_PTE10__I3C2_SCL 0x00A8 0x08BC 0x5 0x1

424

#define MX8ULP_PAD_PTE10__TPM4_CH2 0x00A8 0x080C 0x6 0x1

425

#define MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x00A8 0x0B4C 0x7 0x2

426

#define MX8ULP_PAD_PTE10__SDHC2_DQS 0x00A8 0x0AB8 0x8 0x1

427

#define MX8ULP_PAD_PTE10__FLEXSPI2_B_DATA0 0x00A8 0x0954 0x9 0x2

428

#define MX8ULP_PAD_PTE10__ENET0_1588_TMR2 0x00A8 0x0ADC 0xa 0x1

429

#define MX8ULP_PAD_PTE10__DBI0_D5 0x00A8 0x0000 0xb 0x0

430

#define MX8ULP_PAD_PTE10__EPDC0_VCOM0 0x00A8 0x0000 0xc 0x0

431

#define MX8ULP_PAD_PTE10__LP_HV_DBG_MUX_5 0x00A8 0x0000 0xe 0x0

432

#define MX8ULP_PAD_PTE10__DEBUG_MUX1_21 0x00A8 0x0000 0xf 0x0

433

#define MX8ULP_PAD_PTE11__PTE11 0x00AC 0x0000 0x1 0x0

434

#define MX8ULP_PAD_PTE11__FXIO1_D12 0x00AC 0x084C 0x2 0x1

435

#define MX8ULP_PAD_PTE11__SPDIF_OUT1 0x00AC 0x0000 0x3 0x0

436

#define MX8ULP_PAD_PTE11__LPUART6_RX 0x00AC 0x09D0 0x4 0x1

437

#define MX8ULP_PAD_PTE11__I3C2_SDA 0x00AC 0x08C0 0x5 0x1

438

#define MX8ULP_PAD_PTE11__TPM4_CH3 0x00AC 0x0810 0x6 0x1

439

#define MX8ULP_PAD_PTE11__I2S6_TX_FS 0x00AC 0x0B50 0x7 0x2

440

#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SCLK_B 0x00AC 0x0000 0x8 0x0

441

#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SS0_B 0x00AC 0x0000 0x9 0x0

442

#define MX8ULP_PAD_PTE11__ENET0_1588_TMR1 0x00AC 0x0AD8 0xa 0x1

443

#define MX8ULP_PAD_PTE11__DBI0_D6 0x00AC 0x0000 0xb 0x0

444

#define MX8ULP_PAD_PTE11__EPDC0_PWRCTRL0 0x00AC 0x0000 0xc 0x0

445

#define MX8ULP_PAD_PTE11__LP_HV_DBG_MUX_6 0x00AC 0x0000 0xf 0x0

446

#define MX8ULP_PAD_PTE12__PTE12 0x00B0 0x0000 0x1 0x0

447

#define MX8ULP_PAD_PTE12__FXIO1_D11 0x00B0 0x0848 0x2 0x1

448

#define MX8ULP_PAD_PTE12__LPSPI4_SIN 0x00B0 0x0908 0x3 0x2

449

#define MX8ULP_PAD_PTE12__LPUART7_CTS_B 0x00B0 0x09D8 0x4 0x1

450

#define MX8ULP_PAD_PTE12__LPI2C7_SCL 0x00B0 0x09C4 0x5 0x1

451

#define MX8ULP_PAD_PTE12__TPM4_CH4 0x00B0 0x0814 0x6 0x1

452

#define MX8ULP_PAD_PTE12__I2S6_TXD0 0x00B0 0x0000 0x7 0x0

453

#define MX8ULP_PAD_PTE12__SDHC2_RESET_B 0x00B0 0x0000 0x8 0x0

454

#define MX8ULP_PAD_PTE12__FLEXSPI2_B_SS1_B 0x00B0 0x0000 0x9 0x0

455

#define MX8ULP_PAD_PTE12__ENET0_1588_TMR0 0x00B0 0x0AD4 0xa 0x1

456

#define MX8ULP_PAD_PTE12__DBI0_D7 0x00B0 0x0000 0xb 0x0

457

#define MX8ULP_PAD_PTE12__EPDC0_PWRCTRL1 0x00B0 0x0000 0xc 0x0

458

#define MX8ULP_PAD_PTE12__WUU1_P5 0x00B0 0x0000 0xd 0x0

459

#define MX8ULP_PAD_PTE13__PTE13 0x00B4 0x0000 0x1 0x0

460

#define MX8ULP_PAD_PTE13__FXIO1_D10 0x00B4 0x0844 0x2 0x1

461

#define MX8ULP_PAD_PTE13__LPSPI4_SOUT 0x00B4 0x090C 0x3 0x2

462

#define MX8ULP_PAD_PTE13__LPUART7_RTS_B 0x00B4 0x0000 0x4 0x0

463

#define MX8ULP_PAD_PTE13__LPI2C7_SDA 0x00B4 0x09C8 0x5 0x1

464

#define MX8ULP_PAD_PTE13__TPM4_CH5 0x00B4 0x0818 0x6 0x1

465

#define MX8ULP_PAD_PTE13__I2S6_TXD1 0x00B4 0x0000 0x7 0x0

466

#define MX8ULP_PAD_PTE13__SDHC1_WP 0x00B4 0x0A88 0x8 0x2

467

#define MX8ULP_PAD_PTE13__ENET0_1588_CLKIN 0x00B4 0x0AD0 0xa 0x1

468

#define MX8ULP_PAD_PTE13__DBI0_D8 0x00B4 0x0000 0xb 0x0

469

#define MX8ULP_PAD_PTE13__EPDC0_PWRCTRL2 0x00B4 0x0000 0xc 0x0

470

#define MX8ULP_PAD_PTE13__LP_HV_DBG_MUX_7 0x00B4 0x0000 0xf 0x0

471

#define MX8ULP_PAD_PTE14__PTE14 0x00B8 0x0000 0x1 0x0

472

#define MX8ULP_PAD_PTE14__FXIO1_D9 0x00B8 0x08B8 0x2 0x1

473

#define MX8ULP_PAD_PTE14__LPSPI4_SCK 0x00B8 0x0904 0x3 0x2

474

#define MX8ULP_PAD_PTE14__LPUART7_TX 0x00B8 0x09E0 0x4 0x1

475

#define MX8ULP_PAD_PTE14__LPI2C7_HREQ 0x00B8 0x09C0 0x5 0x1

476

#define MX8ULP_PAD_PTE14__TPM5_CLKIN 0x00B8 0x0838 0x6 0x1

477

#define MX8ULP_PAD_PTE14__I2S6_TXD2 0x00B8 0x0000 0x7 0x0

478

#define MX8ULP_PAD_PTE14__SDHC1_CD 0x00B8 0x0A58 0x8 0x2

479

#define MX8ULP_PAD_PTE14__ENET0_MDIO 0x00B8 0x0AF0 0xa 0x1

480

#define MX8ULP_PAD_PTE14__DBI0_D9 0x00B8 0x0000 0xb 0x0

481

#define MX8ULP_PAD_PTE14__EPDC0_PWRCTRL3 0x00B8 0x0000 0xc 0x0

482

#define MX8ULP_PAD_PTE14__LP_HV_DBG_MUX_8 0x00B8 0x0000 0xf 0x0

483

#define MX8ULP_PAD_PTE15__PTE15 0x00BC 0x0000 0x1 0x0

484

#define MX8ULP_PAD_PTE15__FXIO1_D8 0x00BC 0x08B4 0x2 0x1

485

#define MX8ULP_PAD_PTE15__LPSPI4_PCS0 0x00BC 0x08F4 0x3 0x2

486

#define MX8ULP_PAD_PTE15__LPUART7_RX 0x00BC 0x09DC 0x4 0x1

487

#define MX8ULP_PAD_PTE15__I3C2_PUR 0x00BC 0x0000 0x5 0x0

488

#define MX8ULP_PAD_PTE15__TPM5_CH0 0x00BC 0x0820 0x6 0x1

489

#define MX8ULP_PAD_PTE15__I2S6_TXD3 0x00BC 0x0000 0x7 0x0

490

#define MX8ULP_PAD_PTE15__MQS1_LEFT 0x00BC 0x0000 0x8 0x0

491

#define MX8ULP_PAD_PTE15__ENET0_MDC 0x00BC 0x0000 0xa 0x0

492

#define MX8ULP_PAD_PTE15__DBI0_D10 0x00BC 0x0000 0xb 0x0

493

#define MX8ULP_PAD_PTE15__EPDC0_PWRCOM 0x00BC 0x0000 0xc 0x0

494

#define MX8ULP_PAD_PTE15__WUU1_P6 0x00BC 0x0000 0xd 0x0

495

#define MX8ULP_PAD_PTE16__PTE16 0x00C0 0x0000 0x1 0x0

496

#define MX8ULP_PAD_PTE16__FXIO1_D7 0x00C0 0x08B0 0x2 0x1

497

#define MX8ULP_PAD_PTE16__LPSPI5_PCS1 0x00C0 0x0914 0x3 0x1

498

#define MX8ULP_PAD_PTE16__LPUART4_CTS_B 0x00C0 0x08DC 0x4 0x2

499

#define MX8ULP_PAD_PTE16__LPI2C4_SCL 0x00C0 0x08C8 0x5 0x2

500

#define MX8ULP_PAD_PTE16__TPM5_CH1 0x00C0 0x0824 0x6 0x1

501

#define MX8ULP_PAD_PTE16__MQS1_LEFT 0x00C0 0x0000 0x7 0x0

502

#define MX8ULP_PAD_PTE16__MQS1_RIGHT 0x00C0 0x0000 0x8 0x0

503

#define MX8ULP_PAD_PTE16__USB0_ID 0x00C0 0x0AC8 0x9 0x2

504

#define MX8ULP_PAD_PTE16__ENET0_TXEN 0x00C0 0x0000 0xa 0x0

505

#define MX8ULP_PAD_PTE16__DBI0_D11 0x00C0 0x0000 0xb 0x0

506

#define MX8ULP_PAD_PTE16__EPDC0_PWRIRQ 0x00C0 0x0000 0xc 0x0

507

#define MX8ULP_PAD_PTE16__WDOG3_RST 0x00C0 0x0000 0xd 0x0

508

#define MX8ULP_PAD_PTE16__LP_HV_DBG_MUX_9 0x00C0 0x0000 0xf 0x0

509

#define MX8ULP_PAD_PTE17__PTE17 0x00C4 0x0000 0x1 0x0

510

#define MX8ULP_PAD_PTE17__FXIO1_D6 0x00C4 0x08AC 0x2 0x1

511

#define MX8ULP_PAD_PTE17__LPSPI5_PCS2 0x00C4 0x0918 0x3 0x1

512

#define MX8ULP_PAD_PTE17__LPUART4_RTS_B 0x00C4 0x0000 0x4 0x0

513

#define MX8ULP_PAD_PTE17__LPI2C4_SDA 0x00C4 0x08CC 0x5 0x2

514

#define MX8ULP_PAD_PTE17__MQS1_RIGHT 0x00C4 0x0000 0x7 0x0

515

#define MX8ULP_PAD_PTE17__SDHC1_VS 0x00C4 0x0000 0x8 0x0

516

#define MX8ULP_PAD_PTE17__USB0_PWR 0x00C4 0x0000 0x9 0x0

517

#define MX8ULP_PAD_PTE17__ENET0_RXER 0x00C4 0x0B08 0xa 0x1

518

#define MX8ULP_PAD_PTE17__DBI0_D12 0x00C4 0x0000 0xb 0x0

519

#define MX8ULP_PAD_PTE17__EPDC0_PWRSTAT 0x00C4 0x0000 0xc 0x0

520

#define MX8ULP_PAD_PTE17__LP_HV_DBG_MUX_10 0x00C4 0x0000 0xf 0x0

521

#define MX8ULP_PAD_PTE18__PTE18 0x00C8 0x0000 0x1 0x0

522

#define MX8ULP_PAD_PTE18__FXIO1_D5 0x00C8 0x08A8 0x2 0x1

523

#define MX8ULP_PAD_PTE18__LPSPI5_PCS3 0x00C8 0x091C 0x3 0x1

524

#define MX8ULP_PAD_PTE18__LPUART4_TX 0x00C8 0x08E4 0x4 0x2

525

#define MX8ULP_PAD_PTE18__LPI2C4_HREQ 0x00C8 0x08C4 0x5 0x2

526

#define MX8ULP_PAD_PTE18__I2S7_TX_BCLK 0x00C8 0x0B6C 0x7 0x2

527

#define MX8ULP_PAD_PTE18__USB0_OC 0x00C8 0x0AC0 0x9 0x2

528

#define MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x00C8 0x0AEC 0xa 0x1

529

#define MX8ULP_PAD_PTE18__DBI0_D13 0x00C8 0x0000 0xb 0x0

530

#define MX8ULP_PAD_PTE18__EPDC0_PWRWAKE 0x00C8 0x0000 0xc 0x0

531

#define MX8ULP_PAD_PTE18__LP_HV_DBG_MUX_11 0x00C8 0x0000 0xf 0x0

532

#define MX8ULP_PAD_PTE19__PTE19 0x00CC 0x0000 0x1 0x0

533

#define MX8ULP_PAD_PTE19__FXIO1_D4 0x00CC 0x08A4 0x2 0x1

534

#define MX8ULP_PAD_PTE19__LPUART4_RX 0x00CC 0x08E0 0x4 0x2

535

#define MX8ULP_PAD_PTE19__LPI2C5_HREQ 0x00CC 0x08D0 0x5 0x2

536

#define MX8ULP_PAD_PTE19__I3C2_PUR 0x00CC 0x0000 0x6 0x0

537

#define MX8ULP_PAD_PTE19__I2S7_TX_FS 0x00CC 0x0B70 0x7 0x2

538

#define MX8ULP_PAD_PTE19__USB1_PWR 0x00CC 0x0000 0x9 0x0

539

#define MX8ULP_PAD_PTE19__ENET0_REFCLK 0x00CC 0x0AF4 0xa 0x1

540

#define MX8ULP_PAD_PTE19__DBI0_D14 0x00CC 0x0000 0xb 0x0

541

#define MX8ULP_PAD_PTE19__EPDC0_GDCLK 0x00CC 0x0000 0xc 0x0

542

#define MX8ULP_PAD_PTE19__WUU1_P7 0x00CC 0x0000 0xd 0x0

543

#define MX8ULP_PAD_PTE20__PTE20 0x00D0 0x0000 0x1 0x0

544

#define MX8ULP_PAD_PTE20__FXIO1_D3 0x00D0 0x0898 0x2 0x1

545

#define MX8ULP_PAD_PTE20__LPSPI5_SIN 0x00D0 0x0924 0x3 0x1

546

#define MX8ULP_PAD_PTE20__LPUART5_CTS_B 0x00D0 0x08E8 0x4 0x2

547

#define MX8ULP_PAD_PTE20__LPI2C5_SCL 0x00D0 0x08D4 0x5 0x2

548

#define MX8ULP_PAD_PTE20__I2S7_TXD0 0x00D0 0x0000 0x7 0x0

549

#define MX8ULP_PAD_PTE20__USB1_OC 0x00D0 0x0AC4 0x9 0x2

550

#define MX8ULP_PAD_PTE20__ENET0_RXD1 0x00D0 0x0AFC 0xa 0x1

551

#define MX8ULP_PAD_PTE20__DBI0_D15 0x00D0 0x0000 0xb 0x0

552

#define MX8ULP_PAD_PTE20__EPDC0_GDOE 0x00D0 0x0000 0xc 0x0

553

#define MX8ULP_PAD_PTE20__LP_HV_DBG_MUX_12 0x00D0 0x0000 0xf 0x0

554

#define MX8ULP_PAD_PTE21__PTE21 0x00D4 0x0000 0x1 0x0

555

#define MX8ULP_PAD_PTE21__FXIO1_D2 0x00D4 0x086C 0x2 0x1

556

#define MX8ULP_PAD_PTE21__LPSPI5_SOUT 0x00D4 0x0928 0x3 0x1

557

#define MX8ULP_PAD_PTE21__LPUART5_RTS_B 0x00D4 0x0000 0x4 0x0

558

#define MX8ULP_PAD_PTE21__LPI2C5_SDA 0x00D4 0x08D8 0x5 0x2

559

#define MX8ULP_PAD_PTE21__TPM6_CLKIN 0x00D4 0x0994 0x6 0x1

560

#define MX8ULP_PAD_PTE21__I2S7_TXD1 0x00D4 0x0000 0x7 0x0

561

#define MX8ULP_PAD_PTE21__USB1_ID 0x00D4 0x0ACC 0x9 0x2

562

#define MX8ULP_PAD_PTE21__ENET0_RXD0 0x00D4 0x0AF8 0xa 0x1

563

#define MX8ULP_PAD_PTE21__EPDC0_GDRL 0x00D4 0x0000 0xc 0x0

564

#define MX8ULP_PAD_PTE21__WDOG4_RST 0x00D4 0x0000 0xd 0x0

565

#define MX8ULP_PAD_PTE21__LP_HV_DBG_MUX_13 0x00D4 0x0000 0xf 0x0

566

#define MX8ULP_PAD_PTE22__PTE22 0x00D8 0x0000 0x1 0x0

567

#define MX8ULP_PAD_PTE22__FXIO1_D1 0x00D8 0x0840 0x2 0x1

568

#define MX8ULP_PAD_PTE22__LPSPI5_SCK 0x00D8 0x0920 0x3 0x1

569

#define MX8ULP_PAD_PTE22__LPUART5_TX 0x00D8 0x08F0 0x4 0x2

570

#define MX8ULP_PAD_PTE22__I3C2_SCL 0x00D8 0x08BC 0x5 0x2

571

#define MX8ULP_PAD_PTE22__TPM6_CH0 0x00D8 0x097C 0x6 0x1

572

#define MX8ULP_PAD_PTE22__I2S7_TXD2 0x00D8 0x0000 0x7 0x0

573

#define MX8ULP_PAD_PTE22__EXT_AUD_MCLK3 0x00D8 0x0B14 0x9 0x5

574

#define MX8ULP_PAD_PTE22__ENET0_TXD1 0x00D8 0x0000 0xa 0x0

575

#define MX8ULP_PAD_PTE22__EPDC0_SDOED 0x00D8 0x0000 0xc 0x0

576

#define MX8ULP_PAD_PTE22__CLKOUT2 0x00D8 0x0000 0xd 0x0

577

#define MX8ULP_PAD_PTE22__LP_HV_DBG_MUX_14 0x00D8 0x0000 0xf 0x0

578

#define MX8ULP_PAD_PTE23__PTE23 0x00DC 0x0000 0x1 0x0

579

#define MX8ULP_PAD_PTE23__FXIO1_D0 0x00DC 0x083C 0x2 0x1

580

#define MX8ULP_PAD_PTE23__LPSPI5_PCS0 0x00DC 0x0910 0x3 0x1

581

#define MX8ULP_PAD_PTE23__LPUART5_RX 0x00DC 0x08EC 0x4 0x2

582

#define MX8ULP_PAD_PTE23__I3C2_SDA 0x00DC 0x08C0 0x5 0x2

583

#define MX8ULP_PAD_PTE23__TPM6_CH1 0x00DC 0x0980 0x6 0x1

584

#define MX8ULP_PAD_PTE23__I2S7_TXD3 0x00DC 0x0000 0x7 0x0

585

#define MX8ULP_PAD_PTE23__EXT_AUD_MCLK2 0x00DC 0x0800 0x9 0x1

586

#define MX8ULP_PAD_PTE23__ENET0_TXD0 0x00DC 0x0000 0xa 0x0

587

#define MX8ULP_PAD_PTE23__EPDC0_SDOEZ 0x00DC 0x0000 0xc 0x0

588

#define MX8ULP_PAD_PTE23__CLKOUT1 0x00DC 0x0000 0xd 0x0

589

#define MX8ULP_PAD_PTE23__LP_HV_DBG_MUX_15 0x00DC 0x0000 0xf 0x0

590

#define MX8ULP_PAD_PTF0__PTF0 0x0100 0x0000 0x1 0x0

591

#define MX8ULP_PAD_PTF0__FXIO1_D0 0x0100 0x083C 0x2 0x2

592

#define MX8ULP_PAD_PTF0__LPUART6_CTS_B 0x0100 0x09CC 0x4 0x2

593

#define MX8ULP_PAD_PTF0__LPI2C6_SCL 0x0100 0x09B8 0x5 0x2

594

#define MX8ULP_PAD_PTF0__I2S7_RX_BCLK 0x0100 0x0B64 0x7 0x2

595

#define MX8ULP_PAD_PTF0__SDHC1_D1 0x0100 0x0A68 0x8 0x2

596

#define MX8ULP_PAD_PTF0__ENET0_RXD1 0x0100 0x0AFC 0x9 0x2

597

#define MX8ULP_PAD_PTF0__USB1_ID 0x0100 0x0ACC 0xa 0x3

598

#define MX8ULP_PAD_PTF0__EPDC0_SDOE 0x0100 0x0000 0xb 0x0

599

#define MX8ULP_PAD_PTF0__DPI0_D23 0x0100 0x0000 0xc 0x0

600

#define MX8ULP_PAD_PTF0__WUU1_P8 0x0100 0x0000 0xd 0x0

601

#define MX8ULP_PAD_PTF1__PTF1 0x0104 0x0000 0x1 0x0

602

#define MX8ULP_PAD_PTF1__FXIO1_D1 0x0104 0x0840 0x2 0x2

603

#define MX8ULP_PAD_PTF1__LPUART6_RTS_B 0x0104 0x0000 0x4 0x0

604

#define MX8ULP_PAD_PTF1__LPI2C6_SDA 0x0104 0x09BC 0x5 0x2

605

#define MX8ULP_PAD_PTF1__I2S7_RX_FS 0x0104 0x0B68 0x7 0x2

606

#define MX8ULP_PAD_PTF1__SDHC1_D0 0x0104 0x0A64 0x8 0x2

607

#define MX8ULP_PAD_PTF1__ENET0_RXD0 0x0104 0x0AF8 0x9 0x2

608

#define MX8ULP_PAD_PTF1__LP_HV_DBG_MUX_16 0x0104 0x0000 0xa 0x0

609

#define MX8ULP_PAD_PTF1__EPDC0_SDSHR 0x0104 0x0000 0xb 0x0

610

#define MX8ULP_PAD_PTF1__DPI0_D22 0x0104 0x0000 0xc 0x0

611

#define MX8ULP_PAD_PTF1__WDOG3_RST 0x0104 0x0000 0xd 0x0

612

#define MX8ULP_PAD_PTF1__DEBUG_MUX0_16 0x0104 0x0000 0xe 0x0

613

#define MX8ULP_PAD_PTF1__DEBUG_MUX1_22 0x0104 0x0000 0xf 0x0

614

#define MX8ULP_PAD_PTF2__PTF2 0x0108 0x0000 0x1 0x0

615

#define MX8ULP_PAD_PTF2__FXIO1_D2 0x0108 0x086C 0x2 0x2

616

#define MX8ULP_PAD_PTF2__LPUART6_TX 0x0108 0x09D4 0x4 0x2

617

#define MX8ULP_PAD_PTF2__LPI2C6_HREQ 0x0108 0x09B4 0x5 0x2

618

#define MX8ULP_PAD_PTF2__I2S7_RXD0 0x0108 0x0B54 0x7 0x2

619

#define MX8ULP_PAD_PTF2__SDHC1_CLK 0x0108 0x0A5C 0x8 0x2

620

#define MX8ULP_PAD_PTF2__ENET0_TXD1 0x0108 0x0000 0x9 0x0

621

#define MX8ULP_PAD_PTF2__USB0_ID 0x0108 0x0AC8 0xa 0x3

622

#define MX8ULP_PAD_PTF2__EPDC0_SDCE9 0x0108 0x0000 0xb 0x0

623

#define MX8ULP_PAD_PTF2__DPI0_D21 0x0108 0x0000 0xc 0x0

624

#define MX8ULP_PAD_PTF2__LP_HV_DBG_MUX_17 0x0108 0x0000 0xd 0x0

625

#define MX8ULP_PAD_PTF2__DEBUG_MUX0_17 0x0108 0x0000 0xe 0x0

626

#define MX8ULP_PAD_PTF2__DEBUG_MUX1_23 0x0108 0x0000 0xf 0x0

627

#define MX8ULP_PAD_PTF3__PTF3 0x010C 0x0000 0x1 0x0

628

#define MX8ULP_PAD_PTF3__FXIO1_D3 0x010C 0x0898 0x2 0x2

629

#define MX8ULP_PAD_PTF3__LPUART6_RX 0x010C 0x09D0 0x4 0x2

630

#define MX8ULP_PAD_PTF3__LPI2C7_HREQ 0x010C 0x09C0 0x5 0x2

631

#define MX8ULP_PAD_PTF3__I2S7_RXD1 0x010C 0x0B58 0x7 0x2

632

#define MX8ULP_PAD_PTF3__SDHC1_CMD 0x010C 0x0A60 0x8 0x2

633

#define MX8ULP_PAD_PTF3__ENET0_TXD0 0x010C 0x0000 0x9 0x0

634

#define MX8ULP_PAD_PTF3__USB0_PWR 0x010C 0x0000 0xa 0x0

635

#define MX8ULP_PAD_PTF3__EPDC0_SDCE8 0x010C 0x0000 0xb 0x0

636

#define MX8ULP_PAD_PTF3__DPI0_D20 0x010C 0x0000 0xc 0x0

637

#define MX8ULP_PAD_PTF3__WUU1_P9 0x010C 0x0000 0xd 0x0

638

#define MX8ULP_PAD_PTF3__DEBUG_MUX1_24 0x010C 0x0000 0xf 0x0

639

#define MX8ULP_PAD_PTF4__PTF4 0x0110 0x0000 0x1 0x0

640

#define MX8ULP_PAD_PTF4__FXIO1_D4 0x0110 0x08A4 0x2 0x2

641

#define MX8ULP_PAD_PTF4__LPSPI4_PCS1 0x0110 0x08F8 0x3 0x3

642

#define MX8ULP_PAD_PTF4__LPUART7_CTS_B 0x0110 0x09D8 0x4 0x2

643

#define MX8ULP_PAD_PTF4__LPI2C7_SCL 0x0110 0x09C4 0x5 0x2

644

#define MX8ULP_PAD_PTF4__TPM7_CLKIN 0x0110 0x09B0 0x6 0x1

645

#define MX8ULP_PAD_PTF4__I2S7_RXD2 0x0110 0x0B5C 0x7 0x2

646

#define MX8ULP_PAD_PTF4__SDHC1_D3 0x0110 0x0A70 0x8 0x2

647

#define MX8ULP_PAD_PTF4__ENET0_TXEN 0x0110 0x0000 0x9 0x0

648

#define MX8ULP_PAD_PTF4__USB0_OC 0x0110 0x0AC0 0xa 0x3

649

#define MX8ULP_PAD_PTF4__EPDC0_SDCE7 0x0110 0x0000 0xb 0x0

650

#define MX8ULP_PAD_PTF4__DPI0_D19 0x0110 0x0000 0xc 0x0

651

#define MX8ULP_PAD_PTF4__WUU1_P10 0x0110 0x0000 0xd 0x0

652

#define MX8ULP_PAD_PTF4__DEBUG_MUX1_25 0x0110 0x0000 0xf 0x0

653

#define MX8ULP_PAD_PTF5__PTF5 0x0114 0x0000 0x1 0x0

654

#define MX8ULP_PAD_PTF5__FXIO1_D5 0x0114 0x08A8 0x2 0x2

655

#define MX8ULP_PAD_PTF5__LPSPI4_PCS2 0x0114 0x08FC 0x3 0x3

656

#define MX8ULP_PAD_PTF5__LPUART7_RTS_B 0x0114 0x0000 0x4 0x0

657

#define MX8ULP_PAD_PTF5__LPI2C7_SDA 0x0114 0x09C8 0x5 0x2

658

#define MX8ULP_PAD_PTF5__TPM7_CH0 0x0114 0x0998 0x6 0x1

659

#define MX8ULP_PAD_PTF5__I2S7_RXD3 0x0114 0x0B60 0x7 0x2

660

#define MX8ULP_PAD_PTF5__SDHC1_D2 0x0114 0x0A6C 0x8 0x2

661

#define MX8ULP_PAD_PTF5__ENET0_RXER 0x0114 0x0B08 0x9 0x2

662

#define MX8ULP_PAD_PTF5__USB1_PWR 0x0114 0x0000 0xa 0x0

663

#define MX8ULP_PAD_PTF5__EPDC0_SDCE6 0x0114 0x0000 0xb 0x0

664

#define MX8ULP_PAD_PTF5__DPI0_D18 0x0114 0x0000 0xc 0x0

665

#define MX8ULP_PAD_PTF5__LP_HV_DBG_MUX_18 0x0114 0x0000 0xd 0x0

666

#define MX8ULP_PAD_PTF5__DEBUG_MUX0_18 0x0114 0x0000 0xe 0x0

667

#define MX8ULP_PAD_PTF5__DEBUG_MUX1_26 0x0114 0x0000 0xf 0x0

668

#define MX8ULP_PAD_PTF6__LP_HV_DBG_MUX_19 0x0118 0x0000 0x0 0x0

669

#define MX8ULP_PAD_PTF6__PTF6 0x0118 0x0000 0x1 0x0

670

#define MX8ULP_PAD_PTF6__FXIO1_D6 0x0118 0x08AC 0x2 0x2

671

#define MX8ULP_PAD_PTF6__LPSPI4_PCS3 0x0118 0x0900 0x3 0x3

672

#define MX8ULP_PAD_PTF6__LPUART7_TX 0x0118 0x09E0 0x4 0x2

673

#define MX8ULP_PAD_PTF6__I3C2_SCL 0x0118 0x08BC 0x5 0x3

674

#define MX8ULP_PAD_PTF6__TPM7_CH1 0x0118 0x099C 0x6 0x1

675

#define MX8ULP_PAD_PTF6__I2S7_MCLK 0x0118 0x0000 0x7 0x0

676

#define MX8ULP_PAD_PTF6__SDHC1_D4 0x0118 0x0A74 0x8 0x2

677

#define MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x0118 0x0AEC 0x9 0x2

678

#define MX8ULP_PAD_PTF6__USB1_OC 0x0118 0x0AC4 0xa 0x3

679

#define MX8ULP_PAD_PTF6__EPDC0_SDCE5 0x0118 0x0000 0xb 0x0

680

#define MX8ULP_PAD_PTF6__DPI0_D17 0x0118 0x0000 0xc 0x0

681

#define MX8ULP_PAD_PTF6__WDOG4_RST 0x0118 0x0000 0xd 0x0

682

#define MX8ULP_PAD_PTF6__DEBUG_MUX0_19 0x0118 0x0000 0xe 0x0

683

#define MX8ULP_PAD_PTF6__DEBUG_MUX1_27 0x0118 0x0000 0xf 0x0

684

#define MX8ULP_PAD_PTF7__PTF7 0x011C 0x0000 0x1 0x0

685

#define MX8ULP_PAD_PTF7__FXIO1_D7 0x011C 0x08B0 0x2 0x2

686

#define MX8ULP_PAD_PTF7__LPUART7_RX 0x011C 0x09DC 0x4 0x2

687

#define MX8ULP_PAD_PTF7__I3C2_SDA 0x011C 0x08C0 0x5 0x3

688

#define MX8ULP_PAD_PTF7__TPM7_CH2 0x011C 0x09A0 0x6 0x1

689

#define MX8ULP_PAD_PTF7__MQS1_LEFT 0x011C 0x0000 0x7 0x0

690

#define MX8ULP_PAD_PTF7__SDHC1_D5 0x011C 0x0A78 0x8 0x2

691

#define MX8ULP_PAD_PTF7__ENET0_REFCLK 0x011C 0x0AF4 0x9 0x2

692

#define MX8ULP_PAD_PTF7__TRACE0_D15 0x011C 0x0000 0xa 0x0

693

#define MX8ULP_PAD_PTF7__EPDC0_SDCE4 0x011C 0x0000 0xb 0x0

694

#define MX8ULP_PAD_PTF7__DPI0_D16 0x011C 0x0000 0xc 0x0

695

#define MX8ULP_PAD_PTF7__WUU1_P11 0x011C 0x0000 0xd 0x0

696

#define MX8ULP_PAD_PTF7__DEBUG_MUX1_28 0x011C 0x0000 0xf 0x0

697

#define MX8ULP_PAD_PTF8__PTF8 0x0120 0x0000 0x1 0x0

698

#define MX8ULP_PAD_PTF8__FXIO1_D8 0x0120 0x08B4 0x2 0x2

699

#define MX8ULP_PAD_PTF8__LPSPI4_SIN 0x0120 0x0908 0x3 0x3

700

#define MX8ULP_PAD_PTF8__LPUART4_CTS_B 0x0120 0x08DC 0x4 0x3

701

#define MX8ULP_PAD_PTF8__LPI2C4_SCL 0x0120 0x08C8 0x5 0x3

702

#define MX8ULP_PAD_PTF8__TPM7_CH3 0x0120 0x09A4 0x6 0x1

703

#define MX8ULP_PAD_PTF8__MQS1_RIGHT 0x0120 0x0000 0x7 0x0

704

#define MX8ULP_PAD_PTF8__SDHC1_D6 0x0120 0x0A7C 0x8 0x2

705

#define MX8ULP_PAD_PTF8__ENET0_MDIO 0x0120 0x0AF0 0x9 0x2

706

#define MX8ULP_PAD_PTF8__TRACE0_D14 0x0120 0x0000 0xa 0x0

707

#define MX8ULP_PAD_PTF8__EPDC0_D15 0x0120 0x0000 0xb 0x0

708

#define MX8ULP_PAD_PTF8__DPI0_D15 0x0120 0x0000 0xc 0x0

709

#define MX8ULP_PAD_PTF8__LP_HV_DBG_MUX_24 0x0120 0x0000 0xe 0x0

710

#define MX8ULP_PAD_PTF8__DEBUG_MUX1_29 0x0120 0x0000 0xf 0x0

711

#define MX8ULP_PAD_PTF9__PTF9 0x0124 0x0000 0x1 0x0

712

#define MX8ULP_PAD_PTF9__FXIO1_D9 0x0124 0x08B8 0x2 0x2

713

#define MX8ULP_PAD_PTF9__LPSPI4_SOUT 0x0124 0x090C 0x3 0x3

714

#define MX8ULP_PAD_PTF9__LPUART4_RTS_B 0x0124 0x0000 0x4 0x0

715

#define MX8ULP_PAD_PTF9__LPI2C4_SDA 0x0124 0x08CC 0x5 0x3

716

#define MX8ULP_PAD_PTF9__TPM7_CH4 0x0124 0x09A8 0x6 0x1

717

#define MX8ULP_PAD_PTF9__EXT_AUD_MCLK2 0x0124 0x0800 0x7 0x2

718

#define MX8ULP_PAD_PTF9__SDHC1_D7 0x0124 0x0A80 0x8 0x2

719

#define MX8ULP_PAD_PTF9__ENET0_MDC 0x0124 0x0000 0x9 0x0

720

#define MX8ULP_PAD_PTF9__TRACE0_D13 0x0124 0x0000 0xa 0x0

721

#define MX8ULP_PAD_PTF9__EPDC0_D14 0x0124 0x0000 0xb 0x0

722

#define MX8ULP_PAD_PTF9__DPI0_D14 0x0124 0x0000 0xc 0x0

723

#define MX8ULP_PAD_PTF9__LP_HV_DBG_MUX_25 0x0124 0x0000 0xe 0x0

724

#define MX8ULP_PAD_PTF9__DEBUG_MUX1_30 0x0124 0x0000 0xf 0x0

725

#define MX8ULP_PAD_PTF10__LP_HV_DBG_MUX_26 0x0128 0x0000 0x0 0x0

726

#define MX8ULP_PAD_PTF10__PTF10 0x0128 0x0000 0x1 0x0

727

#define MX8ULP_PAD_PTF10__FXIO1_D10 0x0128 0x0844 0x2 0x2

728

#define MX8ULP_PAD_PTF10__LPSPI4_SCK 0x0128 0x0904 0x3 0x3

729

#define MX8ULP_PAD_PTF10__LPUART4_TX 0x0128 0x08E4 0x4 0x3

730

#define MX8ULP_PAD_PTF10__LPI2C4_HREQ 0x0128 0x08C4 0x5 0x3

731

#define MX8ULP_PAD_PTF10__TPM7_CH5 0x0128 0x09AC 0x6 0x1

732

#define MX8ULP_PAD_PTF10__I2S4_RX_BCLK 0x0128 0x0000 0x7 0x0

733

#define MX8ULP_PAD_PTF10__SDHC1_DQS 0x0128 0x0A84 0x8 0x2

734

#define MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x0128 0x0AD0 0x9 0x2

735

#define MX8ULP_PAD_PTF10__TRACE0_D12 0x0128 0x0000 0xa 0x0

736

#define MX8ULP_PAD_PTF10__EPDC0_D13 0x0128 0x0000 0xb 0x0

737

#define MX8ULP_PAD_PTF10__DPI0_D13 0x0128 0x0000 0xc 0x0

738

#define MX8ULP_PAD_PTF10__DEBUG_MUX0_20 0x0128 0x0000 0xe 0x0

739

#define MX8ULP_PAD_PTF10__DEBUG_MUX1_31 0x0128 0x0000 0xf 0x0

740

#define MX8ULP_PAD_PTF11__PTF11 0x012C 0x0000 0x1 0x0

741

#define MX8ULP_PAD_PTF11__FXIO1_D11 0x012C 0x0848 0x2 0x2

742

#define MX8ULP_PAD_PTF11__LPSPI4_PCS0 0x012C 0x08F4 0x3 0x3

743

#define MX8ULP_PAD_PTF11__LPUART4_RX 0x012C 0x08E0 0x4 0x3

744

#define MX8ULP_PAD_PTF11__TPM4_CLKIN 0x012C 0x081C 0x6 0x2

745

#define MX8ULP_PAD_PTF11__I2S4_RX_FS 0x012C 0x0000 0x7 0x0

746

#define MX8ULP_PAD_PTF11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0

747

#define MX8ULP_PAD_PTF11__ENET0_1588_TMR0 0x012C 0x0AD4 0x9 0x2

748

#define MX8ULP_PAD_PTF11__TRACE0_D11 0x012C 0x0000 0xa 0x0

749

#define MX8ULP_PAD_PTF11__EPDC0_D12 0x012C 0x0000 0xb 0x0

750

#define MX8ULP_PAD_PTF11__DPI0_D12 0x012C 0x0000 0xc 0x0

751

#define MX8ULP_PAD_PTF11__LP_HV_DBG_MUX_27 0x012C 0x0000 0xe 0x0

752

#define MX8ULP_PAD_PTF11__DEBUG_MUX1_32 0x012C 0x0000 0xf 0x0

753

#define MX8ULP_PAD_PTF12__PTF12 0x0130 0x0000 0x1 0x0

754

#define MX8ULP_PAD_PTF12__FXIO1_D12 0x0130 0x084C 0x2 0x2

755

#define MX8ULP_PAD_PTF12__LPSPI5_PCS1 0x0130 0x0914 0x3 0x2

756

#define MX8ULP_PAD_PTF12__LPUART5_CTS_B 0x0130 0x08E8 0x4 0x3

757

#define MX8ULP_PAD_PTF12__LPI2C5_SCL 0x0130 0x08D4 0x5 0x3

758

#define MX8ULP_PAD_PTF12__TPM4_CH0 0x0130 0x0804 0x6 0x2

759

#define MX8ULP_PAD_PTF12__I2S4_RXD0 0x0130 0x0000 0x7 0x0

760

#define MX8ULP_PAD_PTF12__SDHC2_WP 0x0130 0x0ABC 0x8 0x1

761

#define MX8ULP_PAD_PTF12__ENET0_1588_TMR1 0x0130 0x0AD8 0x9 0x2

762

#define MX8ULP_PAD_PTF12__TRACE0_D10 0x0130 0x0000 0xa 0x0

763

#define MX8ULP_PAD_PTF12__EPDC0_D11 0x0130 0x0000 0xb 0x0

764

#define MX8ULP_PAD_PTF12__DPI0_D11 0x0130 0x0000 0xc 0x0

765

#define MX8ULP_PAD_PTF12__LP_HV_DBG_MUX_28 0x0130 0x0000 0xe 0x0

766

#define MX8ULP_PAD_PTF12__DEBUG_MUX1_33 0x0130 0x0000 0xf 0x0

767

#define MX8ULP_PAD_PTF13__PTF13 0x0134 0x0000 0x1 0x0

768

#define MX8ULP_PAD_PTF13__FXIO1_D13 0x0134 0x0850 0x2 0x2

769

#define MX8ULP_PAD_PTF13__LPSPI5_PCS2 0x0134 0x0918 0x3 0x2

770

#define MX8ULP_PAD_PTF13__LPUART5_RTS_B 0x0134 0x0000 0x4 0x0

771

#define MX8ULP_PAD_PTF13__LPI2C5_SDA 0x0134 0x08D8 0x5 0x3

772

#define MX8ULP_PAD_PTF13__TPM4_CH1 0x0134 0x0808 0x6 0x2

773

#define MX8ULP_PAD_PTF13__I2S4_RXD1 0x0134 0x0000 0x7 0x0

774

#define MX8ULP_PAD_PTF13__SDHC2_CD 0x0134 0x0A8C 0x8 0x1

775

#define MX8ULP_PAD_PTF13__ENET0_1588_TMR2 0x0134 0x0ADC 0x9 0x2

776

#define MX8ULP_PAD_PTF13__TRACE0_D9 0x0134 0x0000 0xa 0x0

777

#define MX8ULP_PAD_PTF13__EPDC0_D10 0x0134 0x0000 0xb 0x0

778

#define MX8ULP_PAD_PTF13__DPI0_D10 0x0134 0x0000 0xc 0x0

779

#define MX8ULP_PAD_PTF13__DEBUG_MUX0_21 0x0134 0x0000 0xe 0x0

780

#define MX8ULP_PAD_PTF13__LP_HV_DBG_MUX_29 0x0134 0x0000 0xf 0x0

781

#define MX8ULP_PAD_PTF14__PTF14 0x0138 0x0000 0x1 0x0

782

#define MX8ULP_PAD_PTF14__FXIO1_D14 0x0138 0x0854 0x2 0x2

783

#define MX8ULP_PAD_PTF14__LPSPI5_PCS3 0x0138 0x091C 0x3 0x2

784

#define MX8ULP_PAD_PTF14__LPUART5_TX 0x0138 0x08F0 0x4 0x3

785

#define MX8ULP_PAD_PTF14__LPI2C5_HREQ 0x0138 0x08D0 0x5 0x3

786

#define MX8ULP_PAD_PTF14__TPM4_CH2 0x0138 0x080C 0x6 0x2

787

#define MX8ULP_PAD_PTF14__I2S4_MCLK 0x0138 0x0000 0x7 0x0

788

#define MX8ULP_PAD_PTF14__SDHC2_VS 0x0138 0x0000 0x8 0x0

789

#define MX8ULP_PAD_PTF14__ENET0_1588_TMR3 0x0138 0x0AE0 0x9 0x2

790

#define MX8ULP_PAD_PTF14__TRACE0_D8 0x0138 0x0000 0xa 0x0

791

#define MX8ULP_PAD_PTF14__EPDC0_D9 0x0138 0x0000 0xb 0x0

792

#define MX8ULP_PAD_PTF14__DPI0_D9 0x0138 0x0000 0xc 0x0

793

#define MX8ULP_PAD_PTF14__DEBUG_MUX0_22 0x0138 0x0000 0xe 0x0

794

#define MX8ULP_PAD_PTF14__LP_HV_DBG_MUX_30 0x0138 0x0000 0xf 0x0

795

#define MX8ULP_PAD_PTF15__PTF15 0x013C 0x0000 0x1 0x0

796

#define MX8ULP_PAD_PTF15__FXIO1_D15 0x013C 0x0858 0x2 0x2

797

#define MX8ULP_PAD_PTF15__LPUART5_RX 0x013C 0x08EC 0x4 0x3

798

#define MX8ULP_PAD_PTF15__TPM4_CH3 0x013C 0x0810 0x6 0x2

799

#define MX8ULP_PAD_PTF15__I2S4_TX_BCLK 0x013C 0x0000 0x7 0x0

800

#define MX8ULP_PAD_PTF15__SDHC2_D1 0x013C 0x0A9C 0x8 0x3

801

#define MX8ULP_PAD_PTF15__ENET0_RXD2 0x013C 0x0B00 0x9 0x2

802

#define MX8ULP_PAD_PTF15__TRACE0_D7 0x013C 0x0000 0xa 0x0

803

#define MX8ULP_PAD_PTF15__EPDC0_D8 0x013C 0x0000 0xb 0x0

804

#define MX8ULP_PAD_PTF15__DPI0_D8 0x013C 0x0000 0xc 0x0

805

#define MX8ULP_PAD_PTF15__LP_HV_DBG_MUX_31 0x013C 0x0000 0xf 0x0

806

#define MX8ULP_PAD_PTF16__PTF16 0x0140 0x0000 0x1 0x0

807

#define MX8ULP_PAD_PTF16__FXIO1_D16 0x0140 0x085C 0x2 0x2

808

#define MX8ULP_PAD_PTF16__LPSPI5_SIN 0x0140 0x0924 0x3 0x2

809

#define MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x0140 0x09CC 0x4 0x3

810

#define MX8ULP_PAD_PTF16__LPI2C6_SCL 0x0140 0x09B8 0x5 0x3

811

#define MX8ULP_PAD_PTF16__TPM4_CH4 0x0140 0x0814 0x6 0x2

812

#define MX8ULP_PAD_PTF16__I2S4_TX_FS 0x0140 0x0000 0x7 0x0

813

#define MX8ULP_PAD_PTF16__SDHC2_D0 0x0140 0x0A98 0x8 0x3

814

#define MX8ULP_PAD_PTF16__ENET0_RXD3 0x0140 0x0B04 0x9 0x2

815

#define MX8ULP_PAD_PTF16__TRACE0_D6 0x0140 0x0000 0xa 0x0

816

#define MX8ULP_PAD_PTF16__EPDC0_D7 0x0140 0x0000 0xb 0x0

817

#define MX8ULP_PAD_PTF16__DPI0_D7 0x0140 0x0000 0xc 0x0

818

#define MX8ULP_PAD_PTF16__LP_HV_DBG_MUX_32 0x0140 0x0000 0xf 0x0

819

#define MX8ULP_PAD_PTF17__PTF17 0x0144 0x0000 0x1 0x0

820

#define MX8ULP_PAD_PTF17__FXIO1_D17 0x0144 0x0860 0x2 0x2

821

#define MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x0144 0x0928 0x3 0x2

822

#define MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x0144 0x0000 0x4 0x0

823

#define MX8ULP_PAD_PTF17__LPI2C6_SDA 0x0144 0x09BC 0x5 0x3

824

#define MX8ULP_PAD_PTF17__TPM4_CH5 0x0144 0x0818 0x6 0x2

825

#define MX8ULP_PAD_PTF17__I2S4_TXD0 0x0144 0x0000 0x7 0x0

826

#define MX8ULP_PAD_PTF17__SDHC2_CLK 0x0144 0x0A90 0x8 0x3

827

#define MX8ULP_PAD_PTF17__ENET0_RXCLK 0x0144 0x0B0C 0x9 0x2

828

#define MX8ULP_PAD_PTF17__TRACE0_D5 0x0144 0x0000 0xa 0x0

829

#define MX8ULP_PAD_PTF17__EPDC0_D6 0x0144 0x0000 0xb 0x0

830

#define MX8ULP_PAD_PTF17__DPI0_D6 0x0144 0x0000 0xc 0x0

831

#define MX8ULP_PAD_PTF17__DEBUG_MUX0_23 0x0144 0x0000 0xe 0x0

832

#define MX8ULP_PAD_PTF17__LP_HV_DBG_MUX_33 0x0144 0x0000 0xf 0x0

833

#define MX8ULP_PAD_PTF18__PTF18 0x0148 0x0000 0x1 0x0

834

#define MX8ULP_PAD_PTF18__FXIO1_D18 0x0148 0x0864 0x2 0x2

835

#define MX8ULP_PAD_PTF18__LPSPI5_SCK 0x0148 0x0920 0x3 0x2

836

#define MX8ULP_PAD_PTF18__LPUART6_TX 0x0148 0x09D4 0x4 0x3

837

#define MX8ULP_PAD_PTF18__LPI2C6_HREQ 0x0148 0x09B4 0x5 0x3

838

#define MX8ULP_PAD_PTF18__TPM5_CLKIN 0x0148 0x0838 0x6 0x2

839

#define MX8ULP_PAD_PTF18__I2S4_TXD1 0x0148 0x0000 0x7 0x0

840

#define MX8ULP_PAD_PTF18__SDHC2_CMD 0x0148 0x0A94 0x8 0x3

841

#define MX8ULP_PAD_PTF18__ENET0_TXD2 0x0148 0x0000 0x9 0x0

842

#define MX8ULP_PAD_PTF18__TRACE0_D4 0x0148 0x0000 0xa 0x0

843

#define MX8ULP_PAD_PTF18__EPDC0_D5 0x0148 0x0000 0xb 0x0

844

#define MX8ULP_PAD_PTF18__DPI0_D5 0x0148 0x0000 0xc 0x0

845

#define MX8ULP_PAD_PTF19__PTF19 0x014C 0x0000 0x1 0x0

846

#define MX8ULP_PAD_PTF19__FXIO1_D19 0x014C 0x0868 0x2 0x2

847

#define MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x014C 0x0910 0x3 0x2

848

#define MX8ULP_PAD_PTF19__LPUART6_RX 0x014C 0x09D0 0x4 0x3

849

#define MX8ULP_PAD_PTF19__TPM5_CH0 0x014C 0x0820 0x6 0x2

850

#define MX8ULP_PAD_PTF19__I2S5_RX_BCLK 0x014C 0x0000 0x7 0x0

851

#define MX8ULP_PAD_PTF19__SDHC2_D3 0x014C 0x0AA4 0x8 0x3

852

#define MX8ULP_PAD_PTF19__ENET0_TXD3 0x014C 0x0000 0x9 0x0

853

#define MX8ULP_PAD_PTF19__TRACE0_D3 0x014C 0x0000 0xa 0x0

854

#define MX8ULP_PAD_PTF19__EPDC0_D4 0x014C 0x0000 0xb 0x0

855

#define MX8ULP_PAD_PTF19__DPI0_D4 0x014C 0x0000 0xc 0x0

856

#define MX8ULP_PAD_PTF20__PTF20 0x0150 0x0000 0x1 0x0

857

#define MX8ULP_PAD_PTF20__FXIO1_D20 0x0150 0x0870 0x2 0x2

858

#define MX8ULP_PAD_PTF20__LPUART7_CTS_B 0x0150 0x09D8 0x4 0x3

859

#define MX8ULP_PAD_PTF20__LPI2C7_SCL 0x0150 0x09C4 0x5 0x3

860

#define MX8ULP_PAD_PTF20__TPM5_CH1 0x0150 0x0824 0x6 0x2

861

#define MX8ULP_PAD_PTF20__I2S5_RX_FS 0x0150 0x0000 0x7 0x0

862

#define MX8ULP_PAD_PTF20__SDHC2_D2 0x0150 0x0AA0 0x8 0x3

863

#define MX8ULP_PAD_PTF20__ENET0_TXCLK 0x0150 0x0B10 0x9 0x2

864

#define MX8ULP_PAD_PTF20__TRACE0_D2 0x0150 0x0000 0xa 0x0

865

#define MX8ULP_PAD_PTF20__EPDC0_D3 0x0150 0x0000 0xb 0x0

866

#define MX8ULP_PAD_PTF20__DPI0_D3 0x0150 0x0000 0xc 0x0

867

#define MX8ULP_PAD_PTF21__PTF21 0x0154 0x0000 0x1 0x0

868

#define MX8ULP_PAD_PTF21__FXIO1_D21 0x0154 0x0874 0x2 0x2

869

#define MX8ULP_PAD_PTF21__SPDIF_CLK 0x0154 0x0000 0x3 0x0

870

#define MX8ULP_PAD_PTF21__LPUART7_RTS_B 0x0154 0x0000 0x4 0x0

871

#define MX8ULP_PAD_PTF21__LPI2C7_SDA 0x0154 0x09C8 0x5 0x3

872

#define MX8ULP_PAD_PTF21__TPM6_CLKIN 0x0154 0x0994 0x6 0x2

873

#define MX8ULP_PAD_PTF21__I2S5_RXD0 0x0154 0x0000 0x7 0x0

874

#define MX8ULP_PAD_PTF21__SDHC2_D4 0x0154 0x0AA8 0x8 0x2

875

#define MX8ULP_PAD_PTF21__ENET0_CRS 0x0154 0x0AE8 0x9 0x2

876

#define MX8ULP_PAD_PTF21__TRACE0_D1 0x0154 0x0000 0xa 0x0

877

#define MX8ULP_PAD_PTF21__EPDC0_D2 0x0154 0x0000 0xb 0x0

878

#define MX8ULP_PAD_PTF21__DPI0_D2 0x0154 0x0000 0xc 0x0

879

#define MX8ULP_PAD_PTF22__PTF22 0x0158 0x0000 0x1 0x0

880

#define MX8ULP_PAD_PTF22__FXIO1_D22 0x0158 0x0878 0x2 0x2

881

#define MX8ULP_PAD_PTF22__SPDIF_IN0 0x0158 0x0B74 0x3 0x3

882

#define MX8ULP_PAD_PTF22__LPUART7_TX 0x0158 0x09E0 0x4 0x3

883

#define MX8ULP_PAD_PTF22__LPI2C7_HREQ 0x0158 0x09C0 0x5 0x3

884

#define MX8ULP_PAD_PTF22__TPM6_CH0 0x0158 0x097C 0x6 0x2

885

#define MX8ULP_PAD_PTF22__I2S5_RXD1 0x0158 0x0000 0x7 0x0

886

#define MX8ULP_PAD_PTF22__SDHC2_D5 0x0158 0x0AAC 0x8 0x2

887

#define MX8ULP_PAD_PTF22__ENET0_COL 0x0158 0x0AE4 0x9 0x2

888

#define MX8ULP_PAD_PTF22__TRACE0_D0 0x0158 0x0000 0xa 0x0

889

#define MX8ULP_PAD_PTF22__EPDC0_D1 0x0158 0x0000 0xb 0x0

890

#define MX8ULP_PAD_PTF22__DPI0_D1 0x0158 0x0000 0xc 0x0

891

#define MX8ULP_PAD_PTF23__PTF23 0x015C 0x0000 0x1 0x0

892

#define MX8ULP_PAD_PTF23__FXIO1_D23 0x015C 0x087C 0x2 0x2

893

#define MX8ULP_PAD_PTF23__SPDIF_OUT0 0x015C 0x0000 0x3 0x0

894

#define MX8ULP_PAD_PTF23__LPUART7_RX 0x015C 0x09DC 0x4 0x3

895

#define MX8ULP_PAD_PTF23__I3C2_PUR 0x015C 0x0000 0x5 0x0

896

#define MX8ULP_PAD_PTF23__TPM6_CH1 0x015C 0x0980 0x6 0x2

897

#define MX8ULP_PAD_PTF23__I2S5_RXD2 0x015C 0x0000 0x7 0x0

898

#define MX8ULP_PAD_PTF23__SDHC2_D6 0x015C 0x0AB0 0x8 0x2

899

#define MX8ULP_PAD_PTF23__ENET0_TXER 0x015C 0x0000 0x9 0x0

900

#define MX8ULP_PAD_PTF23__TRACE0_CLKOUT 0x015C 0x0000 0xa 0x0

901

#define MX8ULP_PAD_PTF23__EPDC0_D0 0x015C 0x0000 0xb 0x0

902

#define MX8ULP_PAD_PTF23__DPI0_D0 0x015C 0x0000 0xc 0x0

903

#define MX8ULP_PAD_PTF24__PTF24 0x0160 0x0000 0x1 0x0

904

#define MX8ULP_PAD_PTF24__FXIO1_D24 0x0160 0x0880 0x2 0x2

905

#define MX8ULP_PAD_PTF24__SPDIF_IN1 0x0160 0x0B78 0x3 0x3

906

#define MX8ULP_PAD_PTF24__I3C2_SCL 0x0160 0x08BC 0x5 0x4

907

#define MX8ULP_PAD_PTF24__I2S5_RXD3 0x0160 0x0000 0x7 0x0

908

#define MX8ULP_PAD_PTF24__SDHC2_D7 0x0160 0x0AB4 0x8 0x2

909

#define MX8ULP_PAD_PTF24__DBI0_WRX 0x0160 0x0000 0xa 0x0

910

#define MX8ULP_PAD_PTF24__EPDC0_SDCLK 0x0160 0x0000 0xb 0x0

911

#define MX8ULP_PAD_PTF24__DPI0_PCLK 0x0160 0x0000 0xc 0x0

912

#define MX8ULP_PAD_PTF24__WUU1_P12 0x0160 0x0000 0xd 0x0

913

#define MX8ULP_PAD_PTF25__PTF25 0x0164 0x0000 0x1 0x0

914

#define MX8ULP_PAD_PTF25__FXIO1_D25 0x0164 0x0884 0x2 0x2

915

#define MX8ULP_PAD_PTF25__SPDIF_OUT1 0x0164 0x0000 0x3 0x0

916

#define MX8ULP_PAD_PTF25__I3C2_SDA 0x0164 0x08C0 0x5 0x4

917

#define MX8ULP_PAD_PTF25__TPM7_CH5 0x0164 0x09AC 0x6 0x2

918

#define MX8ULP_PAD_PTF25__I2S5_MCLK 0x0164 0x0000 0x7 0x0

919

#define MX8ULP_PAD_PTF25__SDHC2_DQS 0x0164 0x0AB8 0x8 0x2

920

#define MX8ULP_PAD_PTF25__EXT_AUD_MCLK2 0x0164 0x0800 0x9 0x3

921

#define MX8ULP_PAD_PTF25__EPDC0_GDSP 0x0164 0x0000 0xb 0x0

922

#define MX8ULP_PAD_PTF25__DPI0_VSYNC 0x0164 0x0000 0xc 0x0

923

#define MX8ULP_PAD_PTF25__WUU1_P13 0x0164 0x0000 0xd 0x0

924

#define MX8ULP_PAD_PTF26__PTF26 0x0168 0x0000 0x1 0x0

925

#define MX8ULP_PAD_PTF26__FXIO1_D26 0x0168 0x0888 0x2 0x2

926

#define MX8ULP_PAD_PTF26__SPDIF_IN2 0x0168 0x0B7C 0x3 0x3

927

#define MX8ULP_PAD_PTF26__TPM7_CLKIN 0x0168 0x09B0 0x6 0x2

928

#define MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x0168 0x0000 0x7 0x0

929

#define MX8ULP_PAD_PTF26__SDHC2_RESET_B 0x0168 0x0000 0x8 0x0

930

#define MX8ULP_PAD_PTF26__EPDC0_SDLE 0x0168 0x0000 0xb 0x0

931

#define MX8ULP_PAD_PTF26__DPI0_HSYNC 0x0168 0x0000 0xc 0x0

932

#define MX8ULP_PAD_PTF26__WUU1_P14 0x0168 0x0000 0xd 0x0

933

#define MX8ULP_PAD_PTF27__PTF27 0x016C 0x0000 0x1 0x0

934

#define MX8ULP_PAD_PTF27__FXIO1_D27 0x016C 0x088C 0x2 0x2

935

#define MX8ULP_PAD_PTF27__SPDIF_OUT2 0x016C 0x0000 0x3 0x0

936

#define MX8ULP_PAD_PTF27__TPM7_CH0 0x016C 0x0998 0x6 0x2

937

#define MX8ULP_PAD_PTF27__I2S5_TX_FS 0x016C 0x0000 0x7 0x0

938

#define MX8ULP_PAD_PTF27__SDHC2_WP 0x016C 0x0ABC 0x8 0x2

939

#define MX8ULP_PAD_PTF27__EPDC0_SDCE0 0x016C 0x0000 0xb 0x0

940

#define MX8ULP_PAD_PTF27__DPI0_DE 0x016C 0x0000 0xc 0x0

941

#define MX8ULP_PAD_PTF27__WUU1_P15 0x016C 0x0000 0xd 0x0

942

#define MX8ULP_PAD_PTF28__PTF28 0x0170 0x0000 0x1 0x0

943

#define MX8ULP_PAD_PTF28__FXIO1_D28 0x0170 0x0890 0x2 0x2

944

#define MX8ULP_PAD_PTF28__SPDIF_IN3 0x0170 0x0B80 0x3 0x3

945

#define MX8ULP_PAD_PTF28__TPM7_CH1 0x0170 0x099C 0x6 0x2

946

#define MX8ULP_PAD_PTF28__I2S5_TXD0 0x0170 0x0000 0x7 0x0

947

#define MX8ULP_PAD_PTF28__SDHC2_CD 0x0170 0x0A8C 0x8 0x2

948

#define MX8ULP_PAD_PTF28__EPDC0_SDCLK_B 0x0170 0x0000 0xb 0x0

949

#define MX8ULP_PAD_PTF28__LP_HV_DBG_MUX_20 0x0170 0x0000 0xf 0x0

950

#define MX8ULP_PAD_PTF29__PTF29 0x0174 0x0000 0x1 0x0

951

#define MX8ULP_PAD_PTF29__FXIO1_D29 0x0174 0x0894 0x2 0x2

952

#define MX8ULP_PAD_PTF29__SPDIF_OUT3 0x0174 0x0000 0x3 0x0

953

#define MX8ULP_PAD_PTF29__TPM7_CH2 0x0174 0x09A0 0x6 0x2

954

#define MX8ULP_PAD_PTF29__I2S5_TXD1 0x0174 0x0000 0x7 0x0

955

#define MX8ULP_PAD_PTF29__SDHC2_VS 0x0174 0x0000 0x8 0x0

956

#define MX8ULP_PAD_PTF29__EPDC0_SDCE1 0x0174 0x0000 0xb 0x0

957

#define MX8ULP_PAD_PTF29__WDOG3_RST 0x0174 0x0000 0xd 0x0

958

#define MX8ULP_PAD_PTF29__LP_HV_DBG_MUX_21 0x0174 0x0000 0xf 0x0

959

#define MX8ULP_PAD_PTF30__PTF30 0x0178 0x0000 0x1 0x0

960

#define MX8ULP_PAD_PTF30__FXIO1_D30 0x0178 0x089C 0x2 0x2

961

#define MX8ULP_PAD_PTF30__TPM7_CH3 0x0178 0x09A4 0x6 0x2

962

#define MX8ULP_PAD_PTF30__I2S5_TXD2 0x0178 0x0000 0x7 0x0

963

#define MX8ULP_PAD_PTF30__MQS1_LEFT 0x0178 0x0000 0x8 0x0

964

#define MX8ULP_PAD_PTF30__EPDC0_SDCE2 0x0178 0x0000 0xb 0x0

965

#define MX8ULP_PAD_PTF30__WDOG4_RST 0x0178 0x0000 0xd 0x0

966

#define MX8ULP_PAD_PTF30__LP_HV_DBG_MUX_22 0x0178 0x0000 0xf 0x0

967

#define MX8ULP_PAD_PTF31__PTF31 0x017C 0x0000 0x1 0x0

968

#define MX8ULP_PAD_PTF31__FXIO1_D31 0x017C 0x08A0 0x2 0x2

969

#define MX8ULP_PAD_PTF31__TPM7_CH4 0x017C 0x09A8 0x6 0x2

970

#define MX8ULP_PAD_PTF31__I2S5_TXD3 0x017C 0x0000 0x7 0x0

971

#define MX8ULP_PAD_PTF31__MQS1_RIGHT 0x017C 0x0000 0x8 0x0

972

#define MX8ULP_PAD_PTF31__EPDC0_SDCE3 0x017C 0x0000 0xb 0x0

973

#define MX8ULP_PAD_PTF31__WDOG5_RST 0x017C 0x0000 0xd 0x0

974

#define MX8ULP_PAD_PTF31__LP_HV_DBG_MUX_23 0x017C 0x0000 0xf 0x0

975

#define MX8ULP_PAD_BOOT_MODE0__BOOT_MODE0 0x0400 0x0000 0x0 0x0

976

#define MX8ULP_PAD_BOOT_MODE1__BOOT_MODE1 0x0404 0x0000 0x0 0x0

977

978

#endif /* __DTS_IMX8ULP_PINFUNC_H */