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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / freescale / imx8mp-venice-gw702x.dtsi
blob: 560c68e4da6dc836944506bf173d6403381132e7 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2023 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/net/ti-dp83867.h>
9
10/ {
11 aliases {
12 ethernet0 = &eqos;
13 };
14
15 memory@40000000 {
16 device_type = "memory";
17 reg = <0x0 0x40000000 0 0x80000000>;
18 };
19
20 gpio-keys {
21 compatible = "gpio-keys";
22
23 key-user-pb {
24 label = "user_pb";
25 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
26 linux,code = <BTN_0>;
27 };
28
29 key-user-pb1x {
30 label = "user_pb1x";
31 linux,code = <BTN_1>;
32 interrupt-parent = <&gsc>;
33 interrupts = <0>;
34 };
35
36 key-erased {
37 label = "key_erased";
38 linux,code = <BTN_2>;
39 interrupt-parent = <&gsc>;
40 interrupts = <1>;
41 };
42
43 key-eeprom-wp {
44 label = "eeprom_wp";
45 linux,code = <BTN_3>;
46 interrupt-parent = <&gsc>;
47 interrupts = <2>;
48 };
49
50 key-tamper {
51 label = "tamper";
52 linux,code = <BTN_4>;
53 interrupt-parent = <&gsc>;
54 interrupts = <5>;
55 };
56
57 switch-hold {
58 label = "switch_hold";
59 linux,code = <BTN_5>;
60 interrupt-parent = <&gsc>;
61 interrupts = <7>;
62 };
63 };
64};
65
66&A53_0 {
67 cpu-supply = <&buck3_reg>;
68};
69
70&A53_1 {
71 cpu-supply = <&buck3_reg>;
72};
73
74&A53_2 {
75 cpu-supply = <&buck3_reg>;
76};
77
78&A53_3 {
79 cpu-supply = <&buck3_reg>;
80};
81
82&eqos {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_eqos>;
85 phy-mode = "rgmii-id";
86 phy-handle = <&ethphy0>;
87 status = "okay";
88
89 mdio {
90 compatible = "snps,dwmac-mdio";
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 ethphy0: ethernet-phy@0 {
95 compatible = "ethernet-phy-ieee802.3-c22";
96 pinctrl-0 = <&pinctrl_ethphy0>;
97 pinctrl-names = "default";
98 reg = <0x0>;
99 interrupt-parent = <&gpio3>;
100 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
101 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
102 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
103 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
104 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
105 };
106 };
107};
108
109&i2c1 {
110 clock-frequency = <100000>;
111 pinctrl-names = "default", "gpio";
112 pinctrl-0 = <&pinctrl_i2c1>;
113 pinctrl-1 = <&pinctrl_i2c1_gpio>;
114 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
115 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
116 status = "okay";
117
118 gsc: gsc@20 {
119 compatible = "gw,gsc";
120 reg = <0x20>;
121 pinctrl-0 = <&pinctrl_gsc>;
122 interrupt-parent = <&gpio2>;
123 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
124 interrupt-controller;
125 #interrupt-cells = <1>;
126 #address-cells = <1>;
127 #size-cells = <0>;
128
129 adc {
130 compatible = "gw,gsc-adc";
131 #address-cells = <1>;
132 #size-cells = <0>;
133
134 channel@6 {
135 gw,mode = <0>;
136 reg = <0x06>;
137 label = "temp";
138 };
139
140 channel@8 {
141 gw,mode = <3>;
142 reg = <0x08>;
143 label = "vdd_bat";
144 };
145
146 channel@16 {
147 gw,mode = <4>;
148 reg = <0x16>;
149 label = "fan_tach";
150 };
151
152 channel@82 {
153 gw,mode = <2>;
154 reg = <0x82>;
155 label = "vdd_vin";
156 gw,voltage-divider-ohms = <22100 1000>;
157 };
158
159 channel@84 {
160 gw,mode = <2>;
161 reg = <0x84>;
162 label = "vdd_adc1";
163 gw,voltage-divider-ohms = <10000 10000>;
164 };
165
166 channel@86 {
167 gw,mode = <2>;
168 reg = <0x86>;
169 label = "vdd_adc2";
170 gw,voltage-divider-ohms = <10000 10000>;
171 };
172
173 channel@88 {
174 gw,mode = <2>;
175 reg = <0x88>;
176 label = "vdd_1p0";
177 };
178
179 channel@8c {
180 gw,mode = <2>;
181 reg = <0x8c>;
182 label = "vdd_1p8";
183 };
184
185 channel@8e {
186 gw,mode = <2>;
187 reg = <0x8e>;
188 label = "vdd_2p5";
189 };
190
191 channel@90 {
192 gw,mode = <2>;
193 reg = <0x90>;
194 label = "vdd_3p3";
195 gw,voltage-divider-ohms = <10000 10000>;
196 };
197
198 channel@92 {
199 gw,mode = <2>;
200 reg = <0x92>;
201 label = "vdd_dram";
202 };
203
204 channel@98 {
205 gw,mode = <2>;
206 reg = <0x98>;
207 label = "vdd_soc";
208 };
209
210 channel@9a {
211 gw,mode = <2>;
212 reg = <0x9a>;
213 label = "vdd_arm";
214 };
215
216 channel@a2 {
217 gw,mode = <2>;
218 reg = <0xa2>;
219 label = "vdd_gsc";
220 gw,voltage-divider-ohms = <10000 10000>;
221 };
222 };
223
224 fan-controller@0 {
225 compatible = "gw,gsc-fan";
226 reg = <0x0a>;
227 };
228 };
229
230 gpio: gpio@23 {
231 compatible = "nxp,pca9555";
232 reg = <0x23>;
233 gpio-controller;
234 #gpio-cells = <2>;
235 interrupt-parent = <&gsc>;
236 interrupts = <4>;
237 };
238
239 eeprom@50 {
240 compatible = "atmel,24c02";
241 reg = <0x50>;
242 pagesize = <16>;
243 };
244
245 eeprom@51 {
246 compatible = "atmel,24c02";
247 reg = <0x51>;
248 pagesize = <16>;
249 };
250
251 eeprom@52 {
252 compatible = "atmel,24c02";
253 reg = <0x52>;
254 pagesize = <16>;
255 };
256
257 eeprom@53 {
258 compatible = "atmel,24c02";
259 reg = <0x53>;
260 pagesize = <16>;
261 };
262
263 rtc@68 {
264 compatible = "dallas,ds1672";
265 reg = <0x68>;
266 };
267
268 pmic@69 {
269 compatible = "mps,mp5416";
270 reg = <0x69>;
271
272 regulators {
273 /* vdd_soc */
274 buck1 {
275 regulator-name = "buck1";
276 regulator-min-microvolt = <850000>;
277 regulator-max-microvolt = <1000000>;
278 regulator-always-on;
279 regulator-boot-on;
280 };
281
282 /* vdd_dram */
283 buck2 {
284 regulator-name = "buck2";
285 regulator-min-microvolt = <1100000>;
286 regulator-max-microvolt = <1100000>;
287 regulator-always-on;
288 regulator-boot-on;
289 };
290
291 /* vdd_arm */
292 buck3_reg: buck3 {
293 regulator-name = "buck3";
294 regulator-min-microvolt = <850000>;
295 regulator-max-microvolt = <1000000>;
296 regulator-always-on;
297 regulator-boot-on;
298 };
299
300 /* vdd_1p8 */
301 buck4 {
302 regulator-name = "buck4";
303 regulator-min-microvolt = <1800000>;
304 regulator-max-microvolt = <1800000>;
305 regulator-always-on;
306 regulator-boot-on;
307 };
308
309 /* OUT2: nvcc_snvs_1p8 */
310 ldo1 {
311 regulator-name = "ldo1";
312 regulator-min-microvolt = <1800000>;
313 regulator-max-microvolt = <1800000>;
314 regulator-always-on;
315 regulator-boot-on;
316 };
317
318 /* OUT3: vdd_1p0 */
319 ldo2 {
320 regulator-name = "ldo2";
321 regulator-min-microvolt = <1000000>;
322 regulator-max-microvolt = <1000000>;
323 regulator-always-on;
324 regulator-boot-on;
325 };
326
327 /* OUT4: vdd_2p5 */
328 ldo3 {
329 regulator-name = "ldo3";
330 regulator-min-microvolt = <2500000>;
331 regulator-max-microvolt = <2500000>;
332 regulator-always-on;
333 regulator-boot-on;
334 };
335
336 /* OUT5: vdd_3p3 */
337 ldo4 {
338 regulator-name = "ldo4";
339 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <3300000>;
341 regulator-always-on;
342 regulator-boot-on;
343 };
344 };
345 };
346};
347
348/* off-board header */
349&i2c2 {
350 clock-frequency = <400000>;
351 pinctrl-names = "default", "gpio";
352 pinctrl-0 = <&pinctrl_i2c2>;
353 pinctrl-1 = <&pinctrl_i2c2_gpio>;
354 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
355 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
356 status = "okay";
357
358 eeprom@52 {
359 compatible = "atmel,24c32";
360 reg = <0x52>;
361 pagesize = <32>;
362 };
363};
364
365/* off-board header */
366&i2c3 {
367 clock-frequency = <400000>;
368 pinctrl-names = "default", "gpio";
369 pinctrl-0 = <&pinctrl_i2c3>;
370 pinctrl-1 = <&pinctrl_i2c3_gpio>;
371 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
372 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
373 status = "okay";
374};
375
376/* off-board header */
377&uart1 {
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_uart1>;
380 status = "okay";
381};
382
383/* console */
384&uart2 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_uart2>;
387 status = "okay";
388};
389
390/* off-board header */
391&uart3 {
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_uart3>;
394 status = "okay";
395};
396
397/* off-board */
398&usdhc1 {
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_usdhc1>;
401 bus-width = <4>;
402 non-removable;
403 status = "okay";
404 bus-width = <4>;
405 non-removable;
406 status = "okay";
407};
408
409/* eMMC */
410&usdhc3 {
411 pinctrl-names = "default", "state_100mhz", "state_200mhz";
412 pinctrl-0 = <&pinctrl_usdhc3>;
413 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
414 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
415 bus-width = <8>;
416 non-removable;
417 status = "okay";
418};
419
420&wdog1 {
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_wdog>;
423 fsl,ext-reset-output;
424 status = "okay";
425};
426
427&iomuxc {
428 pinctrl_eqos: eqosgrp {
429 fsl,pins = <
430 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
431 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
432 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
433 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
434 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
435 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
436 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
437 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
438 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
439 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
440 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
441 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
442 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
443 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
444 >;
445 };
446
447 pinctrl_ethphy0: ethphy0grp {
448 fsl,pins = <
449 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */
450 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */
451 >;
452 };
453
454 pinctrl_gsc: gscgrp {
455 fsl,pins = <
456 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */
457 >;
458 };
459
460 pinctrl_i2c1: i2c1grp {
461 fsl,pins = <
462 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
463 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
464 >;
465 };
466
467 pinctrl_i2c1_gpio: i2c1gpiogrp {
468 fsl,pins = <
469 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
470 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
471 >;
472 };
473
474 pinctrl_i2c2: i2c2grp {
475 fsl,pins = <
476 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
477 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
478 >;
479 };
480
481 pinctrl_i2c2_gpio: i2c2gpiogrp {
482 fsl,pins = <
483 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2
484 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2
485 >;
486 };
487
488 pinctrl_i2c3: i2c3grp {
489 fsl,pins = <
490 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
491 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
492 >;
493 };
494
495 pinctrl_i2c3_gpio: i2c3gpiogrp {
496 fsl,pins = <
497 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2
498 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
499 >;
500 };
501
502 pinctrl_uart1: uart1grp {
503 fsl,pins = <
504 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
505 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
506 >;
507 };
508
509 pinctrl_uart2: uart2grp {
510 fsl,pins = <
511 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
512 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
513 >;
514 };
515
516 pinctrl_uart3: uart3grp {
517 fsl,pins = <
518 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
519 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
520 >;
521 };
522
523 pinctrl_usdhc1: usdhc1grp {
524 fsl,pins = <
525 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
526 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
527 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
528 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
529 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
530 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
531 >;
532 };
533
534 pinctrl_usdhc3: usdhc3grp {
535 fsl,pins = <
536 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
537 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
538 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
539 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
540 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
541 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
542 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
543 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
544 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
545 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
546 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
547 >;
548 };
549
550 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
551 fsl,pins = <
552 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
553 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
554 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
555 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
556 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
557 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
558 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
559 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
560 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
561 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
562 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
563 >;
564 };
565
566 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
567 fsl,pins = <
568 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
569 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
570 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
571 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
572 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
573 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
574 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
575 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
576 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
577 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
578 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
579 >;
580 };
581
582 pinctrl_wdog: wdoggrp {
583 fsl,pins = <
584 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
585 >;
586 };
587};