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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / freescale / imx8mp-beacon-som.dtsi
blob: 8be251b6937891bfbd38ebdb14f38f4bbdb87b26 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks
4 */
5
6/ {
7 aliases {
8 rtc0 = &rtc;
9 rtc1 = &snvs_rtc;
10 };
11
12 memory@40000000 {
13 device_type = "memory";
14 reg = <0x0 0x40000000 0 0xc0000000>,
15 <0x1 0x00000000 0 0xc0000000>;
16 };
17
18 reg_wl_bt: regulator-wifi-bt {
19 compatible = "regulator-fixed";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_reg_wl_bt>;
22 regulator-name = "wl-bt-pow-dwn";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
25 gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
26 startup-delay-us = <70000>;
27 regulator-always-on;
28 };
29};
30
31&A53_0 {
32 cpu-supply = <&buck2>;
33};
34
35&A53_1 {
36 cpu-supply = <&buck2>;
37};
38
39&A53_2 {
40 cpu-supply = <&buck2>;
41};
42
43&A53_3 {
44 cpu-supply = <&buck2>;
45};
46
47&eqos {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_eqos>;
50 phy-mode = "rgmii-id";
51 phy-handle = <&ethphy0>;
52 snps,force_thresh_dma_mode;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]53 snps,mtl-rx-config = <&mtl_rx_setup>;
54 snps,mtl-tx-config = <&mtl_tx_setup>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]55 status = "okay";
56
57 mdio {
58 compatible = "snps,dwmac-mdio";
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 ethphy0: ethernet-phy@3 {
63 compatible = "ethernet-phy-id0022.1640",
64 "ethernet-phy-ieee802.3-c22";
65 reg = <3>;
66 reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
67 interrupt-parent = <&gpio1>;
68 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
69 };
70 };
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]71
72 mtl_rx_setup: rx-queues-config {
73 snps,rx-queues-to-use = <5>;
74 snps,rx-sched-sp;
75
76 queue0 {
77 snps,dcb-algorithm;
78 snps,priority = <0x1>;
79 snps,map-to-dma-channel = <0>;
80 };
81
82 queue1 {
83 snps,dcb-algorithm;
84 snps,priority = <0x2>;
85 snps,map-to-dma-channel = <1>;
86 };
87
88 queue2 {
89 snps,dcb-algorithm;
90 snps,priority = <0x4>;
91 snps,map-to-dma-channel = <2>;
92 };
93
94 queue3 {
95 snps,dcb-algorithm;
96 snps,priority = <0x8>;
97 snps,map-to-dma-channel = <3>;
98 };
99
100 queue4 {
101 snps,dcb-algorithm;
102 snps,priority = <0xf0>;
103 snps,map-to-dma-channel = <4>;
104 };
105 };
106
107 mtl_tx_setup: tx-queues-config {
108 snps,tx-queues-to-use = <5>;
109 snps,tx-sched-sp;
110
111 queue0 {
112 snps,dcb-algorithm;
113 snps,priority = <0x1>;
114 };
115
116 queue1 {
117 snps,dcb-algorithm;
118 snps,priority = <0x2>;
119 };
120
121 queue2 {
122 snps,dcb-algorithm;
123 snps,priority = <0x4>;
124 };
125
126 queue3 {
127 snps,dcb-algorithm;
128 snps,priority = <0x8>;
129 };
130
131 queue4 {
132 snps,dcb-algorithm;
133 snps,priority = <0xf0>;
134 };
135 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]136};
137
138&flexspi {
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_flexspi0>;
141 status = "okay";
142
143 flash0: flash@0 {
144 compatible = "jedec,spi-nor";
145 reg = <0>;
146 spi-max-frequency = <80000000>;
147 spi-tx-bus-width = <1>;
148 spi-rx-bus-width = <4>;
149 };
150};
151
152&i2c1 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c1>;
155 clock-frequency = <384000>;
156 status = "okay";
157
158 pmic@25 {
159 compatible = "nxp,pca9450c";
160 reg = <0x25>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_pmic>;
163 interrupt-parent = <&gpio1>;
164 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
165
166 regulators {
167 buck1: BUCK1 {
168 regulator-name = "BUCK1";
169 regulator-min-microvolt = <600000>;
170 regulator-max-microvolt = <2187500>;
171 regulator-boot-on;
172 regulator-always-on;
173 regulator-ramp-delay = <3125>;
174 };
175
176 buck2: BUCK2 {
177 regulator-name = "BUCK2";
178 regulator-min-microvolt = <600000>;
179 regulator-max-microvolt = <2187500>;
180 regulator-boot-on;
181 regulator-always-on;
182 regulator-ramp-delay = <3125>;
183 nxp,dvs-run-voltage = <950000>;
184 nxp,dvs-standby-voltage = <850000>;
185 };
186
187 buck4: BUCK4 {
188 regulator-name = "BUCK4";
189 regulator-min-microvolt = <3300000>;
190 regulator-max-microvolt = <3300000>;
191 regulator-boot-on;
192 regulator-always-on;
193 };
194
195 buck5: BUCK5 {
196 regulator-name = "BUCK5";
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <1800000>;
199 regulator-boot-on;
200 regulator-always-on;
201 };
202
203 buck6: BUCK6 {
204 regulator-name = "BUCK6";
205 regulator-min-microvolt = <600000>;
206 regulator-max-microvolt = <3400000>;
207 regulator-boot-on;
208 regulator-always-on;
209 };
210
211 ldo1: LDO1 {
212 regulator-name = "LDO1";
213 regulator-min-microvolt = <1600000>;
214 regulator-max-microvolt = <1800000>;
215 regulator-boot-on;
216 regulator-always-on;
217 };
218
219 ldo3: LDO3 {
220 regulator-name = "LDO3";
221 regulator-min-microvolt = <800000>;
222 regulator-max-microvolt = <1800000>;
223 regulator-boot-on;
224 regulator-always-on;
225 };
226
227 ldo4: LDO4 {
228 regulator-name = "LDO4";
229 regulator-min-microvolt = <800000>;
230 regulator-max-microvolt = <3300000>;
231 regulator-boot-on;
232 regulator-always-on;
233 };
234
235 ldo5: LDO5 {
236 regulator-name = "LDO5";
237 regulator-min-microvolt = <1800000>;
238 regulator-max-microvolt = <3300000>;
239 regulator-boot-on;
240 regulator-always-on;
241 };
242 };
243 };
244};
245
246&i2c3 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_i2c3>;
249 clock-frequency = <384000>;
250 status = "okay";
251
252 eeprom@50 {
253 compatible = "atmel,24c64";
254 reg = <0x50>;
255 pagesize = <32>;
256 read-only; /* Manufacturing EEPROM programmed at factory */
257 };
258
259 rtc: rtc@51 {
260 compatible = "nxp,pcf85263";
261 reg = <0x51>;
262 };
263};
264
265&snvs_pwrkey {
266 status = "okay";
267};
268
269&uart1 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_uart1>;
272 assigned-clocks = <&clk IMX8MP_CLK_UART1>;
273 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
274 uart-has-rtscts;
275 status = "okay";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]276
277 bluetooth {
278 compatible = "nxp,88w8997-bt";
279 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]280};
281
282&usdhc1 {
283 pinctrl-names = "default", "state_100mhz", "state_200mhz";
284 pinctrl-0 = <&pinctrl_usdhc1>;
285 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
286 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
287 bus-width = <4>;
288 vmmc-supply = <&reg_wl_bt>;
289 cap-sd-highspeed;
290 sd-uhs-sdr50;
291 sd-uhs-sdr104;
292 keep-power-in-suspend;
293 wakeup-source;
294 non-removable;
295 cap-power-off-card;
296 #address-cells = <1>;
297 #size-cells = <0>;
298 status = "okay";
299
300 mwifiex: wifi@1 {
301 compatible = "marvell,sd8997";
302 reg = <1>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_wlan>;
305 interrupt-parent = <&gpio2>;
306 interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
307 };
308};
309
310&usdhc3 {
311 pinctrl-names = "default", "state_100mhz", "state_200mhz";
312 pinctrl-0 = <&pinctrl_usdhc3>;
313 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
314 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
315 bus-width = <8>;
316 non-removable;
317 status = "okay";
318};
319
320&wdog1 {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_wdog>;
323 fsl,ext-reset-output;
324 status = "okay";
325};
326
327&iomuxc {
328 pinctrl_eqos: eqosgrp {
329 fsl,pins = <
330 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
331 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
332 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
333 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
334 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
335 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
336 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
337 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
338 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
339 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
340 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
341 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
342 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
343 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
344 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
345 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10
346 >;
347 };
348
349 pinctrl_flexspi0: flexspi0grp {
350 fsl,pins = <
351 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
352 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
353 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
354 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
355 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
356 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
357 >;
358 };
359
360 pinctrl_i2c1: i2c1grp {
361 fsl,pins = <
362 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
363 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
364 >;
365 };
366
367 pinctrl_i2c3: i2c3grp {
368 fsl,pins = <
369 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
370 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
371 >;
372 };
373
374 pinctrl_pmic: pmicgrp {
375 fsl,pins = <
376 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
377 >;
378 };
379
380 pinctrl_reg_wl_bt: reg-wl-btgrp {
381 fsl,pins = <
382 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
383 >;
384 };
385
386 pinctrl_uart1: uart1grp {
387 fsl,pins = <
388 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
389 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
390 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
391 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
392 >;
393 };
394
395 pinctrl_usdhc1: usdhc1grp {
396 fsl,pins = <
397 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
398 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
399 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
400 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
401 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
402 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
403 >;
404 };
405
406 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
407 fsl,pins = <
408 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
409 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
410 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
411 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
412 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
413 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
414 >;
415 };
416
417 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
418 fsl,pins = <
419 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
420 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
421 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
422 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
423 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
424 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
425 >;
426 };
427
428 pinctrl_usdhc3: usdhc3grp {
429 fsl,pins = <
430 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
431 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
432 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
433 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
434 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
435 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
436 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
437 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
438 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
439 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
440 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
441 >;
442 };
443
444 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
445 fsl,pins = <
446 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
447 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
448 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
449 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
450 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
451 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
452 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
453 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
454 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
455 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
456 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
457 >;
458 };
459
460 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
461 fsl,pins = <
462 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
463 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
464 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
465 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
466 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
467 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
468 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
469 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
470 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
471 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
472 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
473 >;
474 };
475
476 pinctrl_wdog: wdoggrp {
477 fsl,pins = <
478 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
479 >;
480 };
481
482 pinctrl_wlan: wlangrp {
483 fsl,pins = <
484 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140
485 >;
486 };
487};