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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / freescale / imx8mm-venice-gw7904.dts
blob: 05489a31e7fd8d85efb36a75b1c341705bb95676 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12
13#include "imx8mm.dtsi"
14
15/ {
16 model = "Gateworks Venice GW7904 i.MX8MM board";
17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
18
19 chosen {
20 stdout-path = &uart2;
21 };
22
23 memory@40000000 {
24 device_type = "memory";
25 reg = <0x0 0x40000000 0 0x80000000>;
26 };
27
28 gpio-keys {
29 compatible = "gpio-keys";
30
31 key-0 {
32 label = "user_pb";
33 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
34 linux,code = <BTN_0>;
35 };
36
37 key-1 {
38 label = "user_pb1x";
39 linux,code = <BTN_1>;
40 interrupt-parent = <&gsc>;
41 interrupts = <0>;
42 };
43
44 key-2 {
45 label = "key_erased";
46 linux,code = <BTN_2>;
47 interrupt-parent = <&gsc>;
48 interrupts = <1>;
49 };
50
51 key-3 {
52 label = "eeprom_wp";
53 linux,code = <BTN_3>;
54 interrupt-parent = <&gsc>;
55 interrupts = <2>;
56 };
57
58 key-4 {
59 label = "switch_hold";
60 linux,code = <BTN_5>;
61 interrupt-parent = <&gsc>;
62 interrupts = <7>;
63 };
64 };
65
66 led-controller {
67 compatible = "gpio-leds";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_gpio_leds>;
70
71 led-0 {
72 function = LED_FUNCTION_STATUS;
73 color = <LED_COLOR_ID_GREEN>;
74 label = "led01_grn";
75 gpios = <&gpioled 0 GPIO_ACTIVE_LOW>;
76 default-state = "off";
77 };
78
79 led-1 {
80 function = LED_FUNCTION_STATUS;
81 color = <LED_COLOR_ID_YELLOW>;
82 label = "led01_yel";
83 gpios = <&gpioled 1 GPIO_ACTIVE_LOW>;
84 default-state = "off";
85 };
86
87 led-2 {
88 function = LED_FUNCTION_STATUS;
89 color = <LED_COLOR_ID_GREEN>;
90 label = "led02_grn";
91 gpios = <&gpioled 2 GPIO_ACTIVE_LOW>;
92 default-state = "off";
93 };
94
95 led-3 {
96 function = LED_FUNCTION_STATUS;
97 color = <LED_COLOR_ID_YELLOW>;
98 label = "led02_yel";
99 gpios = <&gpioled 3 GPIO_ACTIVE_LOW>;
100 default-state = "off";
101 };
102
103 led-4 {
104 function = LED_FUNCTION_STATUS;
105 color = <LED_COLOR_ID_GREEN>;
106 label = "led03_grn";
107 gpios = <&gpioled 4 GPIO_ACTIVE_LOW>;
108 default-state = "off";
109 };
110
111 led-5 {
112 function = LED_FUNCTION_STATUS;
113 color = <LED_COLOR_ID_YELLOW>;
114 label = "led03_yel";
115 gpios = <&gpioled 5 GPIO_ACTIVE_LOW>;
116 default-state = "off";
117 };
118
119 led-6 {
120 function = LED_FUNCTION_STATUS;
121 color = <LED_COLOR_ID_GREEN>;
122 label = "led04_grn";
123 gpios = <&gpioled 6 GPIO_ACTIVE_LOW>;
124 default-state = "off";
125 };
126
127 led-7 {
128 function = LED_FUNCTION_STATUS;
129 color = <LED_COLOR_ID_YELLOW>;
130 label = "led04_yel";
131 gpios = <&gpioled 7 GPIO_ACTIVE_LOW>;
132 default-state = "off";
133 };
134
135 led-8 {
136 function = LED_FUNCTION_STATUS;
137 color = <LED_COLOR_ID_GREEN>;
138 label = "led05_grn";
139 gpios = <&gpioled 8 GPIO_ACTIVE_LOW>;
140 default-state = "off";
141 };
142
143 led-9 {
144 function = LED_FUNCTION_STATUS;
145 color = <LED_COLOR_ID_YELLOW>;
146 label = "led05_yel";
147 gpios = <&gpioled 9 GPIO_ACTIVE_LOW>;
148 default-state = "off";
149 };
150
151 led-10 {
152 function = LED_FUNCTION_STATUS;
153 color = <LED_COLOR_ID_GREEN>;
154 label = "led06_grn";
155 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
156 default-state = "off";
157 };
158
159 led-11 {
160 function = LED_FUNCTION_STATUS;
161 color = <LED_COLOR_ID_RED>;
162 label = "led06_red";
163 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
164 default-state = "off";
165 };
166
167 led-12 {
168 function = LED_FUNCTION_STATUS;
169 color = <LED_COLOR_ID_GREEN>;
170 label = "led07_grn";
171 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
172 default-state = "off";
173 };
174
175 led-13 {
176 function = LED_FUNCTION_STATUS;
177 color = <LED_COLOR_ID_RED>;
178 label = "led07_red";
179 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
180 default-state = "off";
181 };
182
183 led-14 {
184 function = LED_FUNCTION_STATUS;
185 color = <LED_COLOR_ID_GREEN>;
186 label = "led08_grn";
187 gpios = <&gpioled 10 GPIO_ACTIVE_LOW>;
188 default-state = "off";
189 };
190
191 led-15 {
192 function = LED_FUNCTION_STATUS;
193 color = <LED_COLOR_ID_YELLOW>;
194 label = "led08_yel";
195 gpios = <&gpioled 11 GPIO_ACTIVE_LOW>;
196 default-state = "off";
197 };
198
199 led-16 {
200 function = LED_FUNCTION_STATUS;
201 color = <LED_COLOR_ID_GREEN>;
202 label = "led09_grn";
203 gpios = <&gpioled 12 GPIO_ACTIVE_LOW>;
204 default-state = "off";
205 };
206
207 led-17 {
208 function = LED_FUNCTION_STATUS;
209 color = <LED_COLOR_ID_YELLOW>;
210 label = "led09_yel";
211 gpios = <&gpioled 13 GPIO_ACTIVE_LOW>;
212 default-state = "off";
213 };
214
215 led-18 {
216 function = LED_FUNCTION_STATUS;
217 color = <LED_COLOR_ID_GREEN>;
218 label = "led10_grn";
219 gpios = <&gpioled 14 GPIO_ACTIVE_LOW>;
220 default-state = "off";
221 };
222
223 led-19 {
224 function = LED_FUNCTION_STATUS;
225 color = <LED_COLOR_ID_YELLOW>;
226 label = "led10_yel";
227 gpios = <&gpioled 15 GPIO_ACTIVE_LOW>;
228 default-state = "off";
229 };
230 };
231
232 pcie0_refclk: pcie0-refclk {
233 compatible = "fixed-clock";
234 #clock-cells = <0>;
235 clock-frequency = <100000000>;
236 };
237
238 reg_3p3v: regulator-3p3v {
239 compatible = "regulator-fixed";
240 regulator-name = "3P3V";
241 regulator-min-microvolt = <3300000>;
242 regulator-max-microvolt = <3300000>;
243 regulator-always-on;
244 };
245};
246
247&A53_0 {
248 cpu-supply = <&buck2>;
249};
250
251&A53_1 {
252 cpu-supply = <&buck2>;
253};
254
255&A53_2 {
256 cpu-supply = <&buck2>;
257};
258
259&A53_3 {
260 cpu-supply = <&buck2>;
261};
262
263&ddrc {
264 operating-points-v2 = <&ddrc_opp_table>;
265
266 ddrc_opp_table: opp-table {
267 compatible = "operating-points-v2";
268
269 opp-25000000 {
270 opp-hz = /bits/ 64 <25000000>;
271 };
272
273 opp-100000000 {
274 opp-hz = /bits/ 64 <100000000>;
275 };
276
277 opp-750000000 {
278 opp-hz = /bits/ 64 <750000000>;
279 };
280 };
281};
282
283&fec1 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_fec1>;
286 phy-mode = "rgmii-id";
287 phy-handle = <&ethphy0>;
288 local-mac-address = [00 00 00 00 00 00];
289 status = "okay";
290
291 mdio {
292 #address-cells = <1>;
293 #size-cells = <0>;
294
295 ethphy0: ethernet-phy@0 {
296 compatible = "ethernet-phy-ieee802.3-c22";
297 reg = <0>;
298 };
299 };
300};
301
302&gpio1 {
303 gpio-line-names = "", "", "", "", "", "", "", "",
304 "", "", "", "", "rs232_en#", "", "", "",
305 "", "", "", "", "", "", "", "",
306 "", "", "", "", "", "", "", "";
307};
308
309&gpio5 {
310 gpio-line-names = "", "", "", "", "", "", "", "",
311 "", "", "", "", "pci_wdis#", "", "", "",
312 "", "", "", "", "", "", "", "",
313 "", "", "", "", "", "", "", "";
314};
315
316&i2c1 {
317 clock-frequency = <100000>;
318 pinctrl-names = "default", "gpio";
319 pinctrl-0 = <&pinctrl_i2c1>;
320 pinctrl-1 = <&pinctrl_i2c1_gpio>;
321 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
322 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
323 status = "okay";
324
325 gsc: gsc@20 {
326 compatible = "gw,gsc";
327 reg = <0x20>;
328 pinctrl-0 = <&pinctrl_gsc>;
329 interrupt-parent = <&gpio4>;
330 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
331 interrupt-controller;
332 #interrupt-cells = <1>;
333 #address-cells = <1>;
334 #size-cells = <0>;
335
336 adc {
337 compatible = "gw,gsc-adc";
338 #address-cells = <1>;
339 #size-cells = <0>;
340
341 channel@6 {
342 gw,mode = <0>;
343 reg = <0x06>;
344 label = "temp";
345 };
346
347 channel@82 {
348 gw,mode = <2>;
349 reg = <0x82>;
350 label = "vin";
351 gw,voltage-divider-ohms = <22100 1000>;
352 gw,voltage-offset-microvolt = <700000>;
353 };
354
355 channel@84 {
356 gw,mode = <2>;
357 reg = <0x84>;
358 label = "vdd_5p0";
359 gw,voltage-divider-ohms = <10000 10000>;
360 };
361
362 channel@86 {
363 gw,mode = <2>;
364 reg = <0x86>;
365 label = "vdd_3p3";
366 gw,voltage-divider-ohms = <10000 10000>;
367 };
368
369 channel@88 {
370 gw,mode = <2>;
371 reg = <0x88>;
372 label = "vdd_0p9";
373 };
374
375 channel@8c {
376 gw,mode = <2>;
377 reg = <0x8c>;
378 label = "vdd_soc";
379 };
380
381 channel@8e {
382 gw,mode = <2>;
383 reg = <0x8e>;
384 label = "vdd_arm";
385 };
386
387 channel@90 {
388 gw,mode = <2>;
389 reg = <0x90>;
390 label = "vdd_1p8";
391 };
392
393 channel@92 {
394 gw,mode = <2>;
395 reg = <0x92>;
396 label = "vdd_dram";
397 };
398
399 channel@a2 {
400 gw,mode = <2>;
401 reg = <0xa2>;
402 label = "vdd_gsc";
403 gw,voltage-divider-ohms = <10000 10000>;
404 };
405 };
406 };
407
408 gpio: gpio@23 {
409 compatible = "nxp,pca9555";
410 reg = <0x23>;
411 gpio-controller;
412 #gpio-cells = <2>;
413 interrupt-parent = <&gsc>;
414 interrupts = <4>;
415 };
416
417 eeprom@50 {
418 compatible = "atmel,24c02";
419 reg = <0x50>;
420 pagesize = <16>;
421 };
422
423 eeprom@51 {
424 compatible = "atmel,24c02";
425 reg = <0x51>;
426 pagesize = <16>;
427 };
428
429 eeprom@52 {
430 compatible = "atmel,24c02";
431 reg = <0x52>;
432 pagesize = <16>;
433 };
434
435 eeprom@53 {
436 compatible = "atmel,24c02";
437 reg = <0x53>;
438 pagesize = <16>;
439 };
440
441 rtc@68 {
442 compatible = "dallas,ds1672";
443 reg = <0x68>;
444 };
445};
446
447&i2c2 {
448 clock-frequency = <400000>;
449 pinctrl-names = "default", "gpio";
450 pinctrl-0 = <&pinctrl_i2c2>;
451 pinctrl-1 = <&pinctrl_i2c2_gpio>;
452 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
453 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
454 status = "okay";
455
456 pmic@4b {
457 compatible = "rohm,bd71847";
458 reg = <0x4b>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_pmic>;
461 interrupt-parent = <&gpio3>;
462 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
463 rohm,reset-snvs-powered;
464 #clock-cells = <0>;
465 clocks = <&osc_32k>;
466 clock-output-names = "clk-32k-out";
467
468 regulators {
469 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
470 BUCK1 {
471 regulator-name = "buck1";
472 regulator-min-microvolt = <700000>;
473 regulator-max-microvolt = <1300000>;
474 regulator-boot-on;
475 regulator-always-on;
476 regulator-ramp-delay = <1250>;
477 };
478
479 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
480 buck2: BUCK2 {
481 regulator-name = "buck2";
482 regulator-min-microvolt = <700000>;
483 regulator-max-microvolt = <1300000>;
484 regulator-boot-on;
485 regulator-always-on;
486 regulator-ramp-delay = <1250>;
487 rohm,dvs-run-voltage = <1000000>;
488 rohm,dvs-idle-voltage = <900000>;
489 };
490
491 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
492 BUCK3 {
493 regulator-name = "buck3";
494 regulator-min-microvolt = <700000>;
495 regulator-max-microvolt = <1350000>;
496 regulator-boot-on;
497 regulator-always-on;
498 };
499
500 /* vdd_3p3 */
501 BUCK4 {
502 regulator-name = "buck4";
503 regulator-min-microvolt = <3000000>;
504 regulator-max-microvolt = <3300000>;
505 regulator-boot-on;
506 regulator-always-on;
507 };
508
509 /* vdd_1p8 */
510 BUCK5 {
511 regulator-name = "buck5";
512 regulator-min-microvolt = <1605000>;
513 regulator-max-microvolt = <1995000>;
514 regulator-boot-on;
515 regulator-always-on;
516 };
517
518 /* vdd_dram */
519 BUCK6 {
520 regulator-name = "buck6";
521 regulator-min-microvolt = <800000>;
522 regulator-max-microvolt = <1400000>;
523 regulator-boot-on;
524 regulator-always-on;
525 };
526
527 /* nvcc_snvs_1p8 */
528 LDO1 {
529 regulator-name = "ldo1";
530 regulator-min-microvolt = <1600000>;
531 regulator-max-microvolt = <1900000>;
532 regulator-boot-on;
533 regulator-always-on;
534 };
535
536 /* vdd_snvs_0p8 */
537 LDO2 {
538 regulator-name = "ldo2";
539 regulator-min-microvolt = <800000>;
540 regulator-max-microvolt = <900000>;
541 regulator-boot-on;
542 regulator-always-on;
543 };
544
545 /* vdda_1p8 */
546 LDO3 {
547 regulator-name = "ldo3";
548 regulator-min-microvolt = <1800000>;
549 regulator-max-microvolt = <3300000>;
550 regulator-boot-on;
551 regulator-always-on;
552 };
553
554 LDO4 {
555 regulator-name = "ldo4";
556 regulator-min-microvolt = <900000>;
557 regulator-max-microvolt = <1800000>;
558 regulator-boot-on;
559 regulator-always-on;
560 };
561
562 LDO6 {
563 regulator-name = "ldo6";
564 regulator-min-microvolt = <900000>;
565 regulator-max-microvolt = <1800000>;
566 regulator-boot-on;
567 regulator-always-on;
568 };
569 };
570 };
571};
572
573&i2c3 {
574 clock-frequency = <400000>;
575 pinctrl-names = "default", "gpio";
576 pinctrl-0 = <&pinctrl_i2c3>;
577 pinctrl-1 = <&pinctrl_i2c3_gpio>;
578 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
579 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
580 status = "okay";
581
582 accelerometer@19 {
583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_accel>;
585 compatible = "st,lis2de12";
586 reg = <0x19>;
587 st,drdy-int-pin = <1>;
588 interrupt-parent = <&gpio1>;
589 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
590 };
591};
592
593&i2c4 {
594 clock-frequency = <400000>;
595 pinctrl-names = "default", "gpio";
596 pinctrl-0 = <&pinctrl_i2c4>;
597 pinctrl-1 = <&pinctrl_i2c4_gpio>;
598 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
599 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
600 status = "okay";
601
602 gpioled: gpio@27 {
603 compatible = "nxp,pca9555";
604 reg = <0x27>;
605 gpio-controller;
606 #gpio-cells = <2>;
607 };
608};
609
610&pcie_phy {
611 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
612 fsl,clkreq-unsupported;
613 clocks = <&pcie0_refclk>;
614 clock-names = "ref";
615 status = "okay";
616};
617
618&pcie0 {
619 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_pcie0>;
621 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
622 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
623 <&clk IMX8MM_CLK_PCIE1_AUX>;
624 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
625 <&clk IMX8MM_CLK_PCIE1_CTRL>;
626 assigned-clock-rates = <10000000>, <250000000>;
627 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
628 <&clk IMX8MM_SYS_PLL2_250M>;
629 status = "okay";
630};
631
632&disp_blk_ctrl {
633 status = "disabled";
634};
635
636&pgc_mipi {
637 status = "disabled";
638};
639
640/* off-board RS232 */
641&uart1 {
642 pinctrl-names = "default";
643 pinctrl-0 = <&pinctrl_uart1>;
644 cts-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
645 rts-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
646 status = "okay";
647};
648
649/* console */
650&uart2 {
651 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_uart2>;
653 status = "okay";
654};
655
656&usbotg1 {
657 dr_mode = "host";
658 disable-over-current;
659 status = "okay";
660};
661
662/* microSD */
663&usdhc2 {
664 pinctrl-names = "default", "state_100mhz", "state_200mhz";
665 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
666 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
667 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
668 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
669 bus-width = <4>;
670 vmmc-supply = <&reg_3p3v>;
671 status = "okay";
672};
673
674/* eMMC */
675&usdhc3 {
676 pinctrl-names = "default", "state_100mhz", "state_200mhz";
677 pinctrl-0 = <&pinctrl_usdhc3>;
678 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
679 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
680 bus-width = <8>;
681 non-removable;
682 status = "okay";
683};
684
685&wdog1 {
686 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_wdog>;
688 fsl,ext-reset-output;
689 status = "okay";
690};
691
692&iomuxc {
693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_hog>;
695
696 pinctrl_hog: hoggrp {
697 fsl,pins = <
698 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
699 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
700 >;
701 };
702
703 pinctrl_accel: accelgrp {
704 fsl,pins = <
705 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
706 >;
707 };
708
709 pinctrl_fec1: fec1grp {
710 fsl,pins = <
711 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
712 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
713 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
714 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
715 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
716 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
717 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
718 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
719 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
720 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
721 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
722 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
723 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
724 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
725 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
726 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
727 >;
728 };
729
730 pinctrl_gpio_leds: gpioledsgrp {
731 fsl,pins = <
732 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019
733 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019
734 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019
735 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019
736 >;
737 };
738
739 pinctrl_gsc: gscgrp {
740 fsl,pins = <
741 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
742 >;
743 };
744
745 pinctrl_i2c1: i2c1grp {
746 fsl,pins = <
747 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
748 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
749 >;
750 };
751
752 pinctrl_i2c1_gpio: i2c1gpiogrp {
753 fsl,pins = <
754 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
755 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
756 >;
757 };
758
759 pinctrl_i2c2: i2c2grp {
760 fsl,pins = <
761 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
762 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
763 >;
764 };
765
766 pinctrl_i2c2_gpio: i2c2gpiogrp {
767 fsl,pins = <
768 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
769 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
770 >;
771 };
772
773 pinctrl_i2c3: i2c3grp {
774 fsl,pins = <
775 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
776 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
777 >;
778 };
779
780 pinctrl_i2c3_gpio: i2c3gpiogrp {
781 fsl,pins = <
782 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
783 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
784 >;
785 };
786
787 pinctrl_i2c4: i2c4grp {
788 fsl,pins = <
789 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
790 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
791 >;
792 };
793
794 pinctrl_i2c4_gpio: i2c4gpiogrp {
795 fsl,pins = <
796 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
797 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
798 >;
799 };
800
801 pinctrl_pcie0: pciegrp {
802 fsl,pins = <
803 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
804 >;
805 };
806
807 pinctrl_pmic: pmicgrp {
808 fsl,pins = <
809 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
810 >;
811 };
812
813 pinctrl_uart1: uart1grp {
814 fsl,pins = <
815 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
816 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
817 MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x140 /* CTS# in */
818 MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x140 /* RTS# out */
819 >;
820 };
821
822 pinctrl_uart2: uart2grp {
823 fsl,pins = <
824 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
825 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
826 >;
827 };
828
829 pinctrl_usdhc2: usdhc2grp {
830 fsl,pins = <
831 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
832 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
833 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
834 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
835 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
836 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
837 >;
838 };
839
840 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
841 fsl,pins = <
842 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
843 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
844 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
845 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
846 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
847 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
848 >;
849 };
850
851 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
852 fsl,pins = <
853 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
854 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
855 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
856 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
857 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
858 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
859 >;
860 };
861
862 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
863 fsl,pins = <
864 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
865 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
866 >;
867 };
868
869 pinctrl_usdhc3: usdhc3grp {
870 fsl,pins = <
871 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
872 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
873 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
874 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
875 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
876 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
877 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
878 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
879 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
880 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
881 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
882 >;
883 };
884
885 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
886 fsl,pins = <
887 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
888 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
889 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
890 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
891 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
892 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
893 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
894 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
895 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
896 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
897 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
898 >;
899 };
900
901 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
902 fsl,pins = <
903 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
904 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
905 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
906 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
907 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
908 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
909 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
910 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
911 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
912 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
913 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
914 >;
915 };
916
917 pinctrl_wdog: wdoggrp {
918 fsl,pins = <
919 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
920 >;
921 };
922};