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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / amd / elba-16core.dtsi
blob: 6c1b7b8fe35473d6a34883a48fdbe32db64d0d8b [file] [log] [blame]
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2/*
3 * Copyright 2020-2023 Advanced Micro Devices, Inc.
4 */
5
6/ {
7 cpus {
8 #address-cells = <1>;
9 #size-cells = <0>;
10
11 cpu-map {
12 cluster0 {
13 core0 { cpu = <&cpu0>; };
14 core1 { cpu = <&cpu1>; };
15 core2 { cpu = <&cpu2>; };
16 core3 { cpu = <&cpu3>; };
17 };
18
19 cluster1 {
20 core0 { cpu = <&cpu4>; };
21 core1 { cpu = <&cpu5>; };
22 core2 { cpu = <&cpu6>; };
23 core3 { cpu = <&cpu7>; };
24 };
25
26 cluster2 {
27 core0 { cpu = <&cpu8>; };
28 core1 { cpu = <&cpu9>; };
29 core2 { cpu = <&cpu10>; };
30 core3 { cpu = <&cpu11>; };
31 };
32
33 cluster3 {
34 core0 { cpu = <&cpu12>; };
35 core1 { cpu = <&cpu13>; };
36 core2 { cpu = <&cpu14>; };
37 core3 { cpu = <&cpu15>; };
38 };
39 };
40
41 /* CLUSTER 0 */
42 cpu0: cpu@0 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a72";
45 reg = <0x0>;
46 next-level-cache = <&l2_0>;
47 enable-method = "psci";
48 };
49
50 cpu1: cpu@1 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a72";
53 reg = <0x1>;
54 next-level-cache = <&l2_0>;
55 enable-method = "psci";
56 };
57
58 cpu2: cpu@2 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a72";
61 reg = <0x2>;
62 next-level-cache = <&l2_0>;
63 enable-method = "psci";
64 };
65
66 cpu3: cpu@3 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a72";
69 reg = <0x3>;
70 next-level-cache = <&l2_0>;
71 enable-method = "psci";
72 };
73
74 l2_0: l2-cache0 {
75 compatible = "cache";
76 cache-unified;
77 cache-level = <2>;
78 };
79
80 /* CLUSTER 1 */
81 cpu4: cpu@100 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a72";
84 reg = <0x100>;
85 next-level-cache = <&l2_1>;
86 enable-method = "psci";
87 };
88
89 cpu5: cpu@101 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a72";
92 reg = <0x101>;
93 next-level-cache = <&l2_1>;
94 enable-method = "psci";
95 };
96
97 cpu6: cpu@102 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a72";
100 reg = <0x102>;
101 next-level-cache = <&l2_1>;
102 enable-method = "psci";
103 };
104
105 cpu7: cpu@103 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a72";
108 reg = <0x103>;
109 next-level-cache = <&l2_1>;
110 enable-method = "psci";
111 };
112
113 l2_1: l2-cache1 {
114 compatible = "cache";
115 cache-unified;
116 cache-level = <2>;
117 };
118
119 /* CLUSTER 2 */
120 cpu8: cpu@200 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a72";
123 reg = <0x200>;
124 next-level-cache = <&l2_2>;
125 enable-method = "psci";
126 };
127
128 cpu9: cpu@201 {
129 device_type = "cpu";
130 compatible = "arm,cortex-a72";
131 reg = <0x201>;
132 next-level-cache = <&l2_2>;
133 enable-method = "psci";
134 };
135
136 cpu10: cpu@202 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a72";
139 reg = <0x202>;
140 next-level-cache = <&l2_2>;
141 enable-method = "psci";
142 };
143
144 cpu11: cpu@203 {
145 device_type = "cpu";
146 compatible = "arm,cortex-a72";
147 reg = <0x203>;
148 next-level-cache = <&l2_2>;
149 enable-method = "psci";
150 };
151
152 l2_2: l2-cache2 {
153 compatible = "cache";
154 cache-unified;
155 cache-level = <2>;
156 };
157
158 /* CLUSTER 3 */
159 cpu12: cpu@300 {
160 device_type = "cpu";
161 compatible = "arm,cortex-a72";
162 reg = <0x300>;
163 next-level-cache = <&l2_3>;
164 enable-method = "psci";
165 };
166
167 cpu13: cpu@301 {
168 device_type = "cpu";
169 compatible = "arm,cortex-a72";
170 reg = <0x301>;
171 next-level-cache = <&l2_3>;
172 enable-method = "psci";
173 };
174
175 cpu14: cpu@302 {
176 device_type = "cpu";
177 compatible = "arm,cortex-a72";
178 reg = <0x302>;
179 next-level-cache = <&l2_3>;
180 enable-method = "psci";
181 };
182
183 cpu15: cpu@303 {
184 device_type = "cpu";
185 compatible = "arm,cortex-a72";
186 reg = <0x303>;
187 next-level-cache = <&l2_3>;
188 enable-method = "psci";
189 };
190
191 l2_3: l2-cache3 {
192 compatible = "cache";
193 cache-unified;
194 cache-level = <2>;
195 };
196 };
197};