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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / renesas / r8a7778.dtsi
blob: b80e832c92775756c8d964221363505d0dccdb5f [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
4 *
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 *
8 * based on r8a7779
9 *
10 * Copyright (C) 2013 Renesas Solutions Corp.
11 * Copyright (C) 2013 Simon Horman
12 */
13
14#include <dt-bindings/clock/r8a7778-clock.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/interrupt-controller/irq.h>
17
18/ {
19 compatible = "renesas,r8a7778";
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a9";
31 reg = <0>;
32 clock-frequency = <800000000>;
33 clocks = <&z_clk>;
34 };
35 };
36
37 aliases {
38 spi0 = &hspi0;
39 spi1 = &hspi1;
40 spi2 = &hspi2;
41 };
42
43 bsc: bus@1c000000 {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges = <0 0 0x1c000000>;
48 };
49
50 ether: ethernet@fde00000 {
51 compatible = "renesas,ether-r8a7778",
52 "renesas,rcar-gen1-ether";
53 reg = <0xfde00000 0x400>;
54 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
56 power-domains = <&cpg_clocks>;
57 phy-mode = "rmii";
58 #address-cells = <1>;
59 #size-cells = <0>;
60 status = "disabled";
61 };
62
63 gic: interrupt-controller@fe438000 {
64 compatible = "arm,pl390";
65 #interrupt-cells = <3>;
66 interrupt-controller;
67 reg = <0xfe438000 0x1000>,
68 <0xfe430000 0x100>;
69 };
70
71 /* irqpin: IRQ0 - IRQ3 */
72 irqpin: interrupt-controller@fe78001c {
73 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
74 #interrupt-cells = <2>;
75 interrupt-controller;
76 status = "disabled"; /* default off */
77 reg = <0xfe78001c 4>,
78 <0xfe780010 4>,
79 <0xfe780024 4>,
80 <0xfe780044 4>,
81 <0xfe780064 4>,
82 <0xfe780000 4>;
83 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
87 sense-bitfield-width = <2>;
88 };
89
90 gpio0: gpio@ffc40000 {
91 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
92 reg = <0xffc40000 0x2c>;
93 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
94 #gpio-cells = <2>;
95 gpio-controller;
96 gpio-ranges = <&pfc 0 0 32>;
97 #interrupt-cells = <2>;
98 interrupt-controller;
99 };
100
101 gpio1: gpio@ffc41000 {
102 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
103 reg = <0xffc41000 0x2c>;
104 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
105 #gpio-cells = <2>;
106 gpio-controller;
107 gpio-ranges = <&pfc 0 32 32>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 };
111
112 gpio2: gpio@ffc42000 {
113 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
114 reg = <0xffc42000 0x2c>;
115 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
116 #gpio-cells = <2>;
117 gpio-controller;
118 gpio-ranges = <&pfc 0 64 32>;
119 #interrupt-cells = <2>;
120 interrupt-controller;
121 };
122
123 gpio3: gpio@ffc43000 {
124 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
125 reg = <0xffc43000 0x2c>;
126 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
127 #gpio-cells = <2>;
128 gpio-controller;
129 gpio-ranges = <&pfc 0 96 32>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
132 };
133
134 gpio4: gpio@ffc44000 {
135 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
136 reg = <0xffc44000 0x2c>;
137 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
138 #gpio-cells = <2>;
139 gpio-controller;
140 gpio-ranges = <&pfc 0 128 27>;
141 #interrupt-cells = <2>;
142 interrupt-controller;
143 };
144
145 pfc: pinctrl@fffc0000 {
146 compatible = "renesas,pfc-r8a7778";
147 reg = <0xfffc0000 0x118>;
148 };
149
150 i2c0: i2c@ffc70000 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
154 reg = <0xffc70000 0x1000>;
155 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
157 power-domains = <&cpg_clocks>;
158 status = "disabled";
159 };
160
161 i2c1: i2c@ffc71000 {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
165 reg = <0xffc71000 0x1000>;
166 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
168 power-domains = <&cpg_clocks>;
169 i2c-scl-internal-delay-ns = <5>;
170 status = "disabled";
171 };
172
173 i2c2: i2c@ffc72000 {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
177 reg = <0xffc72000 0x1000>;
178 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
180 power-domains = <&cpg_clocks>;
181 i2c-scl-internal-delay-ns = <5>;
182 status = "disabled";
183 };
184
185 i2c3: i2c@ffc73000 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
189 reg = <0xffc73000 0x1000>;
190 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
192 power-domains = <&cpg_clocks>;
193 i2c-scl-internal-delay-ns = <5>;
194 status = "disabled";
195 };
196
197 tmu0: timer@ffd80000 {
198 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
199 reg = <0xffd80000 0x30>;
200 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]202 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
204 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]205 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
206 clock-names = "fck";
207 power-domains = <&cpg_clocks>;
208
209 #renesas,channels = <3>;
210
211 status = "disabled";
212 };
213
214 tmu1: timer@ffd81000 {
215 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
216 reg = <0xffd81000 0x30>;
217 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]219 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
221 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]222 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
223 clock-names = "fck";
224 power-domains = <&cpg_clocks>;
225
226 #renesas,channels = <3>;
227
228 status = "disabled";
229 };
230
231 tmu2: timer@ffd82000 {
232 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
233 reg = <0xffd82000 0x30>;
234 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]237 interrupt-names = "tuni0", "tuni1", "tuni2";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]238 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
239 clock-names = "fck";
240 power-domains = <&cpg_clocks>;
241
242 #renesas,channels = <3>;
243
244 status = "disabled";
245 };
246
247 rcar_sound: sound@ffd90000 {
248 /*
249 * #sound-dai-cells is required if simple-card
250 *
251 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
252 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
253 */
254 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
255 reg = <0xffd90000 0x1000>, /* SRU */
256 <0xffd91000 0x240>, /* SSI */
257 <0xfffe0000 0x24>; /* ADG */
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]258 reg-names = "sru", "ssi", "adg";
259
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]260 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
261 <&mstp3_clks R8A7778_CLK_SSI7>,
262 <&mstp3_clks R8A7778_CLK_SSI6>,
263 <&mstp3_clks R8A7778_CLK_SSI5>,
264 <&mstp3_clks R8A7778_CLK_SSI4>,
265 <&mstp0_clks R8A7778_CLK_SSI3>,
266 <&mstp0_clks R8A7778_CLK_SSI2>,
267 <&mstp0_clks R8A7778_CLK_SSI1>,
268 <&mstp0_clks R8A7778_CLK_SSI0>,
269 <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
270 <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
271 <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
272 <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
273 <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
274 <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
275 <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
276 <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
277 <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
278 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
279 <&cpg_clocks R8A7778_CLK_S1>;
280 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
281 "ssi.3", "ssi.2", "ssi.1", "ssi.0",
282 "src.8", "src.7", "src.6", "src.5", "src.4",
283 "src.3", "src.2", "src.1", "src.0",
284 "clk_a", "clk_b", "clk_c", "clk_i";
285
286 status = "disabled";
287
288 rcar_sound,src {
289 src3: src-3 { };
290 src4: src-4 { };
291 src5: src-5 { };
292 src6: src-6 { };
293 src7: src-7 { };
294 src8: src-8 { };
295 src9: src-9 { };
296 };
297
298 rcar_sound,ssi {
299 ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
300 ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
301 ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
302 ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
303 ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
304 ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
305 ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
306 };
307 };
308
309 scif0: serial@ffe40000 {
310 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
311 "renesas,scif";
312 reg = <0xffe40000 0x100>;
313 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
315 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
316 clock-names = "fck", "brg_int", "scif_clk";
317 power-domains = <&cpg_clocks>;
318 status = "disabled";
319 };
320
321 scif1: serial@ffe41000 {
322 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
323 "renesas,scif";
324 reg = <0xffe41000 0x100>;
325 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
327 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
328 clock-names = "fck", "brg_int", "scif_clk";
329 power-domains = <&cpg_clocks>;
330 status = "disabled";
331 };
332
333 scif2: serial@ffe42000 {
334 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
335 "renesas,scif";
336 reg = <0xffe42000 0x100>;
337 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
339 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
340 clock-names = "fck", "brg_int", "scif_clk";
341 power-domains = <&cpg_clocks>;
342 status = "disabled";
343 };
344
345 scif3: serial@ffe43000 {
346 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
347 "renesas,scif";
348 reg = <0xffe43000 0x100>;
349 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
351 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
352 clock-names = "fck", "brg_int", "scif_clk";
353 power-domains = <&cpg_clocks>;
354 status = "disabled";
355 };
356
357 scif4: serial@ffe44000 {
358 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
359 "renesas,scif";
360 reg = <0xffe44000 0x100>;
361 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
363 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
364 clock-names = "fck", "brg_int", "scif_clk";
365 power-domains = <&cpg_clocks>;
366 status = "disabled";
367 };
368
369 scif5: serial@ffe45000 {
370 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
371 "renesas,scif";
372 reg = <0xffe45000 0x100>;
373 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
375 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
376 clock-names = "fck", "brg_int", "scif_clk";
377 power-domains = <&cpg_clocks>;
378 status = "disabled";
379 };
380
381 hscif0: serial@ffe48000 {
382 compatible = "renesas,hscif-r8a7778",
383 "renesas,rcar-gen1-hscif", "renesas,hscif";
384 reg = <0xffe48000 96>;
385 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
387 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
388 clock-names = "fck", "brg_int", "scif_clk";
389 power-domains = <&cpg_clocks>;
390 status = "disabled";
391 };
392
393 hscif1: serial@ffe49000 {
394 compatible = "renesas,hscif-r8a7778",
395 "renesas,rcar-gen1-hscif", "renesas,hscif";
396 reg = <0xffe49000 96>;
397 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
399 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
400 clock-names = "fck", "brg_int", "scif_clk";
401 power-domains = <&cpg_clocks>;
402 status = "disabled";
403 };
404
405 mmcif: mmc@ffe4e000 {
406 compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
407 reg = <0xffe4e000 0x100>;
408 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
410 power-domains = <&cpg_clocks>;
411 status = "disabled";
412 };
413
414 sdhi0: mmc@ffe4c000 {
415 compatible = "renesas,sdhi-r8a7778",
416 "renesas,rcar-gen1-sdhi";
417 reg = <0xffe4c000 0x100>;
418 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
420 power-domains = <&cpg_clocks>;
421 status = "disabled";
422 };
423
424 sdhi1: mmc@ffe4d000 {
425 compatible = "renesas,sdhi-r8a7778",
426 "renesas,rcar-gen1-sdhi";
427 reg = <0xffe4d000 0x100>;
428 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
430 power-domains = <&cpg_clocks>;
431 status = "disabled";
432 };
433
434 sdhi2: mmc@ffe4f000 {
435 compatible = "renesas,sdhi-r8a7778",
436 "renesas,rcar-gen1-sdhi";
437 reg = <0xffe4f000 0x100>;
438 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
440 power-domains = <&cpg_clocks>;
441 status = "disabled";
442 };
443
444 hspi0: spi@fffc7000 {
445 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
446 reg = <0xfffc7000 0x18>;
447 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
449 power-domains = <&cpg_clocks>;
450 #address-cells = <1>;
451 #size-cells = <0>;
452 status = "disabled";
453 };
454
455 hspi1: spi@fffc8000 {
456 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
457 reg = <0xfffc8000 0x18>;
458 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
460 power-domains = <&cpg_clocks>;
461 #address-cells = <1>;
462 #size-cells = <0>;
463 status = "disabled";
464 };
465
466 hspi2: spi@fffc6000 {
467 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
468 reg = <0xfffc6000 0x18>;
469 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
471 power-domains = <&cpg_clocks>;
472 #address-cells = <1>;
473 #size-cells = <0>;
474 status = "disabled";
475 };
476
477 clocks {
478 #address-cells = <1>;
479 #size-cells = <1>;
480 ranges;
481
482 /* External input clock */
483 extal_clk: extal {
484 compatible = "fixed-clock";
485 #clock-cells = <0>;
486 clock-frequency = <0>;
487 };
488
489 /* External SCIF clock */
490 scif_clk: scif {
491 compatible = "fixed-clock";
492 #clock-cells = <0>;
493 /* This value must be overridden by the board. */
494 clock-frequency = <0>;
495 };
496
497 /* Special CPG clocks */
498 cpg_clocks: cpg_clocks@ffc80000 {
499 compatible = "renesas,r8a7778-cpg-clocks";
500 reg = <0xffc80000 0x80>;
501 #clock-cells = <1>;
502 clocks = <&extal_clk>;
503 clock-output-names = "plla", "pllb", "b",
504 "out", "p", "s", "s1";
505 #power-domain-cells = <0>;
506 };
507
508 /* Audio clocks; frequencies are set by boards if applicable. */
509 audio_clk_a: audio_clk_a {
510 compatible = "fixed-clock";
511 #clock-cells = <0>;
512 clock-frequency = <0>;
513 };
514 audio_clk_b: audio_clk_b {
515 compatible = "fixed-clock";
516 #clock-cells = <0>;
517 clock-frequency = <0>;
518 };
519 audio_clk_c: audio_clk_c {
520 compatible = "fixed-clock";
521 #clock-cells = <0>;
522 clock-frequency = <0>;
523 };
524
525 /* Fixed ratio clocks */
526 g_clk: g {
527 compatible = "fixed-factor-clock";
528 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
529 #clock-cells = <0>;
530 clock-div = <12>;
531 clock-mult = <1>;
532 };
533 i_clk: i {
534 compatible = "fixed-factor-clock";
535 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
536 #clock-cells = <0>;
537 clock-div = <1>;
538 clock-mult = <1>;
539 };
540 s3_clk: s3 {
541 compatible = "fixed-factor-clock";
542 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
543 #clock-cells = <0>;
544 clock-div = <4>;
545 clock-mult = <1>;
546 };
547 s4_clk: s4 {
548 compatible = "fixed-factor-clock";
549 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
550 #clock-cells = <0>;
551 clock-div = <8>;
552 clock-mult = <1>;
553 };
554 z_clk: z {
555 compatible = "fixed-factor-clock";
556 clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
557 #clock-cells = <0>;
558 clock-div = <1>;
559 clock-mult = <1>;
560 };
561
562 /* Gate clocks */
563 mstp0_clks: mstp0_clks@ffc80030 {
564 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
565 reg = <0xffc80030 4>;
566 clocks = <&cpg_clocks R8A7778_CLK_P>,
567 <&cpg_clocks R8A7778_CLK_P>,
568 <&cpg_clocks R8A7778_CLK_P>,
569 <&cpg_clocks R8A7778_CLK_P>,
570 <&cpg_clocks R8A7778_CLK_P>,
571 <&cpg_clocks R8A7778_CLK_P>,
572 <&cpg_clocks R8A7778_CLK_P>,
573 <&cpg_clocks R8A7778_CLK_P>,
574 <&cpg_clocks R8A7778_CLK_P>,
575 <&cpg_clocks R8A7778_CLK_P>,
576 <&cpg_clocks R8A7778_CLK_S>,
577 <&cpg_clocks R8A7778_CLK_S>,
578 <&cpg_clocks R8A7778_CLK_P>,
579 <&cpg_clocks R8A7778_CLK_P>,
580 <&cpg_clocks R8A7778_CLK_P>,
581 <&cpg_clocks R8A7778_CLK_P>,
582 <&cpg_clocks R8A7778_CLK_P>,
583 <&cpg_clocks R8A7778_CLK_P>,
584 <&cpg_clocks R8A7778_CLK_P>,
585 <&cpg_clocks R8A7778_CLK_P>,
586 <&cpg_clocks R8A7778_CLK_S>;
587 #clock-cells = <1>;
588 clock-indices = <
589 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
590 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
591 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
592 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
593 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
594 R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
595 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
596 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
597 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
598 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
599 R8A7778_CLK_HSPI
600 >;
601 clock-output-names =
602 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
603 "scif1", "scif2", "scif3", "scif4", "scif5",
604 "hscif0", "hscif1",
605 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
606 "ssi2", "ssi3", "sru", "hspi";
607 };
608 mstp1_clks: mstp1_clks@ffc80034 {
609 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
610 reg = <0xffc80034 4>, <0xffc80044 4>;
611 clocks = <&cpg_clocks R8A7778_CLK_P>,
612 <&cpg_clocks R8A7778_CLK_S>,
613 <&cpg_clocks R8A7778_CLK_S>,
614 <&cpg_clocks R8A7778_CLK_P>;
615 #clock-cells = <1>;
616 clock-indices = <
617 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
618 R8A7778_CLK_VIN1 R8A7778_CLK_USB
619 >;
620 clock-output-names =
621 "ether", "vin0", "vin1", "usb";
622 };
623 mstp3_clks: mstp3_clks@ffc8003c {
624 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
625 reg = <0xffc8003c 4>;
626 clocks = <&s4_clk>,
627 <&cpg_clocks R8A7778_CLK_P>,
628 <&cpg_clocks R8A7778_CLK_P>,
629 <&cpg_clocks R8A7778_CLK_P>,
630 <&cpg_clocks R8A7778_CLK_P>,
631 <&cpg_clocks R8A7778_CLK_P>,
632 <&cpg_clocks R8A7778_CLK_P>,
633 <&cpg_clocks R8A7778_CLK_P>,
634 <&cpg_clocks R8A7778_CLK_P>;
635 #clock-cells = <1>;
636 clock-indices = <
637 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
638 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
639 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
640 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
641 R8A7778_CLK_SSI8
642 >;
643 clock-output-names =
644 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
645 "ssi5", "ssi6", "ssi7", "ssi8";
646 };
647 mstp5_clks: mstp5_clks@ffc80054 {
648 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
649 reg = <0xffc80054 4>;
650 clocks = <&cpg_clocks R8A7778_CLK_P>,
651 <&cpg_clocks R8A7778_CLK_P>,
652 <&cpg_clocks R8A7778_CLK_P>,
653 <&cpg_clocks R8A7778_CLK_P>,
654 <&cpg_clocks R8A7778_CLK_P>,
655 <&cpg_clocks R8A7778_CLK_P>,
656 <&cpg_clocks R8A7778_CLK_P>,
657 <&cpg_clocks R8A7778_CLK_P>,
658 <&cpg_clocks R8A7778_CLK_P>;
659 #clock-cells = <1>;
660 clock-indices = <
661 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
662 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
663 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
664 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
665 R8A7778_CLK_SRU_SRC8
666 >;
667 clock-output-names =
668 "sru-src0", "sru-src1", "sru-src2",
669 "sru-src3", "sru-src4", "sru-src5",
670 "sru-src6", "sru-src7", "sru-src8";
671 };
672 };
673
674 rst: reset-controller@ffcc0000 {
675 compatible = "renesas,r8a7778-reset-wdt";
676 reg = <0xffcc0000 0x40>;
677 };
678};