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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / renesas / r8a7742.dtsi
blob: d55c344c1cd2b1511e37fa8a4ecc95707d84ed35 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a7742 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/power/r8a7742-sysc.h>
12
13/ {
14 compatible = "renesas,r8a7742";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 /*
19 * The external audio clocks are configured as 0 Hz fixed frequency
20 * clocks by default.
21 * Boards that provide audio clocks should override them.
22 */
23 audio_clk_a: audio_clk_a {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
27 };
28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <0>;
32 };
33 audio_clk_c: audio_clk_c {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <0>;
37 };
38
39 /* External CAN clock */
40 can_clk: can {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 /* This value must be overridden by the board. */
44 clock-frequency = <0>;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a15";
54 reg = <0>;
55 clock-frequency = <1400000000>;
56 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
57 power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
58 enable-method = "renesas,apmu";
59 next-level-cache = <&L2_CA15>;
60 capacity-dmips-mhz = <1024>;
61 voltage-tolerance = <1>; /* 1% */
62 clock-latency = <300000>; /* 300 us */
63
64 /* kHz - uV - OPPs unknown yet */
65 operating-points = <1400000 1000000>,
66 <1225000 1000000>,
67 <1050000 1000000>,
68 < 875000 1000000>,
69 < 700000 1000000>,
70 < 350000 1000000>;
71 };
72
73 cpu1: cpu@1 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a15";
76 reg = <1>;
77 clock-frequency = <1400000000>;
78 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
79 power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
80 enable-method = "renesas,apmu";
81 next-level-cache = <&L2_CA15>;
82 capacity-dmips-mhz = <1024>;
83 voltage-tolerance = <1>; /* 1% */
84 clock-latency = <300000>; /* 300 us */
85
86 /* kHz - uV - OPPs unknown yet */
87 operating-points = <1400000 1000000>,
88 <1225000 1000000>,
89 <1050000 1000000>,
90 < 875000 1000000>,
91 < 700000 1000000>,
92 < 350000 1000000>;
93 };
94
95 cpu2: cpu@2 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a15";
98 reg = <2>;
99 clock-frequency = <1400000000>;
100 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
101 power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
102 enable-method = "renesas,apmu";
103 next-level-cache = <&L2_CA15>;
104 capacity-dmips-mhz = <1024>;
105 voltage-tolerance = <1>; /* 1% */
106 clock-latency = <300000>; /* 300 us */
107
108 /* kHz - uV - OPPs unknown yet */
109 operating-points = <1400000 1000000>,
110 <1225000 1000000>,
111 <1050000 1000000>,
112 < 875000 1000000>,
113 < 700000 1000000>,
114 < 350000 1000000>;
115 };
116
117 cpu3: cpu@3 {
118 device_type = "cpu";
119 compatible = "arm,cortex-a15";
120 reg = <3>;
121 clock-frequency = <1400000000>;
122 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
123 power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
124 enable-method = "renesas,apmu";
125 next-level-cache = <&L2_CA15>;
126 capacity-dmips-mhz = <1024>;
127 voltage-tolerance = <1>; /* 1% */
128 clock-latency = <300000>; /* 300 us */
129
130 /* kHz - uV - OPPs unknown yet */
131 operating-points = <1400000 1000000>,
132 <1225000 1000000>,
133 <1050000 1000000>,
134 < 875000 1000000>,
135 < 700000 1000000>,
136 < 350000 1000000>;
137 };
138
139 cpu4: cpu@100 {
140 device_type = "cpu";
141 compatible = "arm,cortex-a7";
142 reg = <0x100>;
143 clock-frequency = <780000000>;
144 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
145 power-domains = <&sysc R8A7742_PD_CA7_CPU0>;
146 next-level-cache = <&L2_CA7>;
147 };
148
149 cpu5: cpu@101 {
150 device_type = "cpu";
151 compatible = "arm,cortex-a7";
152 reg = <0x101>;
153 clock-frequency = <780000000>;
154 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
155 power-domains = <&sysc R8A7742_PD_CA7_CPU1>;
156 next-level-cache = <&L2_CA7>;
157 };
158
159 cpu6: cpu@102 {
160 device_type = "cpu";
161 compatible = "arm,cortex-a7";
162 reg = <0x102>;
163 clock-frequency = <780000000>;
164 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
165 power-domains = <&sysc R8A7742_PD_CA7_CPU2>;
166 next-level-cache = <&L2_CA7>;
167 };
168
169 cpu7: cpu@103 {
170 device_type = "cpu";
171 compatible = "arm,cortex-a7";
172 reg = <0x103>;
173 clock-frequency = <780000000>;
174 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
175 power-domains = <&sysc R8A7742_PD_CA7_CPU3>;
176 next-level-cache = <&L2_CA7>;
177 };
178
179 L2_CA15: cache-controller-0 {
180 compatible = "cache";
181 power-domains = <&sysc R8A7742_PD_CA15_SCU>;
182 cache-unified;
183 cache-level = <2>;
184 };
185
186 L2_CA7: cache-controller-1 {
187 compatible = "cache";
188 power-domains = <&sysc R8A7742_PD_CA7_SCU>;
189 cache-unified;
190 cache-level = <2>;
191 };
192 };
193
194 /* External root clock */
195 extal_clk: extal {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 /* This value must be overridden by the board. */
199 clock-frequency = <0>;
200 };
201
202 /* External PCIe clock - can be overridden by the board */
203 pcie_bus_clk: pcie_bus {
204 compatible = "fixed-clock";
205 #clock-cells = <0>;
206 clock-frequency = <0>;
207 };
208
209 pmu-0 {
210 compatible = "arm,cortex-a15-pmu";
211 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
212 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
213 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
214 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
215 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
216 };
217
218 pmu-1 {
219 compatible = "arm,cortex-a7-pmu";
220 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
221 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
222 <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
223 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
225 };
226
227 /* External SCIF clock */
228 scif_clk: scif {
229 compatible = "fixed-clock";
230 #clock-cells = <0>;
231 /* This value must be overridden by the board. */
232 clock-frequency = <0>;
233 };
234
235 soc {
236 compatible = "simple-bus";
237 interrupt-parent = <&gic>;
238
239 #address-cells = <2>;
240 #size-cells = <2>;
241 ranges;
242
243 rwdt: watchdog@e6020000 {
244 compatible = "renesas,r8a7742-wdt",
245 "renesas,rcar-gen2-wdt";
246 reg = <0 0xe6020000 0 0x0c>;
247 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cpg CPG_MOD 402>;
249 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
250 resets = <&cpg 402>;
251 status = "disabled";
252 };
253
254 gpio0: gpio@e6050000 {
255 compatible = "renesas,gpio-r8a7742",
256 "renesas,rcar-gen2-gpio";
257 reg = <0 0xe6050000 0 0x50>;
258 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
259 #gpio-cells = <2>;
260 gpio-controller;
261 gpio-ranges = <&pfc 0 0 32>;
262 #interrupt-cells = <2>;
263 interrupt-controller;
264 clocks = <&cpg CPG_MOD 912>;
265 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
266 resets = <&cpg 912>;
267 };
268
269 gpio1: gpio@e6051000 {
270 compatible = "renesas,gpio-r8a7742",
271 "renesas,rcar-gen2-gpio";
272 reg = <0 0xe6051000 0 0x50>;
273 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
274 #gpio-cells = <2>;
275 gpio-controller;
276 gpio-ranges = <&pfc 0 32 30>;
277 #interrupt-cells = <2>;
278 interrupt-controller;
279 clocks = <&cpg CPG_MOD 911>;
280 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
281 resets = <&cpg 911>;
282 };
283
284 gpio2: gpio@e6052000 {
285 compatible = "renesas,gpio-r8a7742",
286 "renesas,rcar-gen2-gpio";
287 reg = <0 0xe6052000 0 0x50>;
288 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
289 #gpio-cells = <2>;
290 gpio-controller;
291 gpio-ranges = <&pfc 0 64 30>;
292 #interrupt-cells = <2>;
293 interrupt-controller;
294 clocks = <&cpg CPG_MOD 910>;
295 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
296 resets = <&cpg 910>;
297 };
298
299 gpio3: gpio@e6053000 {
300 compatible = "renesas,gpio-r8a7742",
301 "renesas,rcar-gen2-gpio";
302 reg = <0 0xe6053000 0 0x50>;
303 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
304 #gpio-cells = <2>;
305 gpio-controller;
306 gpio-ranges = <&pfc 0 96 32>;
307 #interrupt-cells = <2>;
308 interrupt-controller;
309 clocks = <&cpg CPG_MOD 909>;
310 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
311 resets = <&cpg 909>;
312 };
313
314 gpio4: gpio@e6054000 {
315 compatible = "renesas,gpio-r8a7742",
316 "renesas,rcar-gen2-gpio";
317 reg = <0 0xe6054000 0 0x50>;
318 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
319 #gpio-cells = <2>;
320 gpio-controller;
321 gpio-ranges = <&pfc 0 128 32>;
322 #interrupt-cells = <2>;
323 interrupt-controller;
324 clocks = <&cpg CPG_MOD 908>;
325 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
326 resets = <&cpg 908>;
327 };
328
329 gpio5: gpio@e6055000 {
330 compatible = "renesas,gpio-r8a7742",
331 "renesas,rcar-gen2-gpio";
332 reg = <0 0xe6055000 0 0x50>;
333 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
334 #gpio-cells = <2>;
335 gpio-controller;
336 gpio-ranges = <&pfc 0 160 32>;
337 #interrupt-cells = <2>;
338 interrupt-controller;
339 clocks = <&cpg CPG_MOD 907>;
340 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
341 resets = <&cpg 907>;
342 };
343
344 pfc: pinctrl@e6060000 {
345 compatible = "renesas,pfc-r8a7742";
346 reg = <0 0xe6060000 0 0x250>;
347 };
348
349 tpu: pwm@e60f0000 {
350 compatible = "renesas,tpu-r8a7742", "renesas,tpu";
351 reg = <0 0xe60f0000 0 0x148>;
352 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cpg CPG_MOD 304>;
354 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
355 resets = <&cpg 304>;
356 #pwm-cells = <3>;
357 status = "disabled";
358 };
359
360 cpg: clock-controller@e6150000 {
361 compatible = "renesas,r8a7742-cpg-mssr";
362 reg = <0 0xe6150000 0 0x1000>;
363 clocks = <&extal_clk>, <&usb_extal_clk>;
364 clock-names = "extal", "usb_extal";
365 #clock-cells = <2>;
366 #power-domain-cells = <0>;
367 #reset-cells = <1>;
368 };
369
370 apmu@e6151000 {
371 compatible = "renesas,r8a7742-apmu", "renesas,apmu";
372 reg = <0 0xe6151000 0 0x188>;
373 cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
374 };
375
376 apmu@e6152000 {
377 compatible = "renesas,r8a7742-apmu", "renesas,apmu";
378 reg = <0 0xe6152000 0 0x188>;
379 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
380 };
381
382 rst: reset-controller@e6160000 {
383 compatible = "renesas,r8a7742-rst";
384 reg = <0 0xe6160000 0 0x0100>;
385 };
386
387 sysc: system-controller@e6180000 {
388 compatible = "renesas,r8a7742-sysc";
389 reg = <0 0xe6180000 0 0x0200>;
390 #power-domain-cells = <1>;
391 };
392
393 irqc: interrupt-controller@e61c0000 {
394 compatible = "renesas,irqc-r8a7742", "renesas,irqc";
395 #interrupt-cells = <2>;
396 interrupt-controller;
397 reg = <0 0xe61c0000 0 0x200>;
398 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&cpg CPG_MOD 407>;
403 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
404 resets = <&cpg 407>;
405 };
406
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame^]407 tmu0: timer@e61e0000 {
408 compatible = "renesas,tmu-r8a7742", "renesas,tmu";
409 reg = <0 0xe61e0000 0 0x30>;
410 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
413 interrupt-names = "tuni0", "tuni1", "tuni2";
414 clocks = <&cpg CPG_MOD 125>;
415 clock-names = "fck";
416 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
417 resets = <&cpg 125>;
418 status = "disabled";
419 };
420
421 tmu1: timer@fff60000 {
422 compatible = "renesas,tmu-r8a7742", "renesas,tmu";
423 reg = <0 0xfff60000 0 0x30>;
424 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
429 clocks = <&cpg CPG_MOD 111>;
430 clock-names = "fck";
431 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
432 resets = <&cpg 111>;
433 status = "disabled";
434 };
435
436 tmu2: timer@fff70000 {
437 compatible = "renesas,tmu-r8a7742", "renesas,tmu";
438 reg = <0 0xfff70000 0 0x30>;
439 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
444 clocks = <&cpg CPG_MOD 122>;
445 clock-names = "fck";
446 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
447 resets = <&cpg 122>;
448 status = "disabled";
449 };
450
451 tmu3: timer@fff80000 {
452 compatible = "renesas,tmu-r8a7742", "renesas,tmu";
453 reg = <0 0xfff80000 0 0x30>;
454 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
457 interrupt-names = "tuni0", "tuni1", "tuni2";
458 clocks = <&cpg CPG_MOD 121>;
459 clock-names = "fck";
460 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
461 resets = <&cpg 121>;
462 status = "disabled";
463 };
464
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]465 thermal: thermal@e61f0000 {
466 compatible = "renesas,thermal-r8a7742",
467 "renesas,rcar-gen2-thermal";
468 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
469 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&cpg CPG_MOD 522>;
471 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
472 resets = <&cpg 522>;
473 #thermal-sensor-cells = <0>;
474 };
475
476 ipmmu_sy0: iommu@e6280000 {
477 compatible = "renesas,ipmmu-r8a7742",
478 "renesas,ipmmu-vmsa";
479 reg = <0 0xe6280000 0 0x1000>;
480 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
482 #iommu-cells = <1>;
483 status = "disabled";
484 };
485
486 ipmmu_sy1: iommu@e6290000 {
487 compatible = "renesas,ipmmu-r8a7742",
488 "renesas,ipmmu-vmsa";
489 reg = <0 0xe6290000 0 0x1000>;
490 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
491 #iommu-cells = <1>;
492 status = "disabled";
493 };
494
495 ipmmu_ds: iommu@e6740000 {
496 compatible = "renesas,ipmmu-r8a7742",
497 "renesas,ipmmu-vmsa";
498 reg = <0 0xe6740000 0 0x1000>;
499 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
501 #iommu-cells = <1>;
502 status = "disabled";
503 };
504
505 ipmmu_mp: iommu@ec680000 {
506 compatible = "renesas,ipmmu-r8a7742",
507 "renesas,ipmmu-vmsa";
508 reg = <0 0xec680000 0 0x1000>;
509 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
510 #iommu-cells = <1>;
511 status = "disabled";
512 };
513
514 ipmmu_mx: iommu@fe951000 {
515 compatible = "renesas,ipmmu-r8a7742",
516 "renesas,ipmmu-vmsa";
517 reg = <0 0xfe951000 0 0x1000>;
518 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
520 #iommu-cells = <1>;
521 status = "disabled";
522 };
523
524 icram0: sram@e63a0000 {
525 compatible = "mmio-sram";
526 reg = <0 0xe63a0000 0 0x12000>;
527 #address-cells = <1>;
528 #size-cells = <1>;
529 ranges = <0 0 0xe63a0000 0x12000>;
530 };
531
532 icram1: sram@e63c0000 {
533 compatible = "mmio-sram";
534 reg = <0 0xe63c0000 0 0x1000>;
535 #address-cells = <1>;
536 #size-cells = <1>;
537 ranges = <0 0 0xe63c0000 0x1000>;
538
539 smp-sram@0 {
540 compatible = "renesas,smp-sram";
541 reg = <0 0x100>;
542 };
543 };
544
545 icram2: sram@e6300000 {
546 compatible = "mmio-sram";
547 reg = <0 0xe6300000 0 0x40000>;
548 #address-cells = <1>;
549 #size-cells = <1>;
550 ranges = <0 0 0xe6300000 0x40000>;
551 };
552
553 i2c0: i2c@e6508000 {
554 #address-cells = <1>;
555 #size-cells = <0>;
556 compatible = "renesas,i2c-r8a7742",
557 "renesas,rcar-gen2-i2c";
558 reg = <0 0xe6508000 0 0x40>;
559 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&cpg CPG_MOD 931>;
561 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
562 resets = <&cpg 931>;
563 i2c-scl-internal-delay-ns = <110>;
564 status = "disabled";
565 };
566
567 i2c1: i2c@e6518000 {
568 #address-cells = <1>;
569 #size-cells = <0>;
570 compatible = "renesas,i2c-r8a7742",
571 "renesas,rcar-gen2-i2c";
572 reg = <0 0xe6518000 0 0x40>;
573 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cpg CPG_MOD 930>;
575 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
576 resets = <&cpg 930>;
577 i2c-scl-internal-delay-ns = <6>;
578 status = "disabled";
579 };
580
581 i2c2: i2c@e6530000 {
582 #address-cells = <1>;
583 #size-cells = <0>;
584 compatible = "renesas,i2c-r8a7742",
585 "renesas,rcar-gen2-i2c";
586 reg = <0 0xe6530000 0 0x40>;
587 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&cpg CPG_MOD 929>;
589 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
590 resets = <&cpg 929>;
591 i2c-scl-internal-delay-ns = <6>;
592 status = "disabled";
593 };
594
595 i2c3: i2c@e6540000 {
596 #address-cells = <1>;
597 #size-cells = <0>;
598 compatible = "renesas,i2c-r8a7742",
599 "renesas,rcar-gen2-i2c";
600 reg = <0 0xe6540000 0 0x40>;
601 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&cpg CPG_MOD 928>;
603 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
604 resets = <&cpg 928>;
605 i2c-scl-internal-delay-ns = <110>;
606 status = "disabled";
607 };
608
609 iic0: i2c@e6500000 {
610 #address-cells = <1>;
611 #size-cells = <0>;
612 compatible = "renesas,iic-r8a7742",
613 "renesas,rcar-gen2-iic",
614 "renesas,rmobile-iic";
615 reg = <0 0xe6500000 0 0x425>;
616 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&cpg CPG_MOD 318>;
618 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
619 <&dmac1 0x61>, <&dmac1 0x62>;
620 dma-names = "tx", "rx", "tx", "rx";
621 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
622 resets = <&cpg 318>;
623 status = "disabled";
624 };
625
626 iic1: i2c@e6510000 {
627 #address-cells = <1>;
628 #size-cells = <0>;
629 compatible = "renesas,iic-r8a7742",
630 "renesas,rcar-gen2-iic",
631 "renesas,rmobile-iic";
632 reg = <0 0xe6510000 0 0x425>;
633 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&cpg CPG_MOD 323>;
635 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
636 <&dmac1 0x65>, <&dmac1 0x66>;
637 dma-names = "tx", "rx", "tx", "rx";
638 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
639 resets = <&cpg 323>;
640 status = "disabled";
641 };
642
643 iic2: i2c@e6520000 {
644 #address-cells = <1>;
645 #size-cells = <0>;
646 compatible = "renesas,iic-r8a7742",
647 "renesas,rcar-gen2-iic",
648 "renesas,rmobile-iic";
649 reg = <0 0xe6520000 0 0x425>;
650 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&cpg CPG_MOD 300>;
652 dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
653 <&dmac1 0x69>, <&dmac1 0x6a>;
654 dma-names = "tx", "rx", "tx", "rx";
655 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
656 resets = <&cpg 300>;
657 status = "disabled";
658 };
659
660 iic3: i2c@e60b0000 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 compatible = "renesas,iic-r8a7742",
664 "renesas,rcar-gen2-iic",
665 "renesas,rmobile-iic";
666 reg = <0 0xe60b0000 0 0x425>;
667 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&cpg CPG_MOD 926>;
669 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
670 <&dmac1 0x77>, <&dmac1 0x78>;
671 dma-names = "tx", "rx", "tx", "rx";
672 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
673 resets = <&cpg 926>;
674 status = "disabled";
675 };
676
677 hsusb: usb@e6590000 {
678 compatible = "renesas,usbhs-r8a7742",
679 "renesas,rcar-gen2-usbhs";
680 reg = <0 0xe6590000 0 0x100>;
681 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cpg CPG_MOD 704>;
683 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
684 <&usb_dmac1 0>, <&usb_dmac1 1>;
685 dma-names = "ch0", "ch1", "ch2", "ch3";
686 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
687 resets = <&cpg 704>;
688 renesas,buswait = <4>;
689 phys = <&usb0 1>;
690 phy-names = "usb";
691 status = "disabled";
692 };
693
694 usbphy: usb-phy-controller@e6590100 {
695 compatible = "renesas,usb-phy-r8a7742",
696 "renesas,rcar-gen2-usb-phy";
697 reg = <0 0xe6590100 0 0x100>;
698 #address-cells = <1>;
699 #size-cells = <0>;
700 clocks = <&cpg CPG_MOD 704>;
701 clock-names = "usbhs";
702 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
703 resets = <&cpg 704>;
704 status = "disabled";
705
706 usb0: usb-phy@0 {
707 reg = <0>;
708 #phy-cells = <1>;
709 };
710 usb2: usb-phy@2 {
711 reg = <2>;
712 #phy-cells = <1>;
713 };
714 };
715
716 usb_dmac0: dma-controller@e65a0000 {
717 compatible = "renesas,r8a7742-usb-dmac",
718 "renesas,usb-dmac";
719 reg = <0 0xe65a0000 0 0x100>;
720 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
722 interrupt-names = "ch0", "ch1";
723 clocks = <&cpg CPG_MOD 330>;
724 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
725 resets = <&cpg 330>;
726 #dma-cells = <1>;
727 dma-channels = <2>;
728 };
729
730 usb_dmac1: dma-controller@e65b0000 {
731 compatible = "renesas,r8a7742-usb-dmac",
732 "renesas,usb-dmac";
733 reg = <0 0xe65b0000 0 0x100>;
734 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
736 interrupt-names = "ch0", "ch1";
737 clocks = <&cpg CPG_MOD 331>;
738 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
739 resets = <&cpg 331>;
740 #dma-cells = <1>;
741 dma-channels = <2>;
742 };
743
744 dmac0: dma-controller@e6700000 {
745 compatible = "renesas,dmac-r8a7742",
746 "renesas,rcar-dmac";
747 reg = <0 0xe6700000 0 0x20000>;
748 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
764 interrupt-names = "error",
765 "ch0", "ch1", "ch2", "ch3",
766 "ch4", "ch5", "ch6", "ch7",
767 "ch8", "ch9", "ch10", "ch11",
768 "ch12", "ch13", "ch14";
769 clocks = <&cpg CPG_MOD 219>;
770 clock-names = "fck";
771 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
772 resets = <&cpg 219>;
773 #dma-cells = <1>;
774 dma-channels = <15>;
775 };
776
777 dmac1: dma-controller@e6720000 {
778 compatible = "renesas,dmac-r8a7742",
779 "renesas,rcar-dmac";
780 reg = <0 0xe6720000 0 0x20000>;
781 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
794 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
795 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
796 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
797 interrupt-names = "error",
798 "ch0", "ch1", "ch2", "ch3",
799 "ch4", "ch5", "ch6", "ch7",
800 "ch8", "ch9", "ch10", "ch11",
801 "ch12", "ch13", "ch14";
802 clocks = <&cpg CPG_MOD 218>;
803 clock-names = "fck";
804 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
805 resets = <&cpg 218>;
806 #dma-cells = <1>;
807 dma-channels = <15>;
808 };
809
810 avb: ethernet@e6800000 {
811 compatible = "renesas,etheravb-r8a7742",
812 "renesas,etheravb-rcar-gen2";
813 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
814 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&cpg CPG_MOD 812>;
816 clock-names = "fck";
817 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
818 resets = <&cpg 812>;
819 #address-cells = <1>;
820 #size-cells = <0>;
821 status = "disabled";
822 };
823
824 qspi: spi@e6b10000 {
825 compatible = "renesas,qspi-r8a7742", "renesas,qspi";
826 reg = <0 0xe6b10000 0 0x2c>;
827 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&cpg CPG_MOD 917>;
829 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
830 <&dmac1 0x17>, <&dmac1 0x18>;
831 dma-names = "tx", "rx", "tx", "rx";
832 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
833 resets = <&cpg 917>;
834 num-cs = <1>;
835 #address-cells = <1>;
836 #size-cells = <0>;
837 status = "disabled";
838 };
839
840 scifa0: serial@e6c40000 {
841 compatible = "renesas,scifa-r8a7742",
842 "renesas,rcar-gen2-scifa", "renesas,scifa";
843 reg = <0 0xe6c40000 0 0x40>;
844 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&cpg CPG_MOD 204>;
846 clock-names = "fck";
847 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
848 <&dmac1 0x21>, <&dmac1 0x22>;
849 dma-names = "tx", "rx", "tx", "rx";
850 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
851 resets = <&cpg 204>;
852 status = "disabled";
853 };
854
855 scifa1: serial@e6c50000 {
856 compatible = "renesas,scifa-r8a7742",
857 "renesas,rcar-gen2-scifa", "renesas,scifa";
858 reg = <0 0xe6c50000 0 0x40>;
859 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&cpg CPG_MOD 203>;
861 clock-names = "fck";
862 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
863 <&dmac1 0x25>, <&dmac1 0x26>;
864 dma-names = "tx", "rx", "tx", "rx";
865 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
866 resets = <&cpg 203>;
867 status = "disabled";
868 };
869
870 scifa2: serial@e6c60000 {
871 compatible = "renesas,scifa-r8a7742",
872 "renesas,rcar-gen2-scifa", "renesas,scifa";
873 reg = <0 0xe6c60000 0 0x40>;
874 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&cpg CPG_MOD 202>;
876 clock-names = "fck";
877 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
878 <&dmac1 0x27>, <&dmac1 0x28>;
879 dma-names = "tx", "rx", "tx", "rx";
880 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
881 resets = <&cpg 202>;
882 status = "disabled";
883 };
884
885 scifb0: serial@e6c20000 {
886 compatible = "renesas,scifb-r8a7742",
887 "renesas,rcar-gen2-scifb", "renesas,scifb";
888 reg = <0 0xe6c20000 0 0x100>;
889 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&cpg CPG_MOD 206>;
891 clock-names = "fck";
892 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
893 <&dmac1 0x3d>, <&dmac1 0x3e>;
894 dma-names = "tx", "rx", "tx", "rx";
895 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
896 resets = <&cpg 206>;
897 status = "disabled";
898 };
899
900 scifb1: serial@e6c30000 {
901 compatible = "renesas,scifb-r8a7742",
902 "renesas,rcar-gen2-scifb", "renesas,scifb";
903 reg = <0 0xe6c30000 0 0x100>;
904 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&cpg CPG_MOD 207>;
906 clock-names = "fck";
907 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
908 <&dmac1 0x19>, <&dmac1 0x1a>;
909 dma-names = "tx", "rx", "tx", "rx";
910 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
911 resets = <&cpg 207>;
912 status = "disabled";
913 };
914
915 scifb2: serial@e6ce0000 {
916 compatible = "renesas,scifb-r8a7742",
917 "renesas,rcar-gen2-scifb", "renesas,scifb";
918 reg = <0 0xe6ce0000 0 0x100>;
919 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&cpg CPG_MOD 216>;
921 clock-names = "fck";
922 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
923 <&dmac1 0x1d>, <&dmac1 0x1e>;
924 dma-names = "tx", "rx", "tx", "rx";
925 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
926 resets = <&cpg 216>;
927 status = "disabled";
928 };
929
930 scif0: serial@e6e60000 {
931 compatible = "renesas,scif-r8a7742",
932 "renesas,rcar-gen2-scif", "renesas,scif";
933 reg = <0 0xe6e60000 0 0x40>;
934 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&cpg CPG_MOD 721>,
936 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
937 clock-names = "fck", "brg_int", "scif_clk";
938 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
939 <&dmac1 0x29>, <&dmac1 0x2a>;
940 dma-names = "tx", "rx", "tx", "rx";
941 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
942 resets = <&cpg 721>;
943 status = "disabled";
944 };
945
946 scif1: serial@e6e68000 {
947 compatible = "renesas,scif-r8a7742",
948 "renesas,rcar-gen2-scif", "renesas,scif";
949 reg = <0 0xe6e68000 0 0x40>;
950 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
951 clocks = <&cpg CPG_MOD 720>,
952 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
953 clock-names = "fck", "brg_int", "scif_clk";
954 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
955 <&dmac1 0x2d>, <&dmac1 0x2e>;
956 dma-names = "tx", "rx", "tx", "rx";
957 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
958 resets = <&cpg 720>;
959 status = "disabled";
960 };
961
962 scif2: serial@e6e56000 {
963 compatible = "renesas,scif-r8a7742",
964 "renesas,rcar-gen2-scif", "renesas,scif";
965 reg = <0 0xe6e56000 0 0x40>;
966 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&cpg CPG_MOD 310>,
968 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
969 clock-names = "fck", "brg_int", "scif_clk";
970 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
971 <&dmac1 0x2b>, <&dmac1 0x2c>;
972 dma-names = "tx", "rx", "tx", "rx";
973 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
974 resets = <&cpg 310>;
975 status = "disabled";
976 };
977
978 hscif0: serial@e62c0000 {
979 compatible = "renesas,hscif-r8a7742",
980 "renesas,rcar-gen2-hscif", "renesas,hscif";
981 reg = <0 0xe62c0000 0 0x60>;
982 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&cpg CPG_MOD 717>,
984 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
985 clock-names = "fck", "brg_int", "scif_clk";
986 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
987 <&dmac1 0x39>, <&dmac1 0x3a>;
988 dma-names = "tx", "rx", "tx", "rx";
989 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
990 resets = <&cpg 717>;
991 status = "disabled";
992 };
993
994 hscif1: serial@e62c8000 {
995 compatible = "renesas,hscif-r8a7742",
996 "renesas,rcar-gen2-hscif", "renesas,hscif";
997 reg = <0 0xe62c8000 0 0x60>;
998 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&cpg CPG_MOD 716>,
1000 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
1001 clock-names = "fck", "brg_int", "scif_clk";
1002 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
1003 <&dmac1 0x4d>, <&dmac1 0x4e>;
1004 dma-names = "tx", "rx", "tx", "rx";
1005 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1006 resets = <&cpg 716>;
1007 status = "disabled";
1008 };
1009
1010 msiof0: spi@e6e20000 {
1011 compatible = "renesas,msiof-r8a7742",
1012 "renesas,rcar-gen2-msiof";
1013 reg = <0 0xe6e20000 0 0x0064>;
1014 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cpg CPG_MOD 0>;
1016 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1017 <&dmac1 0x51>, <&dmac1 0x52>;
1018 dma-names = "tx", "rx", "tx", "rx";
1019 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1020 resets = <&cpg 0>;
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 status = "disabled";
1024 };
1025
1026 msiof1: spi@e6e10000 {
1027 compatible = "renesas,msiof-r8a7742",
1028 "renesas,rcar-gen2-msiof";
1029 reg = <0 0xe6e10000 0 0x0064>;
1030 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&cpg CPG_MOD 208>;
1032 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1033 <&dmac1 0x55>, <&dmac1 0x56>;
1034 dma-names = "tx", "rx", "tx", "rx";
1035 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1036 resets = <&cpg 208>;
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1039 status = "disabled";
1040 };
1041
1042 msiof2: spi@e6e00000 {
1043 compatible = "renesas,msiof-r8a7742",
1044 "renesas,rcar-gen2-msiof";
1045 reg = <0 0xe6e00000 0 0x0064>;
1046 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1047 clocks = <&cpg CPG_MOD 205>;
1048 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1049 <&dmac1 0x41>, <&dmac1 0x42>;
1050 dma-names = "tx", "rx", "tx", "rx";
1051 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1052 resets = <&cpg 205>;
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1055 status = "disabled";
1056 };
1057
1058 msiof3: spi@e6c90000 {
1059 compatible = "renesas,msiof-r8a7742",
1060 "renesas,rcar-gen2-msiof";
1061 reg = <0 0xe6c90000 0 0x0064>;
1062 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&cpg CPG_MOD 215>;
1064 dmas = <&dmac0 0x45>, <&dmac0 0x46>,
1065 <&dmac1 0x45>, <&dmac1 0x46>;
1066 dma-names = "tx", "rx", "tx", "rx";
1067 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1068 resets = <&cpg 215>;
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071 status = "disabled";
1072 };
1073
1074 can0: can@e6e80000 {
1075 compatible = "renesas,can-r8a7742",
1076 "renesas,rcar-gen2-can";
1077 reg = <0 0xe6e80000 0 0x1000>;
1078 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1079 clocks = <&cpg CPG_MOD 916>,
1080 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
1081 clock-names = "clkp1", "clkp2", "can_clk";
1082 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1083 resets = <&cpg 916>;
1084 status = "disabled";
1085 };
1086
1087 can1: can@e6e88000 {
1088 compatible = "renesas,can-r8a7742",
1089 "renesas,rcar-gen2-can";
1090 reg = <0 0xe6e88000 0 0x1000>;
1091 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&cpg CPG_MOD 915>,
1093 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
1094 clock-names = "clkp1", "clkp2", "can_clk";
1095 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1096 resets = <&cpg 915>;
1097 status = "disabled";
1098 };
1099
1100 pwm0: pwm@e6e30000 {
1101 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
1102 reg = <0 0xe6e30000 0 0x8>;
1103 clocks = <&cpg CPG_MOD 523>;
1104 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1105 resets = <&cpg 523>;
1106 #pwm-cells = <2>;
1107 status = "disabled";
1108 };
1109
1110 pwm1: pwm@e6e31000 {
1111 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
1112 reg = <0 0xe6e31000 0 0x8>;
1113 clocks = <&cpg CPG_MOD 523>;
1114 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1115 resets = <&cpg 523>;
1116 #pwm-cells = <2>;
1117 status = "disabled";
1118 };
1119
1120 pwm2: pwm@e6e32000 {
1121 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
1122 reg = <0 0xe6e32000 0 0x8>;
1123 clocks = <&cpg CPG_MOD 523>;
1124 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1125 resets = <&cpg 523>;
1126 #pwm-cells = <2>;
1127 status = "disabled";
1128 };
1129
1130 pwm3: pwm@e6e33000 {
1131 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
1132 reg = <0 0xe6e33000 0 0x8>;
1133 clocks = <&cpg CPG_MOD 523>;
1134 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1135 resets = <&cpg 523>;
1136 #pwm-cells = <2>;
1137 status = "disabled";
1138 };
1139
1140 pwm4: pwm@e6e34000 {
1141 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
1142 reg = <0 0xe6e34000 0 0x8>;
1143 clocks = <&cpg CPG_MOD 523>;
1144 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1145 resets = <&cpg 523>;
1146 #pwm-cells = <2>;
1147 status = "disabled";
1148 };
1149
1150 pwm5: pwm@e6e35000 {
1151 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
1152 reg = <0 0xe6e35000 0 0x8>;
1153 clocks = <&cpg CPG_MOD 523>;
1154 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1155 resets = <&cpg 523>;
1156 #pwm-cells = <2>;
1157 status = "disabled";
1158 };
1159
1160 pwm6: pwm@e6e36000 {
1161 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
1162 reg = <0 0xe6e36000 0 0x8>;
1163 clocks = <&cpg CPG_MOD 523>;
1164 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1165 resets = <&cpg 523>;
1166 #pwm-cells = <2>;
1167 status = "disabled";
1168 };
1169
1170 vin0: video@e6ef0000 {
1171 compatible = "renesas,vin-r8a7742",
1172 "renesas,rcar-gen2-vin";
1173 reg = <0 0xe6ef0000 0 0x1000>;
1174 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1175 clocks = <&cpg CPG_MOD 811>;
1176 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1177 resets = <&cpg 811>;
1178 status = "disabled";
1179 };
1180
1181 vin1: video@e6ef1000 {
1182 compatible = "renesas,vin-r8a7742",
1183 "renesas,rcar-gen2-vin";
1184 reg = <0 0xe6ef1000 0 0x1000>;
1185 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1186 clocks = <&cpg CPG_MOD 810>;
1187 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1188 resets = <&cpg 810>;
1189 status = "disabled";
1190 };
1191
1192 vin2: video@e6ef2000 {
1193 compatible = "renesas,vin-r8a7742",
1194 "renesas,rcar-gen2-vin";
1195 reg = <0 0xe6ef2000 0 0x1000>;
1196 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&cpg CPG_MOD 809>;
1198 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1199 resets = <&cpg 809>;
1200 status = "disabled";
1201 };
1202
1203 vin3: video@e6ef3000 {
1204 compatible = "renesas,vin-r8a7742",
1205 "renesas,rcar-gen2-vin";
1206 reg = <0 0xe6ef3000 0 0x1000>;
1207 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cpg CPG_MOD 808>;
1209 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1210 resets = <&cpg 808>;
1211 status = "disabled";
1212 };
1213
1214 rcar_sound: sound@ec500000 {
1215 /*
1216 * #sound-dai-cells is required if simple-card
1217 *
1218 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1219 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1220 */
1221 compatible = "renesas,rcar_sound-r8a7742",
1222 "renesas,rcar_sound-gen2";
1223 reg = <0 0xec500000 0 0x1000>, /* SCU */
1224 <0 0xec5a0000 0 0x100>, /* ADG */
1225 <0 0xec540000 0 0x1000>, /* SSIU */
1226 <0 0xec541000 0 0x280>, /* SSI */
1227 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1228 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1229
1230 clocks = <&cpg CPG_MOD 1005>,
1231 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1232 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1233 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1234 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1235 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1236 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1237 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1238 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1239 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1240 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1241 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1242 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1243 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1244 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
1245 <&cpg CPG_CORE R8A7742_CLK_M2>;
1246 clock-names = "ssi-all",
1247 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1248 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1249 "ssi.1", "ssi.0",
1250 "src.9", "src.8", "src.7", "src.6",
1251 "src.5", "src.4", "src.3", "src.2",
1252 "src.1", "src.0",
1253 "ctu.0", "ctu.1",
1254 "mix.0", "mix.1",
1255 "dvc.0", "dvc.1",
1256 "clk_a", "clk_b", "clk_c", "clk_i";
1257 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1258 resets = <&cpg 1005>,
1259 <&cpg 1006>, <&cpg 1007>,
1260 <&cpg 1008>, <&cpg 1009>,
1261 <&cpg 1010>, <&cpg 1011>,
1262 <&cpg 1012>, <&cpg 1013>,
1263 <&cpg 1014>, <&cpg 1015>;
1264 reset-names = "ssi-all",
1265 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1266 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1267 "ssi.1", "ssi.0";
1268
1269 status = "disabled";
1270
1271 rcar_sound,dvc {
1272 dvc0: dvc-0 {
1273 dmas = <&audma1 0xbc>;
1274 dma-names = "tx";
1275 };
1276 dvc1: dvc-1 {
1277 dmas = <&audma1 0xbe>;
1278 dma-names = "tx";
1279 };
1280 };
1281
1282 rcar_sound,mix {
1283 mix0: mix-0 { };
1284 mix1: mix-1 { };
1285 };
1286
1287 rcar_sound,ctu {
1288 ctu00: ctu-0 { };
1289 ctu01: ctu-1 { };
1290 ctu02: ctu-2 { };
1291 ctu03: ctu-3 { };
1292 ctu10: ctu-4 { };
1293 ctu11: ctu-5 { };
1294 ctu12: ctu-6 { };
1295 ctu13: ctu-7 { };
1296 };
1297
1298 rcar_sound,src {
1299 src0: src-0 {
1300 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1301 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1302 dma-names = "rx", "tx";
1303 };
1304 src1: src-1 {
1305 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1306 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1307 dma-names = "rx", "tx";
1308 };
1309 src2: src-2 {
1310 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1311 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1312 dma-names = "rx", "tx";
1313 };
1314 src3: src-3 {
1315 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1316 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1317 dma-names = "rx", "tx";
1318 };
1319 src4: src-4 {
1320 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1321 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1322 dma-names = "rx", "tx";
1323 };
1324 src5: src-5 {
1325 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1326 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1327 dma-names = "rx", "tx";
1328 };
1329 src6: src-6 {
1330 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1331 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1332 dma-names = "rx", "tx";
1333 };
1334 src7: src-7 {
1335 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1336 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1337 dma-names = "rx", "tx";
1338 };
1339 src8: src-8 {
1340 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1341 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1342 dma-names = "rx", "tx";
1343 };
1344 src9: src-9 {
1345 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1346 dmas = <&audma0 0x97>, <&audma1 0xba>;
1347 dma-names = "rx", "tx";
1348 };
1349 };
1350
1351 rcar_sound,ssi {
1352 ssi0: ssi-0 {
1353 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1354 dmas = <&audma0 0x01>, <&audma1 0x02>,
1355 <&audma0 0x15>, <&audma1 0x16>;
1356 dma-names = "rx", "tx", "rxu", "txu";
1357 };
1358 ssi1: ssi-1 {
1359 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1360 dmas = <&audma0 0x03>, <&audma1 0x04>,
1361 <&audma0 0x49>, <&audma1 0x4a>;
1362 dma-names = "rx", "tx", "rxu", "txu";
1363 };
1364 ssi2: ssi-2 {
1365 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1366 dmas = <&audma0 0x05>, <&audma1 0x06>,
1367 <&audma0 0x63>, <&audma1 0x64>;
1368 dma-names = "rx", "tx", "rxu", "txu";
1369 };
1370 ssi3: ssi-3 {
1371 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1372 dmas = <&audma0 0x07>, <&audma1 0x08>,
1373 <&audma0 0x6f>, <&audma1 0x70>;
1374 dma-names = "rx", "tx", "rxu", "txu";
1375 };
1376 ssi4: ssi-4 {
1377 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1378 dmas = <&audma0 0x09>, <&audma1 0x0a>,
1379 <&audma0 0x71>, <&audma1 0x72>;
1380 dma-names = "rx", "tx", "rxu", "txu";
1381 };
1382 ssi5: ssi-5 {
1383 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1384 dmas = <&audma0 0x0b>, <&audma1 0x0c>,
1385 <&audma0 0x73>, <&audma1 0x74>;
1386 dma-names = "rx", "tx", "rxu", "txu";
1387 };
1388 ssi6: ssi-6 {
1389 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&audma0 0x0d>, <&audma1 0x0e>,
1391 <&audma0 0x75>, <&audma1 0x76>;
1392 dma-names = "rx", "tx", "rxu", "txu";
1393 };
1394 ssi7: ssi-7 {
1395 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1396 dmas = <&audma0 0x0f>, <&audma1 0x10>,
1397 <&audma0 0x79>, <&audma1 0x7a>;
1398 dma-names = "rx", "tx", "rxu", "txu";
1399 };
1400 ssi8: ssi-8 {
1401 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1402 dmas = <&audma0 0x11>, <&audma1 0x12>,
1403 <&audma0 0x7b>, <&audma1 0x7c>;
1404 dma-names = "rx", "tx", "rxu", "txu";
1405 };
1406 ssi9: ssi-9 {
1407 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1408 dmas = <&audma0 0x13>, <&audma1 0x14>,
1409 <&audma0 0x7d>, <&audma1 0x7e>;
1410 dma-names = "rx", "tx", "rxu", "txu";
1411 };
1412 };
1413 };
1414
1415 audma0: dma-controller@ec700000 {
1416 compatible = "renesas,dmac-r8a7742",
1417 "renesas,rcar-dmac";
1418 reg = <0 0xec700000 0 0x10000>;
1419 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
1420 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1425 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1426 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1427 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1429 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1432 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1433 interrupt-names = "error",
1434 "ch0", "ch1", "ch2", "ch3",
1435 "ch4", "ch5", "ch6", "ch7",
1436 "ch8", "ch9", "ch10", "ch11",
1437 "ch12";
1438 clocks = <&cpg CPG_MOD 502>;
1439 clock-names = "fck";
1440 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1441 resets = <&cpg 502>;
1442 #dma-cells = <1>;
1443 dma-channels = <13>;
1444 };
1445
1446 audma1: dma-controller@ec720000 {
1447 compatible = "renesas,dmac-r8a7742",
1448 "renesas,rcar-dmac";
1449 reg = <0 0xec720000 0 0x10000>;
1450 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1455 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1457 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1460 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1463 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1464 interrupt-names = "error",
1465 "ch0", "ch1", "ch2", "ch3",
1466 "ch4", "ch5", "ch6", "ch7",
1467 "ch8", "ch9", "ch10", "ch11",
1468 "ch12";
1469 clocks = <&cpg CPG_MOD 501>;
1470 clock-names = "fck";
1471 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1472 resets = <&cpg 501>;
1473 #dma-cells = <1>;
1474 dma-channels = <13>;
1475 };
1476
1477 xhci: usb@ee000000 {
1478 compatible = "renesas,xhci-r8a7742",
1479 "renesas,rcar-gen2-xhci";
1480 reg = <0 0xee000000 0 0xc00>;
1481 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1482 clocks = <&cpg CPG_MOD 328>;
1483 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1484 resets = <&cpg 328>;
1485 phys = <&usb2 1>;
1486 phy-names = "usb";
1487 status = "disabled";
1488 };
1489
1490 pci0: pci@ee090000 {
1491 compatible = "renesas,pci-r8a7742",
1492 "renesas,pci-rcar-gen2";
1493 device_type = "pci";
1494 reg = <0 0xee090000 0 0xc00>,
1495 <0 0xee080000 0 0x1100>;
1496 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1497 clocks = <&cpg CPG_MOD 703>;
1498 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1499 resets = <&cpg 703>;
1500 status = "disabled";
1501
1502 bus-range = <0 0>;
1503 #address-cells = <3>;
1504 #size-cells = <2>;
1505 #interrupt-cells = <1>;
1506 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1507 interrupt-map-mask = <0xf800 0 0 0x7>;
1508 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1509 <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1510 <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1511
1512 usb@1,0 {
1513 reg = <0x800 0 0 0 0>;
1514 phys = <&usb0 0>;
1515 phy-names = "usb";
1516 };
1517
1518 usb@2,0 {
1519 reg = <0x1000 0 0 0 0>;
1520 phys = <&usb0 0>;
1521 phy-names = "usb";
1522 };
1523 };
1524
1525 pci1: pci@ee0b0000 {
1526 compatible = "renesas,pci-r8a7742",
1527 "renesas,pci-rcar-gen2";
1528 device_type = "pci";
1529 reg = <0 0xee0b0000 0 0xc00>,
1530 <0 0xee0a0000 0 0x1100>;
1531 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1532 clocks = <&cpg CPG_MOD 703>;
1533 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1534 resets = <&cpg 703>;
1535 status = "disabled";
1536
1537 bus-range = <1 1>;
1538 #address-cells = <3>;
1539 #size-cells = <2>;
1540 #interrupt-cells = <1>;
1541 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1542 interrupt-map-mask = <0xf800 0 0 0x7>;
1543 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1544 <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1545 <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1546 };
1547
1548 pci2: pci@ee0d0000 {
1549 compatible = "renesas,pci-r8a7742",
1550 "renesas,pci-rcar-gen2";
1551 device_type = "pci";
1552 clocks = <&cpg CPG_MOD 703>;
1553 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1554 resets = <&cpg 703>;
1555 reg = <0 0xee0d0000 0 0xc00>,
1556 <0 0xee0c0000 0 0x1100>;
1557 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1558 status = "disabled";
1559
1560 bus-range = <2 2>;
1561 #address-cells = <3>;
1562 #size-cells = <2>;
1563 #interrupt-cells = <1>;
1564 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1565 interrupt-map-mask = <0xf800 0 0 0x7>;
1566 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1567 <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1568 <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1569
1570 usb@1,0 {
1571 reg = <0x20800 0 0 0 0>;
1572 phys = <&usb2 0>;
1573 phy-names = "usb";
1574 };
1575
1576 usb@2,0 {
1577 reg = <0x21000 0 0 0 0>;
1578 phys = <&usb2 0>;
1579 phy-names = "usb";
1580 };
1581 };
1582
1583 sdhi0: mmc@ee100000 {
1584 compatible = "renesas,sdhi-r8a7742",
1585 "renesas,rcar-gen2-sdhi";
1586 reg = <0 0xee100000 0 0x328>;
1587 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1588 clocks = <&cpg CPG_MOD 314>;
1589 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1590 <&dmac1 0xcd>, <&dmac1 0xce>;
1591 dma-names = "tx", "rx", "tx", "rx";
1592 max-frequency = <195000000>;
1593 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1594 resets = <&cpg 314>;
1595 status = "disabled";
1596 };
1597
1598 sdhi1: mmc@ee120000 {
1599 compatible = "renesas,sdhi-r8a7742",
1600 "renesas,rcar-gen2-sdhi";
1601 reg = <0 0xee120000 0 0x328>;
1602 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1603 clocks = <&cpg CPG_MOD 313>;
1604 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
1605 <&dmac1 0xc9>, <&dmac1 0xca>;
1606 dma-names = "tx", "rx", "tx", "rx";
1607 max-frequency = <195000000>;
1608 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1609 resets = <&cpg 313>;
1610 status = "disabled";
1611 };
1612
1613 sdhi2: mmc@ee140000 {
1614 compatible = "renesas,sdhi-r8a7742",
1615 "renesas,rcar-gen2-sdhi";
1616 reg = <0 0xee140000 0 0x100>;
1617 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&cpg CPG_MOD 312>;
1619 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1620 <&dmac1 0xc1>, <&dmac1 0xc2>;
1621 dma-names = "tx", "rx", "tx", "rx";
1622 max-frequency = <97500000>;
1623 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1624 resets = <&cpg 312>;
1625 status = "disabled";
1626 };
1627
1628 sdhi3: mmc@ee160000 {
1629 compatible = "renesas,sdhi-r8a7742",
1630 "renesas,rcar-gen2-sdhi";
1631 reg = <0 0xee160000 0 0x100>;
1632 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1633 clocks = <&cpg CPG_MOD 311>;
1634 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1635 <&dmac1 0xd3>, <&dmac1 0xd4>;
1636 dma-names = "tx", "rx", "tx", "rx";
1637 max-frequency = <97500000>;
1638 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1639 resets = <&cpg 311>;
1640 status = "disabled";
1641 };
1642
1643 mmcif0: mmc@ee200000 {
1644 compatible = "renesas,mmcif-r8a7742",
1645 "renesas,sh-mmcif";
1646 reg = <0 0xee200000 0 0x80>;
1647 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1648 clocks = <&cpg CPG_MOD 315>;
1649 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1650 <&dmac1 0xd1>, <&dmac1 0xd2>;
1651 dma-names = "tx", "rx", "tx", "rx";
1652 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1653 resets = <&cpg 315>;
1654 reg-io-width = <4>;
1655 status = "disabled";
1656 max-frequency = <97500000>;
1657 };
1658
1659 mmcif1: mmc@ee220000 {
1660 compatible = "renesas,mmcif-r8a7742",
1661 "renesas,sh-mmcif";
1662 reg = <0 0xee220000 0 0x80>;
1663 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1664 clocks = <&cpg CPG_MOD 305>;
1665 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
1666 <&dmac1 0xe1>, <&dmac1 0xe2>;
1667 dma-names = "tx", "rx", "tx", "rx";
1668 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1669 resets = <&cpg 305>;
1670 reg-io-width = <4>;
1671 status = "disabled";
1672 max-frequency = <97500000>;
1673 };
1674
1675 sata0: sata@ee300000 {
1676 compatible = "renesas,sata-r8a7742",
1677 "renesas,rcar-gen2-sata";
1678 reg = <0 0xee300000 0 0x200000>;
1679 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1680 clocks = <&cpg CPG_MOD 815>;
1681 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1682 resets = <&cpg 815>;
1683 status = "disabled";
1684 };
1685
1686 sata1: sata@ee500000 {
1687 compatible = "renesas,sata-r8a7742",
1688 "renesas,rcar-gen2-sata";
1689 reg = <0 0xee500000 0 0x200000>;
1690 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1691 clocks = <&cpg CPG_MOD 814>;
1692 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1693 resets = <&cpg 814>;
1694 status = "disabled";
1695 };
1696
1697 ether: ethernet@ee700000 {
1698 compatible = "renesas,ether-r8a7742",
1699 "renesas,rcar-gen2-ether";
1700 reg = <0 0xee700000 0 0x400>;
1701 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1702 clocks = <&cpg CPG_MOD 813>;
1703 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1704 resets = <&cpg 813>;
1705 phy-mode = "rmii";
1706 #address-cells = <1>;
1707 #size-cells = <0>;
1708 status = "disabled";
1709 };
1710
1711 gic: interrupt-controller@f1001000 {
1712 compatible = "arm,gic-400";
1713 #interrupt-cells = <3>;
1714 #address-cells = <0>;
1715 interrupt-controller;
1716 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
1717 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
1718 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1719 clocks = <&cpg CPG_MOD 408>;
1720 clock-names = "clk";
1721 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1722 resets = <&cpg 408>;
1723 };
1724
1725 pciec: pcie@fe000000 {
1726 compatible = "renesas,pcie-r8a7742",
1727 "renesas,pcie-rcar-gen2";
1728 reg = <0 0xfe000000 0 0x80000>;
1729 #address-cells = <3>;
1730 #size-cells = <2>;
1731 bus-range = <0x00 0xff>;
1732 device_type = "pci";
1733 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1734 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1735 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1736 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1737 /* Map all possible DDR as inbound ranges */
1738 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
1739 <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1740 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1743 #interrupt-cells = <1>;
1744 interrupt-map-mask = <0 0 0 0>;
1745 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1746 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1747 clock-names = "pcie", "pcie_bus";
1748 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1749 resets = <&cpg 319>;
1750 status = "disabled";
1751 };
1752
1753 vsp@fe920000 {
1754 compatible = "renesas,vsp1";
1755 reg = <0 0xfe920000 0 0x8000>;
1756 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1757 clocks = <&cpg CPG_MOD 130>;
1758 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1759 resets = <&cpg 130>;
1760 };
1761
1762 vsp@fe928000 {
1763 compatible = "renesas,vsp1";
1764 reg = <0 0xfe928000 0 0x8000>;
1765 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
1766 clocks = <&cpg CPG_MOD 131>;
1767 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1768 resets = <&cpg 131>;
1769 };
1770
1771 vsp@fe930000 {
1772 compatible = "renesas,vsp1";
1773 reg = <0 0xfe930000 0 0x8000>;
1774 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1775 clocks = <&cpg CPG_MOD 128>;
1776 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1777 resets = <&cpg 128>;
1778 };
1779
1780 vsp@fe938000 {
1781 compatible = "renesas,vsp1";
1782 reg = <0 0xfe938000 0 0x8000>;
1783 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1784 clocks = <&cpg CPG_MOD 127>;
1785 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1786 resets = <&cpg 127>;
1787 };
1788
1789 du: display@feb00000 {
1790 compatible = "renesas,du-r8a7742";
1791 reg = <0 0xfeb00000 0 0x70000>;
1792 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1793 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1794 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1795 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
1796 <&cpg CPG_MOD 722>;
1797 clock-names = "du.0", "du.1", "du.2";
1798 resets = <&cpg 724>;
1799 reset-names = "du.0";
1800 status = "disabled";
1801
1802 ports {
1803 #address-cells = <1>;
1804 #size-cells = <0>;
1805
1806 port@0 {
1807 reg = <0>;
1808 du_out_rgb: endpoint {
1809 };
1810 };
1811 port@1 {
1812 reg = <1>;
1813 du_out_lvds0: endpoint {
1814 remote-endpoint = <&lvds0_in>;
1815 };
1816 };
1817 port@2 {
1818 reg = <2>;
1819 du_out_lvds1: endpoint {
1820 remote-endpoint = <&lvds1_in>;
1821 };
1822 };
1823 };
1824 };
1825
1826 lvds0: lvds@feb90000 {
1827 compatible = "renesas,r8a7742-lvds";
1828 reg = <0 0xfeb90000 0 0x14>;
1829 clocks = <&cpg CPG_MOD 726>;
1830 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1831 resets = <&cpg 726>;
1832 status = "disabled";
1833
1834 ports {
1835 #address-cells = <1>;
1836 #size-cells = <0>;
1837
1838 port@0 {
1839 reg = <0>;
1840 lvds0_in: endpoint {
1841 remote-endpoint = <&du_out_lvds0>;
1842 };
1843 };
1844 port@1 {
1845 reg = <1>;
1846 lvds0_out: endpoint {
1847 };
1848 };
1849 };
1850 };
1851
1852 lvds1: lvds@feb94000 {
1853 compatible = "renesas,r8a7742-lvds";
1854 reg = <0 0xfeb94000 0 0x14>;
1855 clocks = <&cpg CPG_MOD 725>;
1856 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1857 resets = <&cpg 725>;
1858 status = "disabled";
1859
1860 ports {
1861 #address-cells = <1>;
1862 #size-cells = <0>;
1863
1864 port@0 {
1865 reg = <0>;
1866 lvds1_in: endpoint {
1867 remote-endpoint = <&du_out_lvds1>;
1868 };
1869 };
1870 port@1 {
1871 reg = <1>;
1872 lvds1_out: endpoint {
1873 };
1874 };
1875 };
1876 };
1877
1878 prr: chipid@ff000044 {
1879 compatible = "renesas,prr";
1880 reg = <0 0xff000044 0 4>;
1881 };
1882
1883 cmt0: timer@ffca0000 {
1884 compatible = "renesas,r8a7742-cmt0",
1885 "renesas,rcar-gen2-cmt0";
1886 reg = <0 0xffca0000 0 0x1004>;
1887 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1888 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1889 clocks = <&cpg CPG_MOD 124>;
1890 clock-names = "fck";
1891 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1892 resets = <&cpg 124>;
1893 status = "disabled";
1894 };
1895
1896 cmt1: timer@e6130000 {
1897 compatible = "renesas,r8a7742-cmt1",
1898 "renesas,rcar-gen2-cmt1";
1899 reg = <0 0xe6130000 0 0x1004>;
1900 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1901 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1902 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1903 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1905 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1906 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1907 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1908 clocks = <&cpg CPG_MOD 329>;
1909 clock-names = "fck";
1910 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
1911 resets = <&cpg 329>;
1912 status = "disabled";
1913 };
1914 };
1915
1916 thermal-zones {
1917 cpu_thermal: cpu-thermal {
1918 polling-delay-passive = <0>;
1919 polling-delay = <0>;
1920
1921 thermal-sensors = <&thermal>;
1922
1923 trips {
1924 cpu-crit {
1925 temperature = <95000>;
1926 hysteresis = <0>;
1927 type = "critical";
1928 };
1929 };
1930 cooling-maps {
1931 };
1932 };
1933 };
1934
1935 timer {
1936 compatible = "arm,armv7-timer";
1937 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1938 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1939 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1940 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1941 };
1942
1943 /* External USB clock - can be overridden by the board */
1944 usb_extal_clk: usb_extal {
1945 compatible = "fixed-clock";
1946 #clock-cells = <0>;
1947 clock-frequency = <48000000>;
1948 };
1949};