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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx7d-zii-rmu2.dts
blob: 521493342fe972812c0947bccc10819b536a4f71 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device tree file for ZII's RMU2 board
4 *
5 * RMU - Remote Modem Unit
6 *
7 * Copyright (C) 2019 Zodiac Inflight Innovations
8 */
9
10/dts-v1/;
11#include <dt-bindings/thermal/thermal.h>
12#include "imx7d.dtsi"
13
14/ {
15 model = "ZII RMU2 Board";
16 compatible = "zii,imx7d-rmu2", "fsl,imx7d";
17
18 chosen {
19 stdout-path = &uart2;
20 };
21
22 gpio-leds {
23 compatible = "gpio-leds";
24 pinctrl-0 = <&pinctrl_leds_debug>;
25 pinctrl-names = "default";
26
27 led-debug {
28 label = "zii:green:debug1";
29 gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
30 linux,default-trigger = "heartbeat";
31 };
32 };
33};
34
35&cpu0 {
36 cpu-supply = <&sw1a_reg>;
37};
38
39&ecspi1 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_ecspi1>;
42 cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
43 status = "okay";
44
45 flash@0 {
46 compatible = "jedec,spi-nor";
47 spi-max-frequency = <20000000>;
48 reg = <0>;
49 #address-cells = <1>;
50 #size-cells = <1>;
51 };
52};
53
54&fec1 {
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_enet1>;
57 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
58 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
59 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
60 assigned-clock-rates = <0>, <100000000>;
61 phy-mode = "rgmii-id";
62 phy-handle = <&fec1_phy>;
63 status = "okay";
64
65 mdio {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 fec1_phy: ethernet-phy@0 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_enet1_phy_reset>,
72 <&pinctrl_enet1_phy_interrupt>;
73 reg = <0>;
74 interrupt-parent = <&gpio1>;
75 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
76 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
77 };
78 };
79};
80
81&i2c1 {
82 clock-frequency = <100000>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_i2c1>;
85 status = "okay";
86
87 pmic@8 {
88 compatible = "fsl,pfuze3000";
89 reg = <0x08>;
90
91 regulators {
92 sw1a_reg: sw1a {
93 regulator-min-microvolt = <700000>;
94 regulator-max-microvolt = <3300000>;
95 regulator-boot-on;
96 regulator-always-on;
97 regulator-ramp-delay = <6250>;
98 };
99
100 sw1c_reg: sw1b {
101 regulator-min-microvolt = <700000>;
102 regulator-max-microvolt = <1475000>;
103 regulator-boot-on;
104 regulator-always-on;
105 regulator-ramp-delay = <6250>;
106 };
107
108 sw2_reg: sw2 {
109 regulator-min-microvolt = <1500000>;
110 regulator-max-microvolt = <1850000>;
111 regulator-boot-on;
112 regulator-always-on;
113 };
114
115 sw3a_reg: sw3 {
116 regulator-min-microvolt = <900000>;
117 regulator-max-microvolt = <1650000>;
118 regulator-boot-on;
119 regulator-always-on;
120 };
121
122 swbst_reg: swbst {
123 regulator-min-microvolt = <5000000>;
124 regulator-max-microvolt = <5150000>;
125 };
126
127 snvs_reg: vsnvs {
128 regulator-min-microvolt = <1000000>;
129 regulator-max-microvolt = <3000000>;
130 regulator-boot-on;
131 regulator-always-on;
132 };
133
134 vref_reg: vrefddr {
135 regulator-boot-on;
136 regulator-always-on;
137 };
138
139 vgen1_reg: vldo1 {
140 regulator-min-microvolt = <1800000>;
141 regulator-max-microvolt = <3300000>;
142 regulator-always-on;
143 };
144
145 vgen2_reg: vldo2 {
146 regulator-min-microvolt = <800000>;
147 regulator-max-microvolt = <1550000>;
148 regulator-always-on;
149 };
150
151 vgen3_reg: vccsd {
152 regulator-min-microvolt = <2850000>;
153 regulator-max-microvolt = <3300000>;
154 regulator-always-on;
155 };
156
157 vgen4_reg: v33 {
158 regulator-min-microvolt = <2850000>;
159 regulator-max-microvolt = <3300000>;
160 regulator-always-on;
161 };
162
163 vgen5_reg: vldo3 {
164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <3300000>;
166 regulator-always-on;
167 };
168
169 vgen6_reg: vldo4 {
170 regulator-min-microvolt = <1800000>;
171 regulator-max-microvolt = <3300000>;
172 regulator-always-on;
173 };
174 };
175 };
176
177 eeprom@50 {
178 compatible = "atmel,24c04";
179 reg = <0x50>;
180 };
181
182 eeprom@52 {
183 compatible = "atmel,24c04";
184 reg = <0x52>;
185 };
186};
187
188&snvs_rtc {
189 status = "disabled";
190};
191
192&uart2 {
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_uart2>;
195 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
196 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
197 status = "okay";
198};
199
200&uart4 {
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_uart4>;
203 assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
204 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
205 status = "okay";
206
207 mcu {
208 compatible = "zii,rave-sp-rdu2";
209 current-speed = <1000000>;
210 #address-cells = <1>;
211 #size-cells = <1>;
212
213 watchdog {
214 compatible = "zii,rave-sp-watchdog";
215 };
216
217 eeprom@a3 {
218 compatible = "zii,rave-sp-eeprom";
219 reg = <0xa3 0x4000>;
220 #address-cells = <1>;
221 #size-cells = <1>;
222 zii,eeprom-name = "main-eeprom";
223 };
224 };
225};
226
227&usbotg2 {
228 dr_mode = "host";
229 disable-over-current;
230 status = "okay";
231};
232
233&usdhc1 {
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_usdhc1>;
236 bus-width = <4>;
237 no-1-8-v;
238 no-sdio;
239 keep-power-in-suspend;
240 status = "okay";
241};
242
243&usdhc3 {
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_usdhc3>;
246 bus-width = <8>;
247 no-1-8-v;
248 non-removable;
249 no-sdio;
250 no-sd;
251 keep-power-in-suspend;
252 status = "okay";
253};
254
255&wdog1 {
256 status = "disabled";
257};
258
259&iomuxc {
260 pinctrl_ecspi1: ecspi1grp {
261 fsl,pins = <
262 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
263 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
264 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
265 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59
266 >;
267 };
268
269 pinctrl_enet1: enet1grp {
270 fsl,pins = <
271 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
272 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
273 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
274 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
275 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
276 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
277 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
278 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
279 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
280 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
281 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
282 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
283 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
284 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
285 >;
286 };
287
288 pinctrl_enet1_phy_reset: enet1phyresetgrp {
289 fsl,pins = <
290 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14
291
292 >;
293 };
294
295 pinctrl_i2c1: i2c1grp {
296 fsl,pins = <
297 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
298 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
299 >;
300 };
301
302 pinctrl_leds_debug: ledsgrp {
303 fsl,pins = <
304 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59
305 >;
306 };
307
308
309 pinctrl_uart2: uart2grp {
310 fsl,pins = <
311 MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
312 MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
313 >;
314 };
315
316 pinctrl_uart4: uart4grp {
317 fsl,pins = <
318 MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79
319 MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79
320 >;
321 };
322
323 pinctrl_usdhc1: usdhc1grp {
324 fsl,pins = <
325 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
326 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
327 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
328 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
329 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
330 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
331 >;
332 };
333
334 pinctrl_usdhc3: usdhc3grp {
335 fsl,pins = <
336 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
337 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
338 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
339 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
340 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
341 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
342 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
343 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
344 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
345 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
346 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59
347 >;
348 };
349};
350
351&iomuxc_lpsr {
352 pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp {
353 fsl,phy = <
354 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08
355 >;
356 };
357};