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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx7d-smegw01.dts
blob: 7ed27c7ad726fa0f0328778fc351be8ab226eba4 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2//
3// Copyright (C) 2020 PHYTEC Messtechnik GmbH
4// Author: Jens Lang <J.Lang@phytec.de>
5// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
6
7/dts-v1/;
8#include <dt-bindings/gpio/gpio.h>
9#include "imx7d.dtsi"
10
11/ {
12 model = "Storopack SMEGW01 board";
13 compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
14
15 aliases {
16 ethernet0 = &fec1;
17 ethernet1 = &fec2;
18 mmc0 = &usdhc1;
19 mmc1 = &usdhc3;
20 mmc2 = &usdhc2;
21 rtc0 = &i2c_rtc;
22 rtc1 = &snvs_rtc;
23 };
24
25 chosen {
26 stdout-path = &uart1;
27 };
28
29 memory@80000000 {
30 device_type = "memory";
31 reg = <0x80000000 0x20000000>;
32 };
33
34 reg_lte_on: regulator-lte-on {
35 compatible = "regulator-fixed";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_lte_on>;
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-name = "lte_on";
41 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
42 enable-active-high;
43 regulator-always-on;
44 };
45
46 reg_lte_nreset: regulator-lte-nreset {
47 compatible = "regulator-fixed";
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_lte_nreset>;
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 regulator-name = "LTE_nReset";
53 gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
54 enable-active-high;
55 regulator-always-on;
56 };
57
58 reg_wifi: regulator-wifi {
59 compatible = "regulator-fixed";
60 gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>;
61 enable-active-high;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_wifi>;
64 regulator-name = "wifi_reg";
65 regulator-min-microvolt = <3300000>;
66 regulator-max-microvolt = <3300000>;
67 };
68
69 reg_wlan_rfkill: regulator-wlan-rfkill {
70 compatible = "regulator-fixed";
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_rfkill>;
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 regulator-name = "wlan_rfkill";
76 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
77 enable-active-high;
78 regulator-always-on;
79 };
80
81 reg_usbotg_vbus: regulator-usbotg-vbus {
82 compatible = "regulator-fixed";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>;
85 regulator-name = "usb_otg_vbus";
86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <5000000>;
88 gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>;
89 enable-active-high;
90 };
91};
92
93&ecspi1 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_ecspi1>;
96 cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
97 status = "okay";
98
99 sram@0 {
100 compatible = "microchip,48l640";
101 reg = <0>;
102 spi-max-frequency = <16000000>;
103 };
104};
105
106&fec1 {
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_enet1>;
109 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
110 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
111 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
112 assigned-clock-rates = <0>, <100000000>;
113 phy-mode = "rgmii-id";
114 phy-handle = <&ethphy0>;
115 fsl,magic-packet;
116 status = "okay";
117
118 mdio: mdio {
119 #address-cells = <1>;
120 #size-cells = <0>;
121
122 ethphy0: ethernet-phy@1 {
123 compatible = "ethernet-phy-id0022.1622",
124 "ethernet-phy-ieee802.3-c22";
125 reg = <1>;
126 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
127 };
128
129 ethphy1: ethernet-phy@2 {
130 compatible = "ethernet-phy-id0022.1622",
131 "ethernet-phy-ieee802.3-c22";
132 reg = <2>;
133 };
134 };
135};
136
137&fec2 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_enet2>;
140 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
141 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
142 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
143 assigned-clock-rates = <0>, <100000000>;
144 phy-mode = "rgmii-id";
145 phy-handle = <&ethphy1>;
146 fsl,magic-packet;
147 status = "okay";
148};
149
150&i2c2 {
151 pinctrl-names = "default";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]152 pinctrl-0 = <&pinctrl_i2c2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]153 clock-frequency = <100000>;
154 status = "okay";
155
156 i2c_rtc: rtc@52 {
157 compatible = "microcrystal,rv3028";
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_rtc_int>;
160 reg = <0x52>;
161 interrupt-parent = <&gpio2>;
162 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
163 };
164};
165
166&flexcan1 {
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_flexcan1>;
169 status = "okay";
170};
171
172&flexcan2 {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_flexcan2>;
175 status = "okay";
176};
177
178&uart1 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart1>;
181 status = "okay";
182};
183
184&uart3 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart3>;
187 status = "okay";
188};
189
190&usbotg1 {
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_usbotg1_lpsr>;
193 dr_mode = "otg";
194 vbus-supply = <&reg_usbotg_vbus>;
195 status = "okay";
196};
197
198&usbotg2 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_usbotg2>;
201 over-current-active-low;
202 dr_mode = "host";
203 status = "okay";
204};
205
206&usdhc1 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_usdhc1>;
209 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
210 no-1-8-v;
211 wakeup-source;
212 keep-power-in-suspend;
213 status = "okay";
214};
215
216&usdhc2 {
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_usdhc2>;
219 bus-width = <4>;
220 no-1-8-v;
221 non-removable;
222 vmmc-supply = <&reg_wifi>;
223 wakeup-source;
224 status = "okay";
225};
226
227&usdhc3 {
228 pinctrl-names = "default", "state_100mhz", "state_200mhz";
229 pinctrl-0 = <&pinctrl_usdhc3>;
230 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
231 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
232 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
233 assigned-clock-rates = <400000000>;
234 max-frequency = <200000000>;
235 bus-width = <8>;
236 fsl,tuning-step = <1>;
237 non-removable;
238 cap-mmc-highspeed;
239 cap-mmc-hw-reset;
240 mmc-hs200-1_8v;
241 mmc-ddr-1_8v;
242 status = "okay";
243};
244
245&wdog1 {
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_wdog>;
248 fsl,ext-reset-output;
249 status = "okay";
250};
251
252&iomuxc {
253 pinctrl_ecspi1: ecspi1grp {
254 fsl,pins = <
255 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04
256 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04
257 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04
258 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04
259 >;
260 };
261
262 pinctrl_enet1: enet1grp {
263 fsl,pins = <
264 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
265 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
266 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
267 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
268 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
269 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
270 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
271 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
272 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
273 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
274 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
275 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
276 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
277 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
278 >;
279 };
280
281 pinctrl_enet2: enet2grp {
282 fsl,pins = <
283 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5
284 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5
285 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5
286 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5
287 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5
288 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5
289 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5
290 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5
291 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5
292 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5
293 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5
294 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5
295 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08
296 >;
297 };
298
299 pinctrl_i2c2: i2c2grp {
300 fsl,pins = <
301 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004
302 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004
303 >;
304 };
305
306 pinctrl_flexcan1: flexcan1grp {
307 fsl,pins = <
308 MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0
309 MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0
310 >;
311 };
312
313 pinctrl_flexcan2: flexcan2grp {
314 fsl,pins = <
315 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0
316 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0
317 >;
318 };
319
320 pinctrl_lte_on: lteongrp {
321 fsl,pins = <
322 MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059
323 >;
324 };
325
326 pinctrl_lte_nreset: ltenresetgrp {
327 fsl,pins = <
328 MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059
329 >;
330 };
331
332 pinctrl_rfkill: rfkillgrp {
333 fsl,pins = <
334 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059
335 >;
336 };
337
338 pinctrl_rtc_int: rtcintgrp {
339 fsl,pins = <
340 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059
341 >;
342 };
343
344 pinctrl_uart1: uart1grp {
345 fsl,pins = <
346 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
347 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
348 >;
349 };
350
351 pinctrl_uart3: uart3grp {
352 fsl,pins = <
353 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c
354 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74
355 >;
356 };
357
358 pinctrl_usbotg1_lpsr: usbotg1grp {
359 fsl,pins = <
360 MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04
361 >;
362 };
363
364 pinctrl_usbotg1_pwr: usbotg1-pwrgrp {
365 fsl,pins = <
366 MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04
367 >;
368 };
369
370 pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpiogrp {
371 fsl,pins = <
372 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04
373 >;
374 };
375
376 pinctrl_usbotg2: usbotg2grp {
377 fsl,pins = <
378 MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x5c
379 >;
380 };
381
382 pinctrl_usdhc1: usdhc1grp {
383 fsl,pins = <
384 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
385 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
386 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
387 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
388 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
389 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
390 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
391 >;
392 };
393
394 pinctrl_usdhc2: usdhc2grp {
395 fsl,pins = <
396 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
397 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
398 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
399 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
400 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
401 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
402 MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08
403 >;
404 };
405
406 pinctrl_usdhc3: usdhc3grp {
407 fsl,pins = <
408 MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
409 MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
410 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
411 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
412 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
413 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
414 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
415 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
416 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
417 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
418 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
419 >;
420 };
421
422 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
423 fsl,pins = <
424 MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
425 MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
426 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
427 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
428 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
429 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
430 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
431 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
432 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
433 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
434 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
435 >;
436 };
437
438 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
439 fsl,pins = <
440 MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
441 MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
442 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
443 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
444 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
445 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
446 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
447 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
448 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
449 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
450 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
451 >;
452 };
453
454 pinctrl_wifi: wifigrp {
455 fsl,pins = <
456 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04
457 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04
458 >;
459 };
460};
461
462&iomuxc_lpsr {
463 pinctrl_wdog: wdoggrp {
464 fsl,pins = <
465 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
466 >;
467 };
468};