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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx7d-sdb.dts
blob: 0462e43ec09be5a658e0cf255fce14117837cb65 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright (C) 2015 Freescale Semiconductor, Inc.
4
5/dts-v1/;
6
7#include "imx7d.dtsi"
8
9/ {
10 model = "Freescale i.MX7 SabreSD Board";
11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
12
13 aliases {
14 ethernet0 = &fec1;
15 ethernet1 = &fec2;
16 };
17
18 chosen {
19 stdout-path = &uart1;
20 };
21
22 memory@80000000 {
23 device_type = "memory";
24 reg = <0x80000000 0x80000000>;
25 };
26
27 gpio-keys {
28 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpio_keys>;
31
32 key-volume-up {
33 label = "Volume Up";
34 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_VOLUMEUP>;
36 wakeup-source;
37 };
38
39 key-volume-down {
40 label = "Volume Down";
41 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_VOLUMEDOWN>;
43 wakeup-source;
44 };
45 };
46
47 spi-4 {
48 compatible = "spi-gpio";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_spi4>;
51 sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
52 mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
53 cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
54 num-chipselects = <1>;
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 extended_io: gpio-expander@0 {
59 compatible = "fairchild,74hc595";
60 gpio-controller;
61 #gpio-cells = <2>;
62 reg = <0>;
63 registers-number = <1>;
64 spi-max-frequency = <100000>;
65 };
66 };
67
68 reg_sd1_vmmc: regulator-sd1-vmmc {
69 compatible = "regulator-fixed";
70 regulator-name = "VDD_SD1";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
74 enable-active-high;
75 startup-delay-us = <200000>;
76 off-on-delay-us = <20000>;
77 };
78
79 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
80 compatible = "regulator-fixed";
81 regulator-name = "usb_otg1_vbus";
82 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <5000000>;
84 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
85 enable-active-high;
86 };
87
88 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
89 compatible = "regulator-fixed";
90 regulator-name = "usb_otg2_vbus";
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
93 regulator-min-microvolt = <5000000>;
94 regulator-max-microvolt = <5000000>;
95 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
96 enable-active-high;
97 };
98
99 reg_vref_1v8: regulator-vref-1v8 {
100 compatible = "regulator-fixed";
101 regulator-name = "vref-1v8";
102 regulator-min-microvolt = <1800000>;
103 regulator-max-microvolt = <1800000>;
104 };
105
106 reg_brcm: regulator-brcm {
107 compatible = "regulator-fixed";
108 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
109 enable-active-high;
110 regulator-name = "brcm_reg";
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_brcm_reg>;
113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <3300000>;
115 startup-delay-us = <200000>;
116 };
117
118 reg_lcd_3v3: regulator-lcd-3v3 {
119 compatible = "regulator-fixed";
120 regulator-name = "lcd-3v3";
121 regulator-min-microvolt = <3300000>;
122 regulator-max-microvolt = <3300000>;
123 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
124 };
125
126 reg_can2_3v3: regulator-can2-3v3 {
127 compatible = "regulator-fixed";
128 regulator-name = "can2-3v3";
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_flexcan2_reg>;
131 regulator-min-microvolt = <3300000>;
132 regulator-max-microvolt = <3300000>;
133 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
134 };
135
136 reg_fec2_3v3: regulator-fec2-3v3 {
137 compatible = "regulator-fixed";
138 regulator-name = "fec2-3v3";
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_enet2_reg>;
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
143 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
144 };
145
146 backlight: backlight {
147 compatible = "pwm-backlight";
148 pwms = <&pwm1 0 5000000 0>;
149 brightness-levels = <0 4 8 16 32 64 128 255>;
150 default-brightness-level = <6>;
151 status = "okay";
152 };
153
154 panel {
155 compatible = "innolux,at043tn24";
156 backlight = <&backlight>;
157 power-supply = <&reg_lcd_3v3>;
158
159 port {
160 panel_in: endpoint {
161 remote-endpoint = <&display_out>;
162 };
163 };
164 };
165
166 sound {
167 compatible = "fsl,imx7d-evk-wm8960",
168 "fsl,imx-audio-wm8960";
169 model = "wm8960-audio";
170 audio-cpu = <&sai1>;
171 audio-codec = <&codec>;
172 hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
173 audio-routing =
174 "Headphone Jack", "HP_L",
175 "Headphone Jack", "HP_R",
176 "Ext Spk", "SPK_LP",
177 "Ext Spk", "SPK_LN",
178 "Ext Spk", "SPK_RP",
179 "Ext Spk", "SPK_RN",
180 "LINPUT1", "AMIC",
181 "AMIC", "MICB";
182 };
183
184 sound-hdmi {
185 compatible = "fsl,imx-audio-sii902x";
186 model = "sii902x-audio";
187 audio-cpu = <&sai3>;
188 hdmi-out;
189 };
190};
191
192&adc1 {
193 vref-supply = <&reg_vref_1v8>;
194 status = "okay";
195};
196
197&adc2 {
198 vref-supply = <&reg_vref_1v8>;
199 status = "okay";
200};
201
202&cpu0 {
203 cpu-supply = <&sw1a_reg>;
204};
205
206&cpu1 {
207 cpu-supply = <&sw1a_reg>;
208};
209
210&ecspi3 {
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_ecspi3>;
213 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
214 status = "okay";
215
216 tsc2046@0 {
217 compatible = "ti,tsc2046";
218 reg = <0>;
219 spi-max-frequency = <1000000>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
222 interrupt-parent = <&gpio2>;
223 interrupts = <29 0>;
224 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
225 touchscreen-max-pressure = <255>;
226 wakeup-source;
227 };
228};
229
230&fec1 {
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_enet1>;
233 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
234 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
235 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
236 assigned-clock-rates = <0>, <100000000>;
237 phy-mode = "rgmii";
238 phy-handle = <&ethphy0>;
239 fsl,magic-packet;
240 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
241 status = "okay";
242
243 mdio {
244 #address-cells = <1>;
245 #size-cells = <0>;
246
247 ethphy0: ethernet-phy@0 {
248 reg = <0>;
249 };
250
251 ethphy1: ethernet-phy@1 {
252 reg = <1>;
253 };
254 };
255};
256
257&fec2 {
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_enet2>;
260 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
261 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
262 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
263 assigned-clock-rates = <0>, <100000000>;
264 phy-mode = "rgmii";
265 phy-handle = <&ethphy1>;
266 phy-supply = <&reg_fec2_3v3>;
267 fsl,magic-packet;
268 status = "okay";
269};
270
271&flexcan2 {
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_flexcan2>;
274 xceiver-supply = <&reg_can2_3v3>;
275 status = "okay";
276};
277
278&i2c1 {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_i2c1>;
281 status = "okay";
282
283 pmic: pmic@8 {
284 compatible = "fsl,pfuze3000";
285 reg = <0x08>;
286
287 regulators {
288 sw1a_reg: sw1a {
289 regulator-min-microvolt = <700000>;
290 regulator-max-microvolt = <1475000>;
291 regulator-boot-on;
292 regulator-always-on;
293 regulator-ramp-delay = <6250>;
294 };
295
296 /* use sw1c_reg to align with pfuze100/pfuze200 */
297 sw1c_reg: sw1b {
298 regulator-min-microvolt = <700000>;
299 regulator-max-microvolt = <1475000>;
300 regulator-boot-on;
301 regulator-always-on;
302 regulator-ramp-delay = <6250>;
303 };
304
305 sw2_reg: sw2 {
306 regulator-min-microvolt = <1800000>;
307 regulator-max-microvolt = <1800000>;
308 regulator-boot-on;
309 regulator-always-on;
310 };
311
312 sw3a_reg: sw3 {
313 regulator-min-microvolt = <900000>;
314 regulator-max-microvolt = <1650000>;
315 regulator-boot-on;
316 regulator-always-on;
317 };
318
319 swbst_reg: swbst {
320 regulator-min-microvolt = <5000000>;
321 regulator-max-microvolt = <5150000>;
322 };
323
324 snvs_reg: vsnvs {
325 regulator-min-microvolt = <1000000>;
326 regulator-max-microvolt = <3000000>;
327 regulator-boot-on;
328 regulator-always-on;
329 };
330
331 vref_reg: vrefddr {
332 regulator-boot-on;
333 regulator-always-on;
334 };
335
336 vgen1_reg: vldo1 {
337 regulator-min-microvolt = <1800000>;
338 regulator-max-microvolt = <3300000>;
339 regulator-always-on;
340 };
341
342 vgen2_reg: vldo2 {
343 regulator-min-microvolt = <800000>;
344 regulator-max-microvolt = <1550000>;
345 };
346
347 vgen3_reg: vccsd {
348 regulator-min-microvolt = <2850000>;
349 regulator-max-microvolt = <3300000>;
350 regulator-always-on;
351 };
352
353 vgen4_reg: v33 {
354 regulator-min-microvolt = <2850000>;
355 regulator-max-microvolt = <3300000>;
356 regulator-always-on;
357 };
358
359 vgen5_reg: vldo3 {
360 regulator-min-microvolt = <1800000>;
361 regulator-max-microvolt = <3300000>;
362 regulator-always-on;
363 };
364
365 vgen6_reg: vldo4 {
366 regulator-min-microvolt = <2800000>;
367 regulator-max-microvolt = <2800000>;
368 regulator-always-on;
369 };
370 };
371 };
372};
373
374&i2c2 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_i2c2>;
377 status = "okay";
378
379 mpl3115@60 {
380 compatible = "fsl,mpl3115";
381 reg = <0x60>;
382 };
383};
384
385&i2c3 {
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_i2c3>;
388 status = "okay";
389};
390
391&i2c4 {
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_i2c4>;
394 status = "okay";
395
396 codec: wm8960@1a {
397 compatible = "wlf,wm8960";
398 reg = <0x1a>;
399 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
400 clock-names = "mclk";
401 wlf,shared-lrclk;
402 wlf,hp-cfg = <2 2 3>;
403 wlf,gpio-cfg = <1 3>;
404 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
405 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
406 <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
407 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
408 assigned-clock-rates = <0>, <884736000>, <12288000>;
409 };
410};
411
412&lcdif {
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_lcdif>;
415 status = "okay";
416
417 port {
418 display_out: endpoint {
419 remote-endpoint = <&panel_in>;
420 };
421 };
422};
423
424&pcie {
425 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
426 status = "okay";
427};
428
429&reg_1p0d {
430 vin-supply = <&sw2_reg>;
431};
432
433&reg_1p2 {
434 vin-supply = <&sw2_reg>;
435};
436
437&sai1 {
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_sai1>;
440 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
441 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
442 <&clks IMX7D_SAI1_ROOT_CLK>;
443 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
444 assigned-clock-rates = <0>, <884736000>, <36864000>;
445 status = "okay";
446};
447
448&sai3 {
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>;
451 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
452 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
453 <&clks IMX7D_SAI3_ROOT_CLK>;
454 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
455 assigned-clock-rates = <0>, <884736000>, <36864000>;
456 status = "okay";
457};
458
459&snvs_pwrkey {
460 status = "okay";
461};
462
463&uart1 {
464 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_uart1>;
466 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
467 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
468 status = "okay";
469};
470
471&uart6 {
472 pinctrl-names = "default";
473 pinctrl-0 = <&pinctrl_uart6>;
474 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
475 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
476 uart-has-rtscts;
477 status = "okay";
478};
479
480&usbotg1 {
481 vbus-supply = <&reg_usb_otg1_vbus>;
482 status = "okay";
483};
484
485&usbotg2 {
486 vbus-supply = <&reg_usb_otg2_vbus>;
487 dr_mode = "host";
488 status = "okay";
489};
490
491&usdhc1 {
492 pinctrl-names = "default", "state_100mhz", "state_200mhz";
493 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
494 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
495 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
496 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
497 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
498 vmmc-supply = <&reg_sd1_vmmc>;
499 wakeup-source;
500 keep-power-in-suspend;
501 status = "okay";
502};
503
504&usdhc2 {
505 pinctrl-names = "default", "state_100mhz", "state_200mhz";
506 pinctrl-0 = <&pinctrl_usdhc2>;
507 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
508 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
509 wakeup-source;
510 keep-power-in-suspend;
511 non-removable;
512 vmmc-supply = <&reg_brcm>;
513 fsl,tuning-step = <2>;
514 status = "okay";
515};
516
517&usdhc3 {
518 pinctrl-names = "default", "state_100mhz", "state_200mhz";
519 pinctrl-0 = <&pinctrl_usdhc3>;
520 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
521 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
522 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
523 assigned-clock-rates = <400000000>;
524 bus-width = <8>;
525 fsl,tuning-step = <2>;
526 non-removable;
527 status = "okay";
528};
529
530&wdog1 {
531 pinctrl-names = "default";
532 pinctrl-0 = <&pinctrl_wdog>;
533 fsl,ext-reset-output;
534};
535
536&iomuxc {
537 pinctrl-names = "default";
538 pinctrl-0 = <&pinctrl_hog>;
539
540 imx7d-sdb {
541 pinctrl_brcm_reg: brcmreggrp {
542 fsl,pins = <
543 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
544 >;
545 };
546
547 pinctrl_ecspi3: ecspi3grp {
548 fsl,pins = <
549 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
550 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
551 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
552 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
553 >;
554 };
555
556 pinctrl_enet1: enet1grp {
557 fsl,pins = <
558 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
559 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
560 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
561 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
562 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
563 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
564 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
565 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
566 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
567 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
568 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
569 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
570 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
571 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
572 >;
573 };
574
575 pinctrl_enet2: enet2grp {
576 fsl,pins = <
577 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
578 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
579 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
580 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
581 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
582 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
583 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
584 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
585 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
586 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
587 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
588 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
589 >;
590 };
591
592 pinctrl_enet2_reg: enet2reggrp {
593 fsl,pins = <
594 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14
595 >;
596 };
597
598 pinctrl_flexcan2: flexcan2grp {
599 fsl,pins = <
600 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
601 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
602 >;
603 };
604
605 pinctrl_flexcan2_reg: flexcan2reggrp {
606 fsl,pins = <
607 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
608 >;
609 };
610
611 pinctrl_gpio_keys: gpio_keysgrp {
612 fsl,pins = <
613 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59
614 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59
615 >;
616 };
617
618 pinctrl_hog: hoggrp {
619 fsl,pins = <
620 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
621 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */
622 >;
623 };
624
625 pinctrl_i2c1: i2c1grp {
626 fsl,pins = <
627 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
628 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
629 >;
630 };
631
632 pinctrl_i2c2: i2c2grp {
633 fsl,pins = <
634 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
635 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
636 >;
637 };
638
639 pinctrl_i2c3: i2c3grp {
640 fsl,pins = <
641 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
642 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
643 >;
644 };
645
646 pinctrl_i2c4: i2c4grp {
647 fsl,pins = <
648 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
649 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
650 >;
651 };
652
653 pinctrl_lcdif: lcdifgrp {
654 fsl,pins = <
655 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
656 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
657 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
658 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
659 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
660 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
661 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
662 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
663 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
664 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
665 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
666 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
667 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
668 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
669 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
670 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
671 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
672 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
673 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
674 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
675 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
676 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
677 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
678 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
679 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
680 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
681 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
682 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
683 MX7D_PAD_LCD_RESET__LCD_RESET 0x79
684 >;
685 };
686
687 pinctrl_sai1: sai1grp {
688 fsl,pins = <
689 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
690 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
691 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
692 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
693 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
694 >;
695 };
696
697 pinctrl_sai2: sai2grp {
698 fsl,pins = <
699 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
700 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
701 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
702 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f
703 >;
704 };
705
706 pinctrl_sai3: sai3grp {
707 fsl,pins = <
708 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f
709 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f
710 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30
711 >;
712 };
713
714 pinctrl_spi4: spi4grp {
715 fsl,pins = <
716 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
717 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
718 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
719 >;
720 };
721
722 pinctrl_tsc2046_pendown: tsc2046_pendown {
723 fsl,pins = <
724 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
725 >;
726 };
727
728 pinctrl_uart1: uart1grp {
729 fsl,pins = <
730 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
731 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
732 >;
733 };
734
735 pinctrl_uart5: uart5grp {
736 fsl,pins = <
737 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
738 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
739 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
740 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
741 >;
742 };
743
744 pinctrl_uart6: uart6grp {
745 fsl,pins = <
746 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
747 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
748 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
749 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
750 >;
751 };
752
753 pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
754 fsl,pins = <
755 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
756 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
757 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
758 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
759 >;
760 };
761
762 pinctrl_usdhc1: usdhc1grp {
763 fsl,pins = <
764 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
765 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
766 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
767 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
768 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
769 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
770 >;
771 };
772
773 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
774 fsl,pins = <
775 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
776 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
777 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
778 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
779 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
780 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
781 >;
782 };
783
784 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
785 fsl,pins = <
786 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
787 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
788 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
789 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
790 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
791 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
792 >;
793 };
794
795 pinctrl_usdhc2: usdhc2grp {
796 fsl,pins = <
797 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
798 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
799 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
800 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
801 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
802 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
803 >;
804 };
805
806 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
807 fsl,pins = <
808 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
809 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
810 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
811 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
812 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
813 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
814 >;
815 };
816
817 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
818 fsl,pins = <
819 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
820 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
821 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
822 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
823 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
824 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
825 >;
826 };
827
828
829 pinctrl_usdhc3: usdhc3grp {
830 fsl,pins = <
831 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
832 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
833 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
834 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
835 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
836 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
837 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
838 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
839 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
840 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
841 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
842 >;
843 };
844
845 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
846 fsl,pins = <
847 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
848 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
849 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
850 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
851 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
852 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
853 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
854 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
855 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
856 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
857 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
858 >;
859 };
860
861 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
862 fsl,pins = <
863 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
864 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
865 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
866 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
867 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
868 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
869 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
870 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
871 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
872 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
873 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
874 >;
875 };
876 };
877};
878
879&pwm1 {
880 pinctrl-names = "default";
881 pinctrl-0 = <&pinctrl_pwm1>;
882 status = "okay";
883};
884
885&iomuxc_lpsr {
886 pinctrl_wdog: wdoggrp {
887 fsl,pins = <
888 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
889 >;
890 };
891
892 pinctrl_pwm1: pwm1grp {
893 fsl,pins = <
894 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
895 >;
896 };
897
898 pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
899 fsl,pins = <
900 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
901 >;
902 };
903
904 pinctrl_sai3_mclk: sai3grp_mclk {
905 fsl,pins = <
906 MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f
907 >;
908 };
909};