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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx6ull-phytec-tauri.dtsi
blob: d12fb44aeb140cfacf05a5b257d2106c79392279 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2021 PHYTEC Messtechnik GmbH
4 * Author: Alexander Bauer <a.bauer@phytec.de>
5 */
6
7/dts-v1/;
8#include "imx6ull.dtsi"
9#include "imx6ull-phytec-phycore-som.dtsi"
10
11/ {
12 aliases {
13 rtc0 = &i2c_rtc;
14 rtc1 = &snvs_rtc;
15 };
16
17 gpio_keys: gpio-keys {
18 compatible = "gpio-key";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_keys>;
21
22 key {
23 label = "KEY-A";
24 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
25 linux,code = <KEY_A>;
26 wakeup-source;
27 };
28 };
29
30 reg_adc1_vref_3v3: regulator-vref-3v3 {
31 compatible = "regulator-fixed";
32 regulator-name = "vref-3v3";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 };
36
37 reg_s25fl064_hold: regulator-s25fl064-hold {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_s25fl064_hold>;
40 compatible = "regulator-fixed";
41 regulator-name = "s25fl064_hold";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>;
45 enable-active-high;
46 regulator-always-on;
47 };
48
49 reg_usb_hub_vbus: regulator-hub-otg1-vbus {
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_usbhubpwr>;
52 compatible = "regulator-fixed";
53 regulator-name = "usb_hub_vbus";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
57 enable-active-high;
58 regulator-always-on;
59 };
60
61 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_usbotg1pwr>;
64 compatible = "regulator-fixed";
65 regulator-name = "usb_otg1_vbus";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
68 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
69 enable-active-high;
70 regulator-always-on;
71 };
72
73 user_leds: user-leds {
74 compatible = "gpio-leds";
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_user_leds>,
77 <&pinctrl_user_leds_snvs>;
78
79 user-led1 {
80 label = "yellow";
81 gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
82 linux,default-trigger = "off";
83 };
84
85 user-led2 {
86 label = "red";
87 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
88 linux,default-trigger = "off";
89 };
90 };
91};
92
93&can1 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_flexcan1>;
96 status = "okay";
97};
98
99&can2 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_flexcan2>;
102 status = "okay";
103};
104
105&ecspi1 {
106 #address-cells = <1>;
107 #size-cells = <0>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_ecspi1>,
110 <&pinctrl_ecspi1_cs>;
111 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>,
112 <&gpio3 10 GPIO_ACTIVE_LOW>,
113 <&gpio3 11 GPIO_ACTIVE_LOW>;
114 status = "okay";
115
116 tpm_tis: tpm@1 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_tpm>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]119 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]120 reg = <1>;
121 spi-max-frequency = <20000000>;
122 interrupt-parent = <&gpio5>;
123 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
124 };
125
126 s25fl064: flash@2 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = " jedec,spi-nor";
130 reg = <2>;
131 spi-max-frequency = <40000000>;
132 m25p,fast-read;
133 status = "disabled";
134 };
135};
136
137&ecspi3 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_ecspi3>;
140 cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
141 dmas = <&sdma 7 8 0>,
142 <&sdma 8 8 0>;
143 dma-names = "rx", "tx";
144 status = "okay";
145};
146
147&ethphy1 {
148 status = "okay";
149};
150
151&fec1 {
152 status = "okay";
153};
154
155&fec2 {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_enet2>;
158 phy-mode = "rmii";
159 phy-handle = <&ethphy2>;
160 status = "okay";
161};
162
163&i2c1 {
164 status = "okay";
165
166 tmp102: tmp@49 {
167 compatible = "ti,tmp102";
168 reg = <0x49>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_tempsense>;
171 interrupt-parent = <&gpio5>;
172 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
173 #thermal-sensor-cells = <1>;
174 };
175
176 i2c_rtc: rtc@68 {
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_rtc_int>;
179 compatible = "microcrystal,rv4162";
180 reg = <0x68>;
181 interrupt-parent = <&gpio5>;
182 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
183 };
184};
185
186&i2c2 {
187 pinctrl-names = "default", "gpio";
188 pinctrl-0 = <&pinctrl_i2c2>;
189 pinctrl-1 = <&pinctrl_i2c2_gpio>;
190 sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
191 scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
192 status = "okay";
193};
194
195&i2c3 {
196 pinctrl-names = "default", "gpio";
197 pinctrl-0 = <&pinctrl_i2c3>;
198 pinctrl-1 = <&pinctrl_i2c3_gpio>;
199 sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
200 scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
201 status = "okay";
202};
203
204&i2c4 {
205 pinctrl-names = "default", "gpio";
206 pinctrl-0 = <&pinctrl_i2c4>;
207 pinctrl-1 = <&pinctrl_i2c4_gpio>;
208 sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
209 scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
210 status = "okay";
211};
212
213&mdio {
214 ethphy2: ethernet-phy@2 {
215 reg = <2>;
216 micrel,led-mode = <1>;
217 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
218 clock-names = "rmii-ref";
219 status = "okay";
220 };
221};
222
223&pwm3 {
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_pwm3>;
226 status = "okay";
227};
228
229&pwm6 {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_pwm6>;
232 status = "okay";
233};
234
235&pwm7 {
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_pwm7>;
238 status = "okay";
239};
240
241&pwm8 {
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_pwm8>;
244 status = "okay";
245};
246
247&uart3 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_uart3>;
250 status = "okay";
251};
252
253/* UART4 * RS485 */
254&uart4 {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_uart4>;
257 rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
258 linux,rs485-enabled-at-boot-time;
259 status = "okay";
260};
261
262/* UART5 * RS232 */
263&uart5 {
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_uart5>;
266 uart-has-rtscts;
267 status = "okay";
268};
269
270&uart7 {
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_uart7>;
273 status = "okay";
274};
275
276/* USB */
277&usbotg1 {
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_usb_otg1>;
280 vbus-supply = <&reg_usb_otg1_vbus>;
281 dr_mode = "host";
282 disable-over-current;
283 status = "okay";
284};
285
286&usbotg2 {
287 vbus-supply = <&reg_usb_hub_vbus>;
288 disable-over-current;
289 dr_mode = "host";
290 status = "okay";
291};
292
293&usdhc1 {
294 pinctrl-names = "default", "state_100mhz", "state_200mhz";
295 pinctrl-0 = <&pinctrl_usdhc1>;
296 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
297 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
298 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
299 no-1-8-v;
300 keep-power-in-suspend;
301 wakeup-source;
302 status = "okay";
303};
304
305&usdhc2 {
306 status = "disabled";
307};
308
309&iomuxc_snvs {
310 pinctrl_rtc_int: rtcintgrp {
311 fsl,pins = <
312 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
313 >;
314 };
315
316 pinctrl_stmpe: stmpegrp {
317 fsl,pins = <
318 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
319 >;
320 };
321
322 pinctrl_tempsense: tempsensegrp {
323 fsl,pins = <
324 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
325 >;
326 };
327
328 pinctrl_tpm: tpmgrp {
329 fsl,pins = <
330 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
331 >;
332 };
333
334 pinctrl_usbhubpwr: usbhubpwrgrp {
335 fsl,pins = <
336 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059
337 >;
338 };
339
340 pinctrl_user_leds_snvs: user_ledsgrp {
341 fsl,pins = <
342 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
343 >;
344 };
345};
346
347&iomuxc {
348 pinctrl_gpio: gpiogrp {
349 fsl,pins = <
350 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */
351 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */
352 >;
353 };
354
355 pinctrl_gpio_keys: gpiokeysgrp {
356 fsl,pins = <
357 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79
358 >;
359 };
360
361 pinctrl_ecspi3: ecspi3grp {
362 fsl,pins = <
363 MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1
364 MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1
365 MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1
366 MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
367 >;
368 };
369
370 pinctrl_ecspi1: ecspi1grp {
371 fsl,pins = <
372 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1
373 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1
374 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1
375 >;
376 };
377
378 pinctrl_ecspi1_cs: ecspi1csgrp {
379 fsl,pins = <
380 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0
381 MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0
382 MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0
383 >;
384 };
385
386
387 pinctrl_enet2: enet2grp {
388 fsl,pins = <
389 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
390 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
391 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
392 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
393 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
394 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
395 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
396 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
397 >;
398 };
399
400 pinctrl_flexcan1: flexcan1grp {
401 fsl,pins = <
402 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
403 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
404 >;
405 };
406
407 pinctrl_flexcan2: flexcan2grp {
408 fsl,pins = <
409 MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0
410 MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0
411 >;
412 };
413
414 princtrl_flexcan2_en: flexcan2engrp {
415 fsl,pins = <
416 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059
417 >;
418 };
419
420 pinctrl_i2c2: i2c2grp {
421 fsl,pins = <
422 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0
423 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0
424 >;
425 };
426
427 pinctrl_i2c2_gpio: i2c2gpiogrp {
428 fsl,pins = <
429 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
430 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
431 >;
432 };
433
434 pinctrl_i2c3: i2c3grp {
435 fsl,pins = <
436 MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0
437 MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0
438 >;
439 };
440
441 pinctrl_i2c3_gpio: i2c3gpiogrp {
442 fsl,pins = <
443 MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0
444 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0
445 >;
446 };
447
448 pinctrl_i2c4: i2c4grp {
449 fsl,pins = <
450 MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0
451 MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0
452 >;
453 };
454
455 pinctrl_i2c4_gpio: i2c4gpiogrp {
456 fsl,pins = <
457 MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0
458 MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0
459 >;
460 };
461
462 pinctrl_pwm3: pwm3grp {
463 fsl,pins = <
464 MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0
465 >;
466 };
467
468 pinctrl_pwm6: pwm6grp {
469 fsl,pins = <
470 MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0
471 >;
472 };
473
474 pinctrl_pwm7: pwm7grp {
475 fsl,pins = <
476 MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0
477 >;
478 };
479
480 pinctrl_pwm8: pwm8grp {
481 fsl,pins = <
482 MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0
483 >;
484 };
485
486 pinctrl_s25fl064_hold: s25fl064holdgrp {
487 fsl,pins = <
488 MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1
489 >;
490 };
491
492 pinctrl_sai2: sai2grp {
493 fsl,pins = <
494 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
495 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
496 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
497 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
498 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
499 >;
500 };
501
502 pinctrl_uart3: uart3grp {
503 fsl,pins = <
504 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
505 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
506 >;
507 };
508
509 pinctrl_uart4: uart4grp {
510 fsl,pins = <
511 MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1
512 MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1
513 MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1
514 >;
515 };
516
517 pinctrl_uart5: uart5grp {
518 fsl,pins = <
519 MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
520 MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
521 >;
522 };
523
524 pinctrl_uart7: uart7grp {
525 fsl,pins = <
526 MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1
527 MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1
528 >;
529 };
530
531 pinctrl_usb_otg1: usbotg1grp {
532 fsl,pins = <
533 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80
534 >;
535 };
536
537 pinctrl_usbotg1pwr: usbotg1pwrgrp {
538 fsl,pins = <
539 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059
540 >;
541 };
542
543 pinctrl_usdhc1: usdhc1grp {
544 fsl,pins = <
545 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
546 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
547 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
548 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
549 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
550 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
551 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
552 >;
553 };
554
555 pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
556 fsl,pins = <
557 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
558 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
559 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
560 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
561 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
562 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
563 >;
564 };
565
566 pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
567 fsl,pins = <
568 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
569 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
570 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
571 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
572 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
573 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
574 >;
575 };
576
577 pinctrl_user_leds: userledsgrp {
578 fsl,pins = <
579 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79
580 >;
581 };
582};