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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx6ul-pico.dtsi
blob: fe307f49b9e56794f538486a90cc0af6cfe3bd5e [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Copyright 2015 Technexion Ltd.
4//
5// Author: Wig Cheng <wig.cheng@technexion.com>
6// Richard Hu <richard.hu@technexion.com>
7// Tapani Utriainen <tapani@technexion.com>
8/dts-v1/;
9
10#include "imx6ul.dtsi"
11
12/ {
13 /* Will be filled by the bootloader */
14 memory@80000000 {
15 device_type = "memory";
16 reg = <0x80000000 0>;
17 };
18
19 chosen {
20 stdout-path = &uart6;
21 };
22
23 backlight: backlight {
24 compatible = "pwm-backlight";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame^]25 pwms = <&pwm3 0 5000000 0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <6>;
28 status = "okay";
29 };
30
31 reg_2p5v: regulator-2p5v {
32 compatible = "regulator-fixed";
33 regulator-name = "2P5V";
34 regulator-min-microvolt = <2500000>;
35 regulator-max-microvolt = <2500000>;
36 };
37
38 reg_3p3v: regulator-3p3v {
39 compatible = "regulator-fixed";
40 regulator-name = "3P3V";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 };
44
45 reg_sd1_vmmc: regulator-sd1-vmmc {
46 compatible = "regulator-fixed";
47 regulator-name = "VSD_3V3";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
51 enable-active-high;
52 };
53
54 reg_usb_otg_vbus: regulator-usb-otg-vbus {
55 compatible = "regulator-fixed";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_usb_otg1>;
58 regulator-name = "usb_otg_vbus";
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
61 gpio = <&gpio1 6 0>;
62 };
63
64 reg_brcm: regulator-brcm {
65 compatible = "regulator-fixed";
66 enable-active-high;
67 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_brcm_reg>;
70 regulator-name = "brcm_reg";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 startup-delay-us = <200000>;
74 };
75
76 panel {
77 compatible = "vxt,vl050-8048nt-c01";
78 backlight = <&backlight>;
79
80 port {
81 panel_in: endpoint {
82 remote-endpoint = <&display_out>;
83 };
84 };
85 };
86};
87
88&can1 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_flexcan1>;
91 status = "okay";
92};
93
94&can2 {
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_flexcan2>;
97 status = "okay";
98};
99
100&clks {
101 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
102 assigned-clock-rates = <786432000>;
103};
104
105&fec2 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_enet2>;
108 phy-mode = "rmii";
109 phy-handle = <&ethphy1>;
110 status = "okay";
111 phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
112 phy-reset-duration = <1>;
113
114 mdio {
115 #address-cells = <1>;
116 #size-cells = <0>;
117
118 ethphy1: ethernet-phy@1 {
119 compatible = "ethernet-phy-ieee802.3-c22";
120 reg = <1>;
121 max-speed = <100>;
122 interrupt-parent = <&gpio5>;
123 interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
124 clocks = <&clks IMX6UL_CLK_ENET_REF>;
125 clock-names = "rmii-ref";
126 };
127 };
128};
129
130&i2c1 {
131 clock-frequency = <100000>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_i2c1>;
134 status = "okay";
135
136 pmic: pmic@8 {
137 compatible = "fsl,pfuze3000";
138 reg = <0x08>;
139
140 regulators {
141 /* VDD_ARM_SOC_IN*/
142 sw1b_reg: sw1b {
143 regulator-min-microvolt = <700000>;
144 regulator-max-microvolt = <1475000>;
145 regulator-boot-on;
146 regulator-always-on;
147 regulator-ramp-delay = <6250>;
148 };
149
150 /* DRAM */
151 sw3a_reg: sw3 {
152 regulator-min-microvolt = <900000>;
153 regulator-max-microvolt = <1650000>;
154 regulator-boot-on;
155 regulator-always-on;
156 };
157
158 /* DRAM */
159 vref_reg: vrefddr {
160 regulator-boot-on;
161 regulator-always-on;
162 };
163 };
164 };
165};
166
167&lcdif {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
170 status = "okay";
171
172 port {
173 display_out: endpoint {
174 remote-endpoint = <&panel_in>;
175 };
176 };
177};
178
179&pwm3 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_pwm3>;
182 status = "okay";
183};
184
185&pwm7 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_pwm7>;
188 status = "okay";
189};
190
191&pwm8 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_pwm8>;
194 status = "okay";
195};
196
197&sai1 {
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_sai1>;
200 status = "okay";
201};
202
203&uart3 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_uart3>;
206 uart-has-rtscts;
207 status = "okay";
208};
209
210&uart6 {
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_uart6>;
213 status = "okay";
214};
215
216&usbotg1 {
217 vbus-supply = <&reg_usb_otg_vbus>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_usb_otg1_id>;
220 dr_mode = "otg";
221 disable-over-current;
222 status = "okay";
223};
224
225&usbotg2 {
226 dr_mode = "host";
227 disable-over-current;
228 status = "okay";
229};
230
231&usdhc1 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_usdhc1>;
234 bus-width = <8>;
235 no-1-8-v;
236 non-removable;
237 keep-power-in-suspend;
238 status = "okay";
239};
240
241&usdhc2 { /* Wifi SDIO */
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_usdhc2>;
244 no-1-8-v;
245 non-removable;
246 keep-power-in-suspend;
247 wakeup-source;
248 vmmc-supply = <&reg_brcm>;
249 status = "okay";
250};
251
252&wdog1 {
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_wdog>;
255 fsl,ext-reset-output;
256};
257
258&iomuxc {
259 pinctrl_brcm_reg: brcmreggrp {
260 fsl,pins = <
261 MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */
262 MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */
263 >;
264 };
265
266 pinctrl_enet2: enet2grp {
267 fsl,pins = <
268 MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
269 MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
270 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
271 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
272 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
273 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
274 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
275 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
276 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
277 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
278 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
279 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
280 >;
281 };
282
283 pinctrl_flexcan1: flexcan1grp {
284 fsl,pins = <
285 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
286 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
287 >;
288 };
289
290 pinctrl_flexcan2: flexcan2grp {
291 fsl,pins = <
292 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
293 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
294 >;
295 };
296
297 pinctrl_i2c1: i2c1grp {
298 fsl,pins = <
299 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
300 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
301 >;
302 };
303
304 pinctrl_i2c2: i2c2grp {
305 fsl,pins = <
306 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
307 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
308 >;
309 };
310
311 pinctrl_i2c3: i2c3grp {
312 fsl,pins = <
313 MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
314 MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
315 >;
316 };
317
318 pinctrl_lcdif_dat: lcdifdatgrp {
319 fsl,pins = <
320 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
321 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
322 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
323 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
324 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
325 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
326 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
327 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
328 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
329 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
330 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
331 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
332 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
333 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
334 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
335 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
336 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
337 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
338 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
339 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
340 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
341 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
342 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
343 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
344 >;
345 };
346
347 pinctrl_lcdif_ctrl: lcdifctrlgrp {
348 fsl,pins = <
349 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
350 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
351 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
352 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
353 /* LCD reset */
354 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
355 >;
356 };
357
358 pinctrl_pwm3: pwm3grp {
359 fsl,pins = <
360 MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
361 >;
362 };
363
364 pinctrl_pwm7: pwm7grp {
365 fsl,pins = <
366 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
367 >;
368 };
369
370 pinctrl_pwm8: pwm8grp {
371 fsl,pins = <
372 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
373 >;
374 };
375
376 pinctrl_sai1: sai1grp {
377 fsl,pins = <
378 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
379 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
380 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
381 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
382 >;
383 };
384
385 pinctrl_uart3: uart3grp {
386 fsl,pins = <
387 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
388 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
389 MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
390 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
391 >;
392 };
393
394 pinctrl_uart5: uart5grp {
395 fsl,pins = <
396 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
397 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
398 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
399 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
400 >;
401 };
402
403 pinctrl_uart6: uart6grp {
404 fsl,pins = <
405 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
406 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
407 >;
408 };
409
410 pinctrl_usb_otg1: usbotg1grp {
411 fsl,pins = <
412 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
413 >;
414 };
415
416 pinctrl_usb_otg1_id: usbotg1idgrp {
417 fsl,pins = <
418 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
419 >;
420 };
421
422 pinctrl_usdhc1: usdhc1grp {
423 fsl,pins = <
424 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
425 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
426 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
427 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
428 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
429 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
430 MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
431 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
432 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
433 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
434 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
435 >;
436 };
437
438 pinctrl_usdhc2: usdhc2grp {
439 fsl,pins = <
440 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
441 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
442 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
443 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
444 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
445 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
446 >;
447 };
448
449 pinctrl_wdog: wdoggrp {
450 fsl,pins = <
451 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
452 >;
453 };
454};