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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx6ul-14x14-evk.dtsi
blob: 9cfb99ac9e9daaf5fe7479aee9dc8888909e4bdc [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (C) 2015 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/media/video-interfaces.h>
6
7/ {
8 chosen {
9 stdout-path = &uart1;
10 };
11
12 memory@80000000 {
13 device_type = "memory";
14 reg = <0x80000000 0x20000000>;
15 };
16
17 backlight_display: backlight-display {
18 compatible = "pwm-backlight";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame^]19 pwms = <&pwm1 0 5000000 0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]20 brightness-levels = <0 4 8 16 32 64 128 255>;
21 default-brightness-level = <6>;
22 status = "okay";
23 };
24
25
26 reg_sd1_vmmc: regulator-sd1-vmmc {
27 compatible = "regulator-fixed";
28 regulator-name = "VSD_3V3";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
32 enable-active-high;
33 };
34
35 reg_peri_3v3: regulator-peri-3v3 {
36 compatible = "regulator-fixed";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_peri_3v3>;
39 regulator-name = "VPERI_3V3";
40 regulator-min-microvolt = <3300000>;
41 regulator-max-microvolt = <3300000>;
42 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
43 /*
44 * If you want to want to make this dynamic please
45 * check schematics and test all affected peripherals:
46 *
47 * - sensors
48 * - ethernet phy
49 * - can
50 * - bluetooth
51 * - wm8960 audio codec
52 * - ov5640 camera
53 */
54 regulator-always-on;
55 };
56
57 reg_can_3v3: regulator-can-3v3 {
58 compatible = "regulator-fixed";
59 regulator-name = "can-3v3";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
62 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
63 };
64
65 sound-wm8960 {
66 compatible = "fsl,imx-audio-wm8960";
67 model = "wm8960-audio";
68 audio-cpu = <&sai2>;
69 audio-codec = <&codec>;
70 audio-asrc = <&asrc>;
71 hp-det-gpio = <&gpio5 4 0>;
72 audio-routing =
73 "Headphone Jack", "HP_L",
74 "Headphone Jack", "HP_R",
75 "Ext Spk", "SPK_LP",
76 "Ext Spk", "SPK_LN",
77 "Ext Spk", "SPK_RP",
78 "Ext Spk", "SPK_RN",
79 "LINPUT2", "Mic Jack",
80 "LINPUT3", "Mic Jack",
81 "RINPUT1", "AMIC",
82 "RINPUT2", "AMIC",
83 "Mic Jack", "MICB",
84 "AMIC", "MICB";
85 };
86
87 spi-4 {
88 compatible = "spi-gpio";
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_spi4>;
91 status = "okay";
92 sck-gpios = <&gpio5 11 0>;
93 mosi-gpios = <&gpio5 10 0>;
94 cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
95 num-chipselects = <1>;
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 gpio_spi: gpio@0 {
100 compatible = "fairchild,74hc595";
101 gpio-controller;
102 #gpio-cells = <2>;
103 reg = <0>;
104 registers-number = <1>;
105 spi-max-frequency = <100000>;
106 enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
107 };
108 };
109
110 panel {
111 compatible = "innolux,at043tn24";
112 backlight = <&backlight_display>;
113
114 port {
115 panel_in: endpoint {
116 remote-endpoint = <&display_out>;
117 };
118 };
119 };
120};
121
122&clks {
123 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
124 assigned-clock-rates = <786432000>;
125};
126
127&i2c2 {
128 clock-frequency = <100000>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_i2c2>;
131 status = "okay";
132
133 codec: wm8960@1a {
134 #sound-dai-cells = <0>;
135 compatible = "wlf,wm8960";
136 reg = <0x1a>;
137 wlf,shared-lrclk;
138 wlf,hp-cfg = <3 2 3>;
139 wlf,gpio-cfg = <1 3>;
140 clocks = <&clks IMX6UL_CLK_SAI2>;
141 clock-names = "mclk";
142 };
143
144 camera@3c {
145 compatible = "ovti,ov5640";
146 reg = <0x3c>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_camera_clock>;
149 clocks = <&clks IMX6UL_CLK_CSI>;
150 clock-names = "xclk";
151 powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
152 reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>;
153
154 port {
155 ov5640_to_parallel: endpoint {
156 remote-endpoint = <&parallel_from_ov5640>;
157 bus-width = <8>;
158 data-shift = <2>; /* lines 9:2 are used */
159 hsync-active = <0>;
160 vsync-active = <0>;
161 pclk-sample = <1>;
162 };
163 };
164 };
165};
166
167&csi {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_csi1>;
170 status = "okay";
171
172 port {
173 parallel_from_ov5640: endpoint {
174 remote-endpoint = <&ov5640_to_parallel>;
175 bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
176 };
177 };
178};
179
180&fec1 {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_enet1>;
183 phy-mode = "rmii";
184 phy-handle = <&ethphy0>;
185 phy-supply = <&reg_peri_3v3>;
186 status = "okay";
187};
188
189&fec2 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_enet2>;
192 phy-mode = "rmii";
193 phy-handle = <&ethphy1>;
194 phy-supply = <&reg_peri_3v3>;
195 status = "okay";
196
197 mdio {
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 ethphy0: ethernet-phy@2 {
202 compatible = "ethernet-phy-id0022.1560";
203 reg = <2>;
204 micrel,led-mode = <1>;
205 clocks = <&clks IMX6UL_CLK_ENET_REF>;
206 clock-names = "rmii-ref";
207
208 };
209
210 ethphy1: ethernet-phy@1 {
211 compatible = "ethernet-phy-id0022.1560";
212 reg = <1>;
213 micrel,led-mode = <1>;
214 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
215 clock-names = "rmii-ref";
216 };
217 };
218};
219
220&can1 {
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_flexcan1>;
223 xceiver-supply = <&reg_can_3v3>;
224 status = "okay";
225};
226
227&can2 {
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_flexcan2>;
230 xceiver-supply = <&reg_can_3v3>;
231 status = "okay";
232};
233
234&gpio_spi {
235 eth0-phy-hog {
236 gpio-hog;
237 gpios = <1 GPIO_ACTIVE_HIGH>;
238 output-high;
239 line-name = "eth0-phy";
240 };
241
242 eth1-phy-hog {
243 gpio-hog;
244 gpios = <2 GPIO_ACTIVE_HIGH>;
245 output-high;
246 line-name = "eth1-phy";
247 };
248};
249
250&i2c1 {
251 clock-frequency = <100000>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_i2c1>;
254 status = "okay";
255
256 magnetometer@e {
257 compatible = "fsl,mag3110";
258 reg = <0x0e>;
259 vdd-supply = <&reg_peri_3v3>;
260 vddio-supply = <&reg_peri_3v3>;
261 };
262};
263
264&lcdif {
265 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
266 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_lcdif_dat
269 &pinctrl_lcdif_ctrl>;
270 status = "okay";
271
272 port {
273 display_out: endpoint {
274 remote-endpoint = <&panel_in>;
275 };
276 };
277};
278
279&pwm1 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_pwm1>;
282 status = "okay";
283};
284
285&qspi {
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_qspi>;
288 status = "okay";
289
290 flash0: flash@0 {
291 #address-cells = <1>;
292 #size-cells = <1>;
293 compatible = "micron,n25q256a", "jedec,spi-nor";
294 spi-max-frequency = <29000000>;
295 spi-rx-bus-width = <4>;
296 spi-tx-bus-width = <1>;
297 reg = <0>;
298 };
299};
300
301&sai2 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_sai2>;
304 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
305 <&clks IMX6UL_CLK_SAI2>;
306 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
307 assigned-clock-rates = <0>, <12288000>;
308 fsl,sai-mclk-direction-output;
309 status = "okay";
310};
311
312&snvs_poweroff {
313 status = "okay";
314};
315
316&snvs_pwrkey {
317 status = "okay";
318};
319
320&tsc {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_tsc>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]323 xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]324 measure-delay-time = <0xffff>;
325 pre-charge-time = <0xfff>;
326 status = "okay";
327};
328
329&uart1 {
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_uart1>;
332 status = "okay";
333};
334
335&uart2 {
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_uart2>;
338 uart-has-rtscts;
339 status = "okay";
340};
341
342&usbotg1 {
343 dr_mode = "otg";
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_usb_otg1>;
346 status = "okay";
347};
348
349&usbotg2 {
350 dr_mode = "host";
351 disable-over-current;
352 status = "okay";
353};
354
355&usbphy1 {
356 fsl,tx-d-cal = <106>;
357};
358
359&usbphy2 {
360 fsl,tx-d-cal = <106>;
361};
362
363&usdhc1 {
364 pinctrl-names = "default", "state_100mhz", "state_200mhz";
365 pinctrl-0 = <&pinctrl_usdhc1>;
366 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
367 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
368 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
369 keep-power-in-suspend;
370 wakeup-source;
371 vmmc-supply = <&reg_sd1_vmmc>;
372 status = "okay";
373};
374
375&usdhc2 {
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_usdhc2>;
378 no-1-8-v;
379 broken-cd;
380 keep-power-in-suspend;
381 wakeup-source;
382 status = "okay";
383};
384
385&wdog1 {
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_wdog>;
388 fsl,ext-reset-output;
389};
390
391&iomuxc {
392 pinctrl-names = "default";
393
394 pinctrl_camera_clock: cameraclockgrp {
395 fsl,pins = <
396 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
397 >;
398 };
399
400 pinctrl_csi1: csi1grp {
401 fsl,pins = <
402 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
403 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
404 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
405 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
406 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
407 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
408 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
409 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
410 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
411 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
412 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
413 >;
414 };
415
416 pinctrl_enet1: enet1grp {
417 fsl,pins = <
418 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
419 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
420 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
421 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
422 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
423 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
424 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
425 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
426 >;
427 };
428
429 pinctrl_enet2: enet2grp {
430 fsl,pins = <
431 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
432 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
433 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
434 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
435 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
436 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
437 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
438 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
439 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
440 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
441 >;
442 };
443
444 pinctrl_flexcan1: flexcan1grp {
445 fsl,pins = <
446 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
447 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
448 >;
449 };
450
451 pinctrl_flexcan2: flexcan2grp {
452 fsl,pins = <
453 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
454 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
455 >;
456 };
457
458 pinctrl_i2c1: i2c1grp {
459 fsl,pins = <
460 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
461 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
462 >;
463 };
464
465 pinctrl_i2c2: i2c2grp {
466 fsl,pins = <
467 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
468 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
469 >;
470 };
471
472 pinctrl_lcdif_dat: lcdifdatgrp {
473 fsl,pins = <
474 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
475 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
476 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
477 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
478 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
479 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
480 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
481 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
482 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
483 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
484 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
485 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
486 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
487 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
488 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
489 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
490 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
491 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
492 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
493 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
494 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
495 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
496 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
497 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
498 >;
499 };
500
501 pinctrl_lcdif_ctrl: lcdifctrlgrp {
502 fsl,pins = <
503 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
504 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
505 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
506 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
507 /* used for lcd reset */
508 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
509 >;
510 };
511
512 pinctrl_qspi: qspigrp {
513 fsl,pins = <
514 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
515 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
516 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
517 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
518 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
519 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
520 >;
521 };
522
523 pinctrl_sai2: sai2grp {
524 fsl,pins = <
525 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
526 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
527 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
528 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
529 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
530 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
531 >;
532 };
533
534 pinctrl_peri_3v3: peri3v3grp {
535 fsl,pins = <
536 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
537 >;
538 };
539
540 pinctrl_pwm1: pwm1grp {
541 fsl,pins = <
542 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
543 >;
544 };
545
546 pinctrl_sim2: sim2grp {
547 fsl,pins = <
548 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
549 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
550 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
551 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
552 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
553 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
554 >;
555 };
556
557 pinctrl_spi4: spi4grp {
558 fsl,pins = <
559 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
560 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
561 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
562 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
563 >;
564 };
565
566 pinctrl_tsc: tscgrp {
567 fsl,pins = <
568 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
569 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
570 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
571 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
572 >;
573 };
574
575 pinctrl_uart1: uart1grp {
576 fsl,pins = <
577 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
578 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
579 >;
580 };
581
582 pinctrl_uart2: uart2grp {
583 fsl,pins = <
584 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
585 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
586 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
587 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
588 >;
589 };
590
591 pinctrl_usb_otg1: usbotg1grp {
592 fsl,pins = <
593 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
594 >;
595 };
596
597 pinctrl_usdhc1: usdhc1grp {
598 fsl,pins = <
599 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
600 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
601 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
602 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
603 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
604 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
605 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
606 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
607 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
608 >;
609 };
610
611 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
612 fsl,pins = <
613 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
614 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
615 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
616 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
617 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
618 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
619
620 >;
621 };
622
623 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
624 fsl,pins = <
625 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
626 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
627 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
628 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
629 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
630 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
631 >;
632 };
633
634 pinctrl_usdhc2: usdhc2grp {
635 fsl,pins = <
636 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
637 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
638 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
639 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
640 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
641 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
642 >;
643 };
644
645 pinctrl_wdog: wdoggrp {
646 fsl,pins = <
647 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
648 >;
649 };
650};